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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/spi/spi-atmel.c
....@@ -1,11 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Driver for Atmel AT32 and AT91 SPI Controllers
34  *
45  * Copyright (C) 2006 Atmel Corporation
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 
118 #include <linux/kernel.h>
....@@ -19,14 +16,13 @@
1916 #include <linux/interrupt.h>
2017 #include <linux/spi/spi.h>
2118 #include <linux/slab.h>
22
-#include <linux/platform_data/dma-atmel.h>
2319 #include <linux/of.h>
2420 
2521 #include <linux/io.h>
26
-#include <linux/gpio.h>
27
-#include <linux/of_gpio.h>
22
+#include <linux/gpio/consumer.h>
2823 #include <linux/pinctrl/consumer.h>
2924 #include <linux/pm_runtime.h>
25
+#include <trace/events/spi.h>
3026 
3127 /* SPI register offsets */
3228 #define SPI_CR					0x0000
....@@ -225,37 +221,13 @@
225221 	  | SPI_BF(name, value))
226222 
227223 /* Register access macros */
228
-#ifdef CONFIG_AVR32
229
-#define spi_readl(port, reg) \
230
-	__raw_readl((port)->regs + SPI_##reg)
231
-#define spi_writel(port, reg, value) \
232
-	__raw_writel((value), (port)->regs + SPI_##reg)
233
-
234
-#define spi_readw(port, reg) \
235
-	__raw_readw((port)->regs + SPI_##reg)
236
-#define spi_writew(port, reg, value) \
237
-	__raw_writew((value), (port)->regs + SPI_##reg)
238
-
239
-#define spi_readb(port, reg) \
240
-	__raw_readb((port)->regs + SPI_##reg)
241
-#define spi_writeb(port, reg, value) \
242
-	__raw_writeb((value), (port)->regs + SPI_##reg)
243
-#else
244224 #define spi_readl(port, reg) \
245225 	readl_relaxed((port)->regs + SPI_##reg)
246226 #define spi_writel(port, reg, value) \
247227 	writel_relaxed((value), (port)->regs + SPI_##reg)
248
-
249
-#define spi_readw(port, reg) \
250
-	readw_relaxed((port)->regs + SPI_##reg)
251228 #define spi_writew(port, reg, value) \
252229 	writew_relaxed((value), (port)->regs + SPI_##reg)
253230 
254
-#define spi_readb(port, reg) \
255
-	readb_relaxed((port)->regs + SPI_##reg)
256
-#define spi_writeb(port, reg, value) \
257
-	writeb_relaxed((value), (port)->regs + SPI_##reg)
258
-#endif
259231 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
260232  * cache operations; better heuristics consider wordsize and bitrate.
261233  */
....@@ -302,16 +274,16 @@
302274 
303275 	bool			use_dma;
304276 	bool			use_pdc;
305
-	bool			use_cs_gpios;
306277 
307278 	bool			keep_cs;
308279 
309280 	u32			fifo_size;
281
+	u8			native_cs_free;
282
+	u8			native_cs_for_gpio;
310283 };
311284 
312285 /* Controller-specific per-slave state */
313286 struct atmel_spi_device {
314
-	unsigned int		npcs_pin;
315287 	u32			csr;
316288 };
317289 
....@@ -338,11 +310,9 @@
338310  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
339311  * controllers have CSAAT and friends.
340312  *
341
- * Since the CSAAT functionality is a bit weird on newer controllers as
342
- * well, we use GPIO to control nCSx pins on all controllers, updating
343
- * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
344
- * support active-high chipselects despite the controller's belief that
345
- * only active-low devices/systems exists.
313
+ * Even controller newer than ar91rm9200, using GPIOs can make sens as
314
+ * it lets us support active-high chipselects despite the controller's
315
+ * belief that only active-low devices/systems exists.
346316  *
347317  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
348318  * right when driven with GPIO.  ("Mode Fault does not allow more than one
....@@ -354,31 +324,36 @@
354324 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
355325 {
356326 	struct atmel_spi_device *asd = spi->controller_state;
357
-	unsigned active = spi->mode & SPI_CS_HIGH;
327
+	int chip_select;
358328 	u32 mr;
359329 
330
+	if (spi->cs_gpiod)
331
+		chip_select = as->native_cs_for_gpio;
332
+	else
333
+		chip_select = spi->chip_select;
334
+
360335 	if (atmel_spi_is_v2(as)) {
361
-		spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
336
+		spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
362337 		/* For the low SPI version, there is a issue that PDC transfer
363338 		 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
364339 		 */
365340 		spi_writel(as, CSR0, asd->csr);
366341 		if (as->caps.has_wdrbt) {
367342 			spi_writel(as, MR,
368
-					SPI_BF(PCS, ~(0x01 << spi->chip_select))
343
+					SPI_BF(PCS, ~(0x01 << chip_select))
369344 					| SPI_BIT(WDRBT)
370345 					| SPI_BIT(MODFDIS)
371346 					| SPI_BIT(MSTR));
372347 		} else {
373348 			spi_writel(as, MR,
374
-					SPI_BF(PCS, ~(0x01 << spi->chip_select))
349
+					SPI_BF(PCS, ~(0x01 << chip_select))
375350 					| SPI_BIT(MODFDIS)
376351 					| SPI_BIT(MSTR));
377352 		}
378353 
379354 		mr = spi_readl(as, MR);
380
-		if (as->use_cs_gpios)
381
-			gpio_set_value(asd->npcs_pin, active);
355
+		if (spi->cs_gpiod)
356
+			gpiod_set_value(spi->cs_gpiod, 1);
382357 	} else {
383358 		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
384359 		int i;
....@@ -393,40 +368,40 @@
393368 		}
394369 
395370 		mr = spi_readl(as, MR);
396
-		mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
397
-		if (as->use_cs_gpios && spi->chip_select != 0)
398
-			gpio_set_value(asd->npcs_pin, active);
371
+		mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
372
+		if (spi->cs_gpiod)
373
+			gpiod_set_value(spi->cs_gpiod, 1);
399374 		spi_writel(as, MR, mr);
400375 	}
401376 
402
-	dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
403
-			asd->npcs_pin, active ? " (high)" : "",
404
-			mr);
377
+	dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
405378 }
406379 
407380 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
408381 {
409
-	struct atmel_spi_device *asd = spi->controller_state;
410
-	unsigned active = spi->mode & SPI_CS_HIGH;
382
+	int chip_select;
411383 	u32 mr;
384
+
385
+	if (spi->cs_gpiod)
386
+		chip_select = as->native_cs_for_gpio;
387
+	else
388
+		chip_select = spi->chip_select;
412389 
413390 	/* only deactivate *this* device; sometimes transfers to
414391 	 * another device may be active when this routine is called.
415392 	 */
416393 	mr = spi_readl(as, MR);
417
-	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
394
+	if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
418395 		mr = SPI_BFINS(PCS, 0xf, mr);
419396 		spi_writel(as, MR, mr);
420397 	}
421398 
422
-	dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
423
-			asd->npcs_pin, active ? " (low)" : "",
424
-			mr);
399
+	dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
425400 
426
-	if (!as->use_cs_gpios)
401
+	if (!spi->cs_gpiod)
427402 		spi_writel(as, CR, SPI_BIT(LASTXFER));
428
-	else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
429
-		gpio_set_value(asd->npcs_pin, !active);
403
+	else
404
+		gpiod_set_value(spi->cs_gpiod, 0);
430405 }
431406 
432407 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
....@@ -535,29 +510,21 @@
535510 	dma_cap_zero(mask);
536511 	dma_cap_set(DMA_SLAVE, mask);
537512 
538
-	master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
513
+	master->dma_tx = dma_request_chan(dev, "tx");
539514 	if (IS_ERR(master->dma_tx)) {
540
-		err = PTR_ERR(master->dma_tx);
541
-		if (err == -EPROBE_DEFER) {
542
-			dev_warn(dev, "no DMA channel available at the moment\n");
543
-			goto error_clear;
544
-		}
545
-		dev_err(dev,
546
-			"DMA TX channel not available, SPI unable to use DMA\n");
547
-		err = -EBUSY;
515
+		err = dev_err_probe(dev, PTR_ERR(master->dma_tx),
516
+				    "No TX DMA channel, DMA is disabled\n");
548517 		goto error_clear;
549518 	}
550519 
551
-	/*
552
-	 * No reason to check EPROBE_DEFER here since we have already requested
553
-	 * tx channel. If it fails here, it's for another reason.
554
-	 */
555
-	master->dma_rx = dma_request_slave_channel(dev, "rx");
556
-
557
-	if (!master->dma_rx) {
558
-		dev_err(dev,
559
-			"DMA RX channel not available, SPI unable to use DMA\n");
560
-		err = -EBUSY;
520
+	master->dma_rx = dma_request_chan(dev, "rx");
521
+	if (IS_ERR(master->dma_rx)) {
522
+		err = PTR_ERR(master->dma_rx);
523
+		/*
524
+		 * No reason to check EPROBE_DEFER here since we have already
525
+		 * requested tx channel.
526
+		 */
527
+		dev_err(dev, "No RX DMA channel, DMA is disabled\n");
561528 		goto error;
562529 	}
563530 
....@@ -572,7 +539,7 @@
572539 
573540 	return 0;
574541 error:
575
-	if (master->dma_rx)
542
+	if (!IS_ERR(master->dma_rx))
576543 		dma_release_channel(master->dma_rx);
577544 	if (!IS_ERR(master->dma_tx))
578545 		dma_release_channel(master->dma_tx);
....@@ -737,6 +704,7 @@
737704 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
738705 				struct spi_transfer *xfer,
739706 				u32 *plen)
707
+	__must_hold(&as->lock)
740708 {
741709 	struct atmel_spi	*as = spi_master_get_devdata(master);
742710 	struct dma_chan		*rxchan = master->dma_rx;
....@@ -852,6 +820,12 @@
852820 {
853821 	u32			scbr, csr;
854822 	unsigned long		bus_hz;
823
+	int chip_select;
824
+
825
+	if (spi->cs_gpiod)
826
+		chip_select = as->native_cs_for_gpio;
827
+	else
828
+		chip_select = spi->chip_select;
855829 
856830 	/* v1 chips start out at half the peripheral bus speed. */
857831 	bus_hz = as->spi_clk;
....@@ -880,9 +854,10 @@
880854 			xfer->speed_hz, scbr, bus_hz);
881855 		return -EINVAL;
882856 	}
883
-	csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
857
+	csr = spi_readl(as, CSR0 + 4 * chip_select);
884858 	csr = SPI_BFINS(SCBR, scbr, csr);
885
-	spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
859
+	spi_writel(as, CSR0 + 4 * chip_select, csr);
860
+	xfer->effective_speed_hz = bus_hz / scbr;
886861 
887862 	return 0;
888863 }
....@@ -1181,46 +1156,105 @@
11811156 	return ret;
11821157 }
11831158 
1159
+static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1160
+{
1161
+	struct spi_delay *delay = &spi->word_delay;
1162
+	u32 value = delay->value;
1163
+
1164
+	switch (delay->unit) {
1165
+	case SPI_DELAY_UNIT_NSECS:
1166
+		value /= 1000;
1167
+		break;
1168
+	case SPI_DELAY_UNIT_USECS:
1169
+		break;
1170
+	default:
1171
+		return -EINVAL;
1172
+	}
1173
+
1174
+	return (as->spi_clk / 1000000 * value) >> 5;
1175
+}
1176
+
1177
+static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1178
+{
1179
+	int i;
1180
+	struct spi_master *master = platform_get_drvdata(as->pdev);
1181
+
1182
+	if (!as->native_cs_free)
1183
+		return; /* already initialized */
1184
+
1185
+	if (!master->cs_gpiods)
1186
+		return; /* No CS GPIO */
1187
+
1188
+	/*
1189
+	 * On the first version of the controller (AT91RM9200), CS0
1190
+	 * can't be used associated with GPIO
1191
+	 */
1192
+	if (atmel_spi_is_v2(as))
1193
+		i = 0;
1194
+	else
1195
+		i = 1;
1196
+
1197
+	for (; i < 4; i++)
1198
+		if (master->cs_gpiods[i])
1199
+			as->native_cs_free |= BIT(i);
1200
+
1201
+	if (as->native_cs_free)
1202
+		as->native_cs_for_gpio = ffs(as->native_cs_free);
1203
+}
1204
+
11841205 static int atmel_spi_setup(struct spi_device *spi)
11851206 {
11861207 	struct atmel_spi	*as;
11871208 	struct atmel_spi_device	*asd;
11881209 	u32			csr;
11891210 	unsigned int		bits = spi->bits_per_word;
1190
-	unsigned int		npcs_pin;
1211
+	int chip_select;
1212
+	int			word_delay_csr;
11911213 
11921214 	as = spi_master_get_devdata(spi->master);
11931215 
11941216 	/* see notes above re chipselect */
1195
-	if (!as->use_cs_gpios && (spi->mode & SPI_CS_HIGH)) {
1217
+	if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
11961218 		dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
11971219 		return -EINVAL;
11981220 	}
1221
+
1222
+	/* Setup() is called during spi_register_controller(aka
1223
+	 * spi_register_master) but after all membmers of the cs_gpiod
1224
+	 * array have been filled, so we can looked for which native
1225
+	 * CS will be free for using with GPIO
1226
+	 */
1227
+	initialize_native_cs_for_gpio(as);
1228
+
1229
+	if (spi->cs_gpiod && as->native_cs_free) {
1230
+		dev_err(&spi->dev,
1231
+			"No native CS available to support this GPIO CS\n");
1232
+		return -EBUSY;
1233
+	}
1234
+
1235
+	if (spi->cs_gpiod)
1236
+		chip_select = as->native_cs_for_gpio;
1237
+	else
1238
+		chip_select = spi->chip_select;
11991239 
12001240 	csr = SPI_BF(BITS, bits - 8);
12011241 	if (spi->mode & SPI_CPOL)
12021242 		csr |= SPI_BIT(CPOL);
12031243 	if (!(spi->mode & SPI_CPHA))
12041244 		csr |= SPI_BIT(NCPHA);
1205
-	if (!as->use_cs_gpios)
1245
+
1246
+	if (!spi->cs_gpiod)
12061247 		csr |= SPI_BIT(CSAAT);
1207
-
1208
-	/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1209
-	 *
1210
-	 * DLYBCT would add delays between words, slowing down transfers.
1211
-	 * It could potentially be useful to cope with DMA bottlenecks, but
1212
-	 * in those cases it's probably best to just use a lower bitrate.
1213
-	 */
12141248 	csr |= SPI_BF(DLYBS, 0);
1215
-	csr |= SPI_BF(DLYBCT, 0);
12161249 
1217
-	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
1218
-	npcs_pin = (unsigned long)spi->controller_data;
1250
+	word_delay_csr = atmel_word_delay_csr(spi, as);
1251
+	if (word_delay_csr < 0)
1252
+		return word_delay_csr;
12191253 
1220
-	if (!as->use_cs_gpios)
1221
-		npcs_pin = spi->chip_select;
1222
-	else if (gpio_is_valid(spi->cs_gpio))
1223
-		npcs_pin = spi->cs_gpio;
1254
+	/* DLYBCT adds delays between words.  This is useful for slow devices
1255
+	 * that need a bit of time to setup the next transfer.
1256
+	 */
1257
+	csr |= SPI_BF(DLYBCT, word_delay_csr);
12241258 
12251259 	asd = spi->controller_state;
12261260 	if (!asd) {
....@@ -1228,11 +1262,6 @@
12281262 		if (!asd)
12291263 			return -ENOMEM;
12301264 
1231
-		if (as->use_cs_gpios)
1232
-			gpio_direction_output(npcs_pin,
1233
-					      !(spi->mode & SPI_CS_HIGH));
1234
-
1235
-		asd->npcs_pin = npcs_pin;
12361265 		spi->controller_state = asd;
12371266 	}
12381267 
....@@ -1243,7 +1272,7 @@
12431272 		bits, spi->mode, spi->chip_select, csr);
12441273 
12451274 	if (!atmel_spi_is_v2(as))
1246
-		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1275
+		spi_writel(as, CSR0 + 4 * chip_select, csr);
12471276 
12481277 	return 0;
12491278 }
....@@ -1372,8 +1401,7 @@
13721401 		&& as->use_pdc)
13731402 		atmel_spi_dma_unmap_xfer(master, xfer);
13741403 
1375
-	if (xfer->delay_usecs)
1376
-		udelay(xfer->delay_usecs);
1404
+	spi_transfer_delay_exec(xfer);
13771405 
13781406 	if (xfer->cs_change) {
13791407 		if (list_is_last(&xfer->transfer_list,
....@@ -1411,9 +1439,13 @@
14111439 	msg->actual_length = 0;
14121440 
14131441 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1442
+		trace_spi_transfer_start(msg, xfer);
1443
+
14141444 		ret = atmel_spi_one_transfer(master, msg, xfer);
14151445 		if (ret)
14161446 			goto msg_done;
1447
+
1448
+		trace_spi_transfer_stop(msg, xfer);
14171449 	}
14181450 
14191451 	if (as->use_pdc)
....@@ -1467,41 +1499,6 @@
14671499 	as->caps.has_pdc_support = version < 0x212;
14681500 }
14691501 
1470
-/*-------------------------------------------------------------------------*/
1471
-static int atmel_spi_gpio_cs(struct platform_device *pdev)
1472
-{
1473
-	struct spi_master	*master = platform_get_drvdata(pdev);
1474
-	struct atmel_spi	*as = spi_master_get_devdata(master);
1475
-	struct device_node	*np = master->dev.of_node;
1476
-	int			i;
1477
-	int			ret = 0;
1478
-	int			nb = 0;
1479
-
1480
-	if (!as->use_cs_gpios)
1481
-		return 0;
1482
-
1483
-	if (!np)
1484
-		return 0;
1485
-
1486
-	nb = of_gpio_named_count(np, "cs-gpios");
1487
-	for (i = 0; i < nb; i++) {
1488
-		int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1489
-						"cs-gpios", i);
1490
-
1491
-		if (cs_gpio == -EPROBE_DEFER)
1492
-			return cs_gpio;
1493
-
1494
-		if (gpio_is_valid(cs_gpio)) {
1495
-			ret = devm_gpio_request(&pdev->dev, cs_gpio,
1496
-						dev_name(&pdev->dev));
1497
-			if (ret)
1498
-				return ret;
1499
-		}
1500
-	}
1501
-
1502
-	return 0;
1503
-}
1504
-
15051502 static void atmel_spi_init(struct atmel_spi *as)
15061503 {
15071504 	spi_writel(as, CR, SPI_BIT(SWRST));
....@@ -1548,17 +1545,17 @@
15481545 		return PTR_ERR(clk);
15491546 
15501547 	/* setup spi core then atmel-specific driver state */
1551
-	ret = -ENOMEM;
15521548 	master = spi_alloc_master(&pdev->dev, sizeof(*as));
15531549 	if (!master)
1554
-		goto out_free;
1550
+		return -ENOMEM;
15551551 
15561552 	/* the spi->mode bits understood by this driver: */
1553
+	master->use_gpio_descriptors = true;
15571554 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
15581555 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
15591556 	master->dev.of_node = pdev->dev.of_node;
15601557 	master->bus_num = pdev->id;
1561
-	master->num_chipselect = master->dev.of_node ? 0 : 4;
1558
+	master->num_chipselect = 4;
15621559 	master->setup = atmel_spi_setup;
15631560 	master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
15641561 	master->transfer_one_message = atmel_spi_transfer_one_message;
....@@ -1585,18 +1582,6 @@
15851582 	init_completion(&as->xfer_completion);
15861583 
15871584 	atmel_get_caps(as);
1588
-
1589
-	as->use_cs_gpios = true;
1590
-	if (atmel_spi_is_v2(as) &&
1591
-	    pdev->dev.of_node &&
1592
-	    !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1593
-		as->use_cs_gpios = false;
1594
-		master->num_chipselect = 4;
1595
-	}
1596
-
1597
-	ret = atmel_spi_gpio_cs(pdev);
1598
-	if (ret)
1599
-		goto out_unmap_regs;
16001585 
16011586 	as->use_dma = false;
16021587 	as->use_pdc = false;
....@@ -1691,7 +1676,6 @@
16911676 	clk_disable_unprepare(clk);
16921677 out_free_irq:
16931678 out_unmap_regs:
1694
-out_free:
16951679 	spi_master_put(master);
16961680 	return ret;
16971681 }
....@@ -1761,10 +1745,8 @@
17611745 
17621746 	/* Stop the queue running */
17631747 	ret = spi_master_suspend(master);
1764
-	if (ret) {
1765
-		dev_warn(dev, "cannot suspend master\n");
1748
+	if (ret)
17661749 		return ret;
1767
-	}
17681750 
17691751 	if (!pm_runtime_suspended(dev))
17701752 		atmel_spi_runtime_suspend(dev);
....@@ -1793,11 +1775,7 @@
17931775 	}
17941776 
17951777 	/* Start the queue running */
1796
-	ret = spi_master_resume(master);
1797
-	if (ret)
1798
-		dev_err(dev, "problem starting queue (%d)\n", ret);
1799
-
1800
-	return ret;
1778
+	return spi_master_resume(master);
18011779 }
18021780 #endif
18031781 
....@@ -1811,20 +1789,18 @@
18111789 #define ATMEL_SPI_PM_OPS	NULL
18121790 #endif
18131791 
1814
-#if defined(CONFIG_OF)
18151792 static const struct of_device_id atmel_spi_dt_ids[] = {
18161793 	{ .compatible = "atmel,at91rm9200-spi" },
18171794 	{ /* sentinel */ }
18181795 };
18191796 
18201797 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1821
-#endif
18221798 
18231799 static struct platform_driver atmel_spi_driver = {
18241800 	.driver		= {
18251801 		.name	= "atmel_spi",
18261802 		.pm	= ATMEL_SPI_PM_OPS,
1827
-		.of_match_table	= of_match_ptr(atmel_spi_dt_ids),
1803
+		.of_match_table	= atmel_spi_dt_ids,
18281804 	},
18291805 	.probe		= atmel_spi_probe,
18301806 	.remove		= atmel_spi_remove,