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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/spi/spi-ath79.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
34  *
....@@ -5,11 +6,6 @@
56  *
67  * This driver has been based on the spi-gpio.c:
78  *	Copyright (C) 2006,2008 David Brownell
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as
11
- * published by the Free Software Foundation.
12
- *
139  */
1410 
1511 #include <linux/kernel.h>
....@@ -21,17 +17,25 @@
2117 #include <linux/spi/spi.h>
2218 #include <linux/spi/spi_bitbang.h>
2319 #include <linux/bitops.h>
24
-#include <linux/gpio.h>
2520 #include <linux/clk.h>
2621 #include <linux/err.h>
27
-
28
-#include <asm/mach-ath79/ar71xx_regs.h>
29
-#include <asm/mach-ath79/ath79_spi_platform.h>
22
+#include <linux/platform_data/spi-ath79.h>
3023 
3124 #define DRV_NAME	"ath79-spi"
3225 
3326 #define ATH79_SPI_RRW_DELAY_FACTOR	12000
3427 #define MHZ				(1000 * 1000)
28
+
29
+#define AR71XX_SPI_REG_FS		0x00	/* Function Select */
30
+#define AR71XX_SPI_REG_CTRL		0x04	/* SPI Control */
31
+#define AR71XX_SPI_REG_IOC		0x08	/* SPI I/O Control */
32
+#define AR71XX_SPI_REG_RDS		0x0c	/* Read Data Shift */
33
+
34
+#define AR71XX_SPI_FS_GPIO		BIT(0)	/* Enable GPIO mode */
35
+
36
+#define AR71XX_SPI_IOC_DO		BIT(0)	/* Data Out pin */
37
+#define AR71XX_SPI_IOC_CLK		BIT(8)	/* CLK pin */
38
+#define AR71XX_SPI_IOC_CS(n)		BIT(16 + (n))
3539 
3640 struct ath79_spi {
3741 	struct spi_bitbang	bitbang;
....@@ -67,31 +71,14 @@
6771 {
6872 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
6973 	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
74
+	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
7075 
71
-	if (is_active) {
72
-		/* set initial clock polarity */
73
-		if (spi->mode & SPI_CPOL)
74
-			sp->ioc_base |= AR71XX_SPI_IOC_CLK;
75
-		else
76
-			sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
76
+	if (cs_high)
77
+		sp->ioc_base |= cs_bit;
78
+	else
79
+		sp->ioc_base &= ~cs_bit;
7780 
78
-		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
79
-	}
80
-
81
-	if (gpio_is_valid(spi->cs_gpio)) {
82
-		/* SPI is normally active-low */
83
-		gpio_set_value_cansleep(spi->cs_gpio, cs_high);
84
-	} else {
85
-		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
86
-
87
-		if (cs_high)
88
-			sp->ioc_base |= cs_bit;
89
-		else
90
-			sp->ioc_base &= ~cs_bit;
91
-
92
-		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
93
-	}
94
-
81
+	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
9582 }
9683 
9784 static void ath79_spi_enable(struct ath79_spi *sp)
....@@ -103,6 +90,9 @@
10390 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
10491 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
10592 
93
+	/* clear clk and mosi in the base state */
94
+	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
95
+
10696 	/* TODO: setup speed? */
10797 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
10898 }
....@@ -113,66 +103,6 @@
113103 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
114104 	/* disable GPIO mode */
115105 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
116
-}
117
-
118
-static int ath79_spi_setup_cs(struct spi_device *spi)
119
-{
120
-	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
121
-	int status;
122
-
123
-	status = 0;
124
-	if (gpio_is_valid(spi->cs_gpio)) {
125
-		unsigned long flags;
126
-
127
-		flags = GPIOF_DIR_OUT;
128
-		if (spi->mode & SPI_CS_HIGH)
129
-			flags |= GPIOF_INIT_LOW;
130
-		else
131
-			flags |= GPIOF_INIT_HIGH;
132
-
133
-		status = gpio_request_one(spi->cs_gpio, flags,
134
-					  dev_name(&spi->dev));
135
-	} else {
136
-		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
137
-
138
-		if (spi->mode & SPI_CS_HIGH)
139
-			sp->ioc_base &= ~cs_bit;
140
-		else
141
-			sp->ioc_base |= cs_bit;
142
-
143
-		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
144
-	}
145
-
146
-	return status;
147
-}
148
-
149
-static void ath79_spi_cleanup_cs(struct spi_device *spi)
150
-{
151
-	if (gpio_is_valid(spi->cs_gpio))
152
-		gpio_free(spi->cs_gpio);
153
-}
154
-
155
-static int ath79_spi_setup(struct spi_device *spi)
156
-{
157
-	int status = 0;
158
-
159
-	if (!spi->controller_state) {
160
-		status = ath79_spi_setup_cs(spi);
161
-		if (status)
162
-			return status;
163
-	}
164
-
165
-	status = spi_bitbang_setup(spi);
166
-	if (status && !spi->controller_state)
167
-		ath79_spi_cleanup_cs(spi);
168
-
169
-	return status;
170
-}
171
-
172
-static void ath79_spi_cleanup(struct spi_device *spi)
173
-{
174
-	ath79_spi_cleanup_cs(spi);
175
-	spi_bitbang_cleanup(spi);
176106 }
177107 
178108 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
....@@ -209,7 +139,6 @@
209139 	struct spi_master *master;
210140 	struct ath79_spi *sp;
211141 	struct ath79_spi_platform_data *pdata;
212
-	struct resource	*r;
213142 	unsigned long rate;
214143 	int ret;
215144 
....@@ -225,9 +154,9 @@
225154 
226155 	pdata = dev_get_platdata(&pdev->dev);
227156 
157
+	master->use_gpio_descriptors = true;
228158 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
229
-	master->setup = ath79_spi_setup;
230
-	master->cleanup = ath79_spi_cleanup;
159
+	master->flags = SPI_MASTER_GPIO_SS;
231160 	if (pdata) {
232161 		master->bus_num = pdata->bus_num;
233162 		master->num_chipselect = pdata->num_chipselect;
....@@ -236,11 +165,9 @@
236165 	sp->bitbang.master = master;
237166 	sp->bitbang.chipselect = ath79_spi_chipselect;
238167 	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
239
-	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
240168 	sp->bitbang.flags = SPI_CS_HIGH;
241169 
242
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
243
-	sp->base = devm_ioremap_resource(&pdev->dev, r);
170
+	sp->base = devm_platform_ioremap_resource(pdev, 0);
244171 	if (IS_ERR(sp->base)) {
245172 		ret = PTR_ERR(sp->base);
246173 		goto err_put_master;