| .. | .. |
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| 41 | 41 | #include <linux/slab.h> |
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| 42 | 42 | #include "pm8001_sas.h" |
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| 43 | 43 | #include "pm8001_chips.h" |
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| 44 | +#include "pm80xx_hwi.h" |
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| 45 | + |
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| 46 | +static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; |
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| 47 | +module_param(logging_level, ulong, 0644); |
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| 48 | +MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); |
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| 49 | + |
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| 50 | +static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; |
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| 51 | +module_param(link_rate, ulong, 0644); |
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| 52 | +MODULE_PARM_DESC(link_rate, "Enable link rate.\n" |
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| 53 | + " 1: Link rate 1.5G\n" |
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| 54 | + " 2: Link rate 3.0G\n" |
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| 55 | + " 4: Link rate 6.0G\n" |
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| 56 | + " 8: Link rate 12.0G\n"); |
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| 44 | 57 | |
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| 45 | 58 | static struct scsi_transport_template *pm8001_stt; |
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| 59 | +static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *); |
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| 46 | 60 | |
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| 47 | | -/** |
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| 61 | +/* |
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| 48 | 62 | * chip info structure to identify chip key functionality as |
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| 49 | 63 | * encryption available/not, no of ports, hw specific function ref |
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| 50 | 64 | */ |
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| .. | .. |
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| 67 | 81 | |
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| 68 | 82 | struct workqueue_struct *pm8001_wq; |
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| 69 | 83 | |
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| 70 | | -/** |
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| 84 | +/* |
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| 71 | 85 | * The main structure which LLDD must register for scsi core. |
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| 72 | 86 | */ |
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| 73 | 87 | static struct scsi_host_template pm8001_sht = { |
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| 74 | 88 | .module = THIS_MODULE, |
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| 75 | 89 | .name = DRV_NAME, |
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| 76 | 90 | .queuecommand = sas_queuecommand, |
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| 91 | + .dma_need_drain = ata_scsi_dma_need_drain, |
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| 77 | 92 | .target_alloc = sas_target_alloc, |
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| 78 | 93 | .slave_configure = sas_slave_configure, |
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| 79 | 94 | .scan_finished = pm8001_scan_finished, |
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| .. | .. |
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| 82 | 97 | .bios_param = sas_bios_param, |
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| 83 | 98 | .can_queue = 1, |
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| 84 | 99 | .this_id = -1, |
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| 85 | | - .sg_tablesize = SG_ALL, |
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| 100 | + .sg_tablesize = PM8001_MAX_DMA_SG, |
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| 86 | 101 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, |
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| 87 | | - .use_clustering = ENABLE_CLUSTERING, |
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| 88 | 102 | .eh_device_reset_handler = sas_eh_device_reset_handler, |
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| 89 | 103 | .eh_target_reset_handler = sas_eh_target_reset_handler, |
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| 90 | 104 | .slave_alloc = sas_slave_alloc, |
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| 91 | 105 | .target_destroy = sas_target_destroy, |
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| 92 | 106 | .ioctl = sas_ioctl, |
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| 107 | +#ifdef CONFIG_COMPAT |
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| 108 | + .compat_ioctl = sas_ioctl, |
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| 109 | +#endif |
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| 93 | 110 | .shost_attrs = pm8001_host_attrs, |
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| 94 | 111 | .track_queue_depth = 1, |
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| 95 | 112 | }; |
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| 96 | 113 | |
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| 97 | | -/** |
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| 114 | +/* |
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| 98 | 115 | * Sas layer call this function to execute specific task. |
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| 99 | 116 | */ |
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| 100 | 117 | static struct sas_domain_function_template pm8001_transport_ops = { |
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| .. | .. |
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| 114 | 131 | }; |
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| 115 | 132 | |
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| 116 | 133 | /** |
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| 117 | | - *pm8001_phy_init - initiate our adapter phys |
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| 118 | | - *@pm8001_ha: our hba structure. |
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| 119 | | - *@phy_id: phy id. |
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| 134 | + * pm8001_phy_init - initiate our adapter phys |
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| 135 | + * @pm8001_ha: our hba structure. |
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| 136 | + * @phy_id: phy id. |
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| 120 | 137 | */ |
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| 121 | 138 | static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) |
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| 122 | 139 | { |
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| 123 | 140 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; |
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| 124 | 141 | struct asd_sas_phy *sas_phy = &phy->sas_phy; |
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| 125 | | - phy->phy_state = 0; |
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| 142 | + phy->phy_state = PHY_LINK_DISABLE; |
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| 126 | 143 | phy->pm8001_ha = pm8001_ha; |
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| 127 | 144 | sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; |
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| 128 | 145 | sas_phy->class = SAS; |
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| .. | .. |
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| 140 | 157 | } |
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| 141 | 158 | |
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| 142 | 159 | /** |
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| 143 | | - *pm8001_free - free hba |
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| 144 | | - *@pm8001_ha: our hba structure. |
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| 145 | | - * |
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| 160 | + * pm8001_free - free hba |
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| 161 | + * @pm8001_ha: our hba structure. |
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| 146 | 162 | */ |
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| 147 | 163 | static void pm8001_free(struct pm8001_hba_info *pm8001_ha) |
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| 148 | 164 | { |
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| .. | .. |
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| 153 | 169 | |
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| 154 | 170 | for (i = 0; i < USI_MAX_MEMCNT; i++) { |
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| 155 | 171 | if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { |
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| 156 | | - pci_free_consistent(pm8001_ha->pdev, |
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| 172 | + dma_free_coherent(&pm8001_ha->pdev->dev, |
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| 157 | 173 | (pm8001_ha->memoryMap.region[i].total_len + |
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| 158 | 174 | pm8001_ha->memoryMap.region[i].alignment), |
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| 159 | 175 | pm8001_ha->memoryMap.region[i].virt_ptr, |
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| .. | .. |
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| 190 | 206 | * pm8001_interrupt_handler_msix - main MSIX interrupt handler. |
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| 191 | 207 | * It obtains the vector number and calls the equivalent bottom |
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| 192 | 208 | * half or services directly. |
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| 209 | + * @irq: interrupt number |
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| 193 | 210 | * @opaque: the passed outbound queue/vector. Host structure is |
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| 194 | 211 | * retrieved from the same. |
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| 195 | 212 | */ |
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| .. | .. |
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| 203 | 220 | |
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| 204 | 221 | if (unlikely(!pm8001_ha)) |
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| 205 | 222 | return IRQ_NONE; |
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| 206 | | - if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) |
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| 223 | + if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) |
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| 207 | 224 | return IRQ_NONE; |
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| 208 | 225 | #ifdef PM8001_USE_TASKLET |
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| 209 | 226 | tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); |
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| .. | .. |
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| 215 | 232 | |
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| 216 | 233 | /** |
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| 217 | 234 | * pm8001_interrupt_handler_intx - main INTx interrupt handler. |
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| 235 | + * @irq: interrupt number |
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| 218 | 236 | * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. |
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| 219 | 237 | */ |
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| 220 | 238 | |
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| .. | .. |
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| 226 | 244 | pm8001_ha = sha->lldd_ha; |
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| 227 | 245 | if (unlikely(!pm8001_ha)) |
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| 228 | 246 | return IRQ_NONE; |
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| 229 | | - if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) |
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| 247 | + if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) |
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| 230 | 248 | return IRQ_NONE; |
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| 231 | 249 | |
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| 232 | 250 | #ifdef PM8001_USE_TASKLET |
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| .. | .. |
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| 237 | 255 | return ret; |
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| 238 | 256 | } |
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| 239 | 257 | |
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| 258 | +static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); |
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| 259 | +static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); |
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| 260 | + |
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| 240 | 261 | /** |
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| 241 | 262 | * pm8001_alloc - initiate our hba structure and 6 DMAs area. |
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| 242 | | - * @pm8001_ha:our hba structure. |
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| 243 | | - * |
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| 263 | + * @pm8001_ha: our hba structure. |
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| 264 | + * @ent: PCI device ID structure to match on |
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| 244 | 265 | */ |
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| 245 | 266 | static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, |
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| 246 | 267 | const struct pci_device_id *ent) |
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| 247 | 268 | { |
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| 248 | | - int i; |
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| 269 | + int i, count = 0, rc = 0; |
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| 270 | + u32 ci_offset, ib_offset, ob_offset, pi_offset; |
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| 271 | + struct inbound_queue_table *circularQ; |
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| 272 | + |
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| 249 | 273 | spin_lock_init(&pm8001_ha->lock); |
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| 250 | 274 | spin_lock_init(&pm8001_ha->bitmap_lock); |
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| 251 | | - PM8001_INIT_DBG(pm8001_ha, |
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| 252 | | - pm8001_printk("pm8001_alloc: PHY:%x\n", |
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| 253 | | - pm8001_ha->chip->n_phy)); |
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| 275 | + pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", |
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| 276 | + pm8001_ha->chip->n_phy); |
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| 277 | + |
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| 278 | + /* Setup Interrupt */ |
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| 279 | + rc = pm8001_setup_irq(pm8001_ha); |
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| 280 | + if (rc) { |
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| 281 | + pm8001_dbg(pm8001_ha, FAIL, |
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| 282 | + "pm8001_setup_irq failed [ret: %d]\n", rc); |
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| 283 | + goto err_out; |
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| 284 | + } |
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| 285 | + /* Request Interrupt */ |
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| 286 | + rc = pm8001_request_irq(pm8001_ha); |
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| 287 | + if (rc) |
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| 288 | + goto err_out; |
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| 289 | + |
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| 290 | + count = pm8001_ha->max_q_num; |
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| 291 | + /* Queues are chosen based on the number of cores/msix availability */ |
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| 292 | + ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; |
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| 293 | + ci_offset = pm8001_ha->ci_offset = ib_offset + count; |
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| 294 | + ob_offset = pm8001_ha->ob_offset = ci_offset + count; |
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| 295 | + pi_offset = pm8001_ha->pi_offset = ob_offset + count; |
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| 296 | + pm8001_ha->max_memcnt = pi_offset + count; |
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| 297 | + |
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| 254 | 298 | for (i = 0; i < pm8001_ha->chip->n_phy; i++) { |
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| 255 | 299 | pm8001_phy_init(pm8001_ha, i); |
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| 256 | 300 | pm8001_ha->port[i].wide_port_phymap = 0; |
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| .. | .. |
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| 259 | 303 | INIT_LIST_HEAD(&pm8001_ha->port[i].list); |
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| 260 | 304 | } |
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| 261 | 305 | |
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| 262 | | - pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); |
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| 263 | | - if (!pm8001_ha->tags) |
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| 264 | | - goto err_out; |
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| 265 | 306 | /* MPI Memory region 1 for AAP Event Log for fw */ |
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| 266 | 307 | pm8001_ha->memoryMap.region[AAP1].num_elements = 1; |
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| 267 | 308 | pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; |
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| .. | .. |
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| 274 | 315 | pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; |
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| 275 | 316 | pm8001_ha->memoryMap.region[IOP].alignment = 32; |
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| 276 | 317 | |
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| 277 | | - for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { |
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| 318 | + for (i = 0; i < count; i++) { |
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| 319 | + circularQ = &pm8001_ha->inbnd_q_tbl[i]; |
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| 320 | + spin_lock_init(&circularQ->iq_lock); |
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| 278 | 321 | /* MPI Memory region 3 for consumer Index of inbound queues */ |
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| 279 | | - pm8001_ha->memoryMap.region[CI+i].num_elements = 1; |
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| 280 | | - pm8001_ha->memoryMap.region[CI+i].element_size = 4; |
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| 281 | | - pm8001_ha->memoryMap.region[CI+i].total_len = 4; |
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| 282 | | - pm8001_ha->memoryMap.region[CI+i].alignment = 4; |
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| 322 | + pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; |
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| 323 | + pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; |
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| 324 | + pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; |
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| 325 | + pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; |
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| 283 | 326 | |
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| 284 | 327 | if ((ent->driver_data) != chip_8001) { |
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| 285 | 328 | /* MPI Memory region 5 inbound queues */ |
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| 286 | | - pm8001_ha->memoryMap.region[IB+i].num_elements = |
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| 329 | + pm8001_ha->memoryMap.region[ib_offset+i].num_elements = |
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| 287 | 330 | PM8001_MPI_QUEUE; |
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| 288 | | - pm8001_ha->memoryMap.region[IB+i].element_size = 128; |
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| 289 | | - pm8001_ha->memoryMap.region[IB+i].total_len = |
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| 331 | + pm8001_ha->memoryMap.region[ib_offset+i].element_size |
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| 332 | + = 128; |
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| 333 | + pm8001_ha->memoryMap.region[ib_offset+i].total_len = |
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| 290 | 334 | PM8001_MPI_QUEUE * 128; |
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| 291 | | - pm8001_ha->memoryMap.region[IB+i].alignment = 128; |
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| 335 | + pm8001_ha->memoryMap.region[ib_offset+i].alignment |
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| 336 | + = 128; |
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| 292 | 337 | } else { |
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| 293 | | - pm8001_ha->memoryMap.region[IB+i].num_elements = |
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| 338 | + pm8001_ha->memoryMap.region[ib_offset+i].num_elements = |
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| 294 | 339 | PM8001_MPI_QUEUE; |
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| 295 | | - pm8001_ha->memoryMap.region[IB+i].element_size = 64; |
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| 296 | | - pm8001_ha->memoryMap.region[IB+i].total_len = |
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| 340 | + pm8001_ha->memoryMap.region[ib_offset+i].element_size |
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| 341 | + = 64; |
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| 342 | + pm8001_ha->memoryMap.region[ib_offset+i].total_len = |
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| 297 | 343 | PM8001_MPI_QUEUE * 64; |
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| 298 | | - pm8001_ha->memoryMap.region[IB+i].alignment = 64; |
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| 344 | + pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; |
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| 299 | 345 | } |
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| 300 | 346 | } |
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| 301 | 347 | |
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| 302 | | - for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { |
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| 348 | + for (i = 0; i < count; i++) { |
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| 303 | 349 | /* MPI Memory region 4 for producer Index of outbound queues */ |
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| 304 | | - pm8001_ha->memoryMap.region[PI+i].num_elements = 1; |
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| 305 | | - pm8001_ha->memoryMap.region[PI+i].element_size = 4; |
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| 306 | | - pm8001_ha->memoryMap.region[PI+i].total_len = 4; |
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| 307 | | - pm8001_ha->memoryMap.region[PI+i].alignment = 4; |
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| 350 | + pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; |
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| 351 | + pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; |
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| 352 | + pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; |
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| 353 | + pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; |
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| 308 | 354 | |
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| 309 | 355 | if (ent->driver_data != chip_8001) { |
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| 310 | 356 | /* MPI Memory region 6 Outbound queues */ |
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| 311 | | - pm8001_ha->memoryMap.region[OB+i].num_elements = |
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| 357 | + pm8001_ha->memoryMap.region[ob_offset+i].num_elements = |
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| 312 | 358 | PM8001_MPI_QUEUE; |
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| 313 | | - pm8001_ha->memoryMap.region[OB+i].element_size = 128; |
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| 314 | | - pm8001_ha->memoryMap.region[OB+i].total_len = |
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| 359 | + pm8001_ha->memoryMap.region[ob_offset+i].element_size |
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| 360 | + = 128; |
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| 361 | + pm8001_ha->memoryMap.region[ob_offset+i].total_len = |
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| 315 | 362 | PM8001_MPI_QUEUE * 128; |
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| 316 | | - pm8001_ha->memoryMap.region[OB+i].alignment = 128; |
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| 363 | + pm8001_ha->memoryMap.region[ob_offset+i].alignment |
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| 364 | + = 128; |
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| 317 | 365 | } else { |
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| 318 | 366 | /* MPI Memory region 6 Outbound queues */ |
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| 319 | | - pm8001_ha->memoryMap.region[OB+i].num_elements = |
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| 367 | + pm8001_ha->memoryMap.region[ob_offset+i].num_elements = |
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| 320 | 368 | PM8001_MPI_QUEUE; |
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| 321 | | - pm8001_ha->memoryMap.region[OB+i].element_size = 64; |
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| 322 | | - pm8001_ha->memoryMap.region[OB+i].total_len = |
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| 369 | + pm8001_ha->memoryMap.region[ob_offset+i].element_size |
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| 370 | + = 64; |
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| 371 | + pm8001_ha->memoryMap.region[ob_offset+i].total_len = |
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| 323 | 372 | PM8001_MPI_QUEUE * 64; |
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| 324 | | - pm8001_ha->memoryMap.region[OB+i].alignment = 64; |
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| 373 | + pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; |
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| 325 | 374 | } |
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| 326 | 375 | |
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| 327 | 376 | } |
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| .. | .. |
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| 329 | 378 | pm8001_ha->memoryMap.region[NVMD].num_elements = 1; |
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| 330 | 379 | pm8001_ha->memoryMap.region[NVMD].element_size = 4096; |
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| 331 | 380 | pm8001_ha->memoryMap.region[NVMD].total_len = 4096; |
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| 332 | | - /* Memory region for devices*/ |
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| 333 | | - pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; |
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| 334 | | - pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * |
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| 335 | | - sizeof(struct pm8001_device); |
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| 336 | | - pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * |
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| 337 | | - sizeof(struct pm8001_device); |
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| 338 | | - |
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| 339 | | - /* Memory region for ccb_info*/ |
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| 340 | | - pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; |
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| 341 | | - pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * |
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| 342 | | - sizeof(struct pm8001_ccb_info); |
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| 343 | | - pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * |
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| 344 | | - sizeof(struct pm8001_ccb_info); |
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| 345 | 381 | |
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| 346 | 382 | /* Memory region for fw flash */ |
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| 347 | 383 | pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; |
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| .. | .. |
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| 350 | 386 | pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; |
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| 351 | 387 | pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; |
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| 352 | 388 | pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; |
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| 353 | | - for (i = 0; i < USI_MAX_MEMCNT; i++) { |
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| 389 | + for (i = 0; i < pm8001_ha->max_memcnt; i++) { |
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| 354 | 390 | if (pm8001_mem_alloc(pm8001_ha->pdev, |
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| 355 | 391 | &pm8001_ha->memoryMap.region[i].virt_ptr, |
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| 356 | 392 | &pm8001_ha->memoryMap.region[i].phys_addr, |
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| .. | .. |
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| 358 | 394 | &pm8001_ha->memoryMap.region[i].phys_addr_lo, |
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| 359 | 395 | pm8001_ha->memoryMap.region[i].total_len, |
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| 360 | 396 | pm8001_ha->memoryMap.region[i].alignment) != 0) { |
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| 361 | | - PM8001_FAIL_DBG(pm8001_ha, |
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| 362 | | - pm8001_printk("Mem%d alloc failed\n", |
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| 363 | | - i)); |
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| 397 | + pm8001_dbg(pm8001_ha, FAIL, |
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| 398 | + "Mem%d alloc failed\n", |
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| 399 | + i); |
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| 364 | 400 | goto err_out; |
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| 365 | 401 | } |
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| 366 | 402 | } |
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| 367 | 403 | |
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| 368 | | - pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; |
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| 404 | + /* Memory region for devices*/ |
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| 405 | + pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES |
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| 406 | + * sizeof(struct pm8001_device), GFP_KERNEL); |
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| 407 | + if (!pm8001_ha->devices) { |
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| 408 | + rc = -ENOMEM; |
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| 409 | + goto err_out_nodev; |
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| 410 | + } |
|---|
| 369 | 411 | for (i = 0; i < PM8001_MAX_DEVICES; i++) { |
|---|
| 370 | 412 | pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; |
|---|
| 371 | 413 | pm8001_ha->devices[i].id = i; |
|---|
| 372 | 414 | pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; |
|---|
| 373 | | - pm8001_ha->devices[i].running_req = 0; |
|---|
| 374 | | - } |
|---|
| 375 | | - pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; |
|---|
| 376 | | - for (i = 0; i < PM8001_MAX_CCB; i++) { |
|---|
| 377 | | - pm8001_ha->ccb_info[i].ccb_dma_handle = |
|---|
| 378 | | - pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + |
|---|
| 379 | | - i * sizeof(struct pm8001_ccb_info); |
|---|
| 380 | | - pm8001_ha->ccb_info[i].task = NULL; |
|---|
| 381 | | - pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; |
|---|
| 382 | | - pm8001_ha->ccb_info[i].device = NULL; |
|---|
| 383 | | - ++pm8001_ha->tags_num; |
|---|
| 415 | + atomic_set(&pm8001_ha->devices[i].running_req, 0); |
|---|
| 384 | 416 | } |
|---|
| 385 | 417 | pm8001_ha->flags = PM8001F_INIT_TIME; |
|---|
| 386 | 418 | /* Initialize tags */ |
|---|
| 387 | 419 | pm8001_tag_init(pm8001_ha); |
|---|
| 388 | 420 | return 0; |
|---|
| 421 | + |
|---|
| 422 | +err_out_nodev: |
|---|
| 423 | + for (i = 0; i < pm8001_ha->max_memcnt; i++) { |
|---|
| 424 | + if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { |
|---|
| 425 | + pci_free_consistent(pm8001_ha->pdev, |
|---|
| 426 | + (pm8001_ha->memoryMap.region[i].total_len + |
|---|
| 427 | + pm8001_ha->memoryMap.region[i].alignment), |
|---|
| 428 | + pm8001_ha->memoryMap.region[i].virt_ptr, |
|---|
| 429 | + pm8001_ha->memoryMap.region[i].phys_addr); |
|---|
| 430 | + } |
|---|
| 431 | + } |
|---|
| 389 | 432 | err_out: |
|---|
| 390 | 433 | return 1; |
|---|
| 391 | 434 | } |
|---|
| .. | .. |
|---|
| 403 | 446 | |
|---|
| 404 | 447 | pdev = pm8001_ha->pdev; |
|---|
| 405 | 448 | /* map pci mem (PMC pci base 0-3)*/ |
|---|
| 406 | | - for (bar = 0; bar < 6; bar++) { |
|---|
| 449 | + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
|---|
| 407 | 450 | /* |
|---|
| 408 | 451 | ** logical BARs for SPC: |
|---|
| 409 | 452 | ** bar 0 and 1 - logical BAR0 |
|---|
| .. | .. |
|---|
| 422 | 465 | pm8001_ha->io_mem[logicalBar].memvirtaddr = |
|---|
| 423 | 466 | ioremap(pm8001_ha->io_mem[logicalBar].membase, |
|---|
| 424 | 467 | pm8001_ha->io_mem[logicalBar].memsize); |
|---|
| 425 | | - PM8001_INIT_DBG(pm8001_ha, |
|---|
| 426 | | - pm8001_printk("PCI: bar %d, logicalBar %d ", |
|---|
| 427 | | - bar, logicalBar)); |
|---|
| 428 | | - PM8001_INIT_DBG(pm8001_ha, pm8001_printk( |
|---|
| 429 | | - "base addr %llx virt_addr=%llx len=%d\n", |
|---|
| 430 | | - (u64)pm8001_ha->io_mem[logicalBar].membase, |
|---|
| 431 | | - (u64)(unsigned long) |
|---|
| 432 | | - pm8001_ha->io_mem[logicalBar].memvirtaddr, |
|---|
| 433 | | - pm8001_ha->io_mem[logicalBar].memsize)); |
|---|
| 468 | + pm8001_dbg(pm8001_ha, INIT, |
|---|
| 469 | + "PCI: bar %d, logicalBar %d\n", |
|---|
| 470 | + bar, logicalBar); |
|---|
| 471 | + pm8001_dbg(pm8001_ha, INIT, |
|---|
| 472 | + "base addr %llx virt_addr=%llx len=%d\n", |
|---|
| 473 | + (u64)pm8001_ha->io_mem[logicalBar].membase, |
|---|
| 474 | + (u64)(unsigned long) |
|---|
| 475 | + pm8001_ha->io_mem[logicalBar].memvirtaddr, |
|---|
| 476 | + pm8001_ha->io_mem[logicalBar].memsize); |
|---|
| 434 | 477 | } else { |
|---|
| 435 | 478 | pm8001_ha->io_mem[logicalBar].membase = 0; |
|---|
| 436 | 479 | pm8001_ha->io_mem[logicalBar].memsize = 0; |
|---|
| 437 | | - pm8001_ha->io_mem[logicalBar].memvirtaddr = 0; |
|---|
| 480 | + pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; |
|---|
| 438 | 481 | } |
|---|
| 439 | 482 | logicalBar++; |
|---|
| 440 | 483 | } |
|---|
| .. | .. |
|---|
| 468 | 511 | pm8001_ha->sas = sha; |
|---|
| 469 | 512 | pm8001_ha->shost = shost; |
|---|
| 470 | 513 | pm8001_ha->id = pm8001_id++; |
|---|
| 471 | | - pm8001_ha->logging_level = 0x01; |
|---|
| 514 | + pm8001_ha->logging_level = logging_level; |
|---|
| 515 | + pm8001_ha->non_fatal_count = 0; |
|---|
| 516 | + if (link_rate >= 1 && link_rate <= 15) |
|---|
| 517 | + pm8001_ha->link_rate = (link_rate << 8); |
|---|
| 518 | + else { |
|---|
| 519 | + pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | |
|---|
| 520 | + LINKRATE_60 | LINKRATE_120; |
|---|
| 521 | + pm8001_dbg(pm8001_ha, FAIL, |
|---|
| 522 | + "Setting link rate to default value\n"); |
|---|
| 523 | + } |
|---|
| 472 | 524 | sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); |
|---|
| 473 | 525 | /* IOMB size is 128 for 8088/89 controllers */ |
|---|
| 474 | 526 | if (pm8001_ha->chip_id != chip_8001) |
|---|
| .. | .. |
|---|
| 502 | 554 | { |
|---|
| 503 | 555 | int rc; |
|---|
| 504 | 556 | |
|---|
| 505 | | - if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) { |
|---|
| 506 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44)); |
|---|
| 507 | | - if (rc) { |
|---|
| 508 | | - rc = pci_set_consistent_dma_mask(pdev, |
|---|
| 509 | | - DMA_BIT_MASK(32)); |
|---|
| 510 | | - if (rc) { |
|---|
| 511 | | - dev_printk(KERN_ERR, &pdev->dev, |
|---|
| 512 | | - "44-bit DMA enable failed\n"); |
|---|
| 513 | | - return rc; |
|---|
| 514 | | - } |
|---|
| 515 | | - } |
|---|
| 516 | | - } else { |
|---|
| 517 | | - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|---|
| 518 | | - if (rc) { |
|---|
| 557 | + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); |
|---|
| 558 | + if (rc) { |
|---|
| 559 | + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
|---|
| 560 | + if (rc) |
|---|
| 519 | 561 | dev_printk(KERN_ERR, &pdev->dev, |
|---|
| 520 | 562 | "32-bit DMA enable failed\n"); |
|---|
| 521 | | - return rc; |
|---|
| 522 | | - } |
|---|
| 523 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
|---|
| 524 | | - if (rc) { |
|---|
| 525 | | - dev_printk(KERN_ERR, &pdev->dev, |
|---|
| 526 | | - "32-bit consistent DMA enable failed\n"); |
|---|
| 527 | | - return rc; |
|---|
| 528 | | - } |
|---|
| 529 | 563 | } |
|---|
| 530 | 564 | return rc; |
|---|
| 531 | 565 | } |
|---|
| .. | .. |
|---|
| 606 | 640 | |
|---|
| 607 | 641 | /** |
|---|
| 608 | 642 | * pm8001_init_sas_add - initialize sas address |
|---|
| 609 | | - * @chip_info: our ha struct. |
|---|
| 643 | + * @pm8001_ha: our ha struct. |
|---|
| 610 | 644 | * |
|---|
| 611 | 645 | * Currently we just set the fixed SAS address to our HBA,for manufacture, |
|---|
| 612 | 646 | * it should read from the EEPROM |
|---|
| .. | .. |
|---|
| 631 | 665 | if (pm8001_ha->chip_id == chip_8001) { |
|---|
| 632 | 666 | if (deviceid == 0x8081 || deviceid == 0x0042) { |
|---|
| 633 | 667 | payload.minor_function = 4; |
|---|
| 634 | | - payload.length = 4096; |
|---|
| 668 | + payload.rd_length = 4096; |
|---|
| 635 | 669 | } else { |
|---|
| 636 | 670 | payload.minor_function = 0; |
|---|
| 637 | | - payload.length = 128; |
|---|
| 671 | + payload.rd_length = 128; |
|---|
| 638 | 672 | } |
|---|
| 639 | 673 | } else if ((pm8001_ha->chip_id == chip_8070 || |
|---|
| 640 | 674 | pm8001_ha->chip_id == chip_8072) && |
|---|
| 641 | 675 | pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { |
|---|
| 642 | 676 | payload.minor_function = 4; |
|---|
| 643 | | - payload.length = 4096; |
|---|
| 677 | + payload.rd_length = 4096; |
|---|
| 644 | 678 | } else { |
|---|
| 645 | 679 | payload.minor_function = 1; |
|---|
| 646 | | - payload.length = 4096; |
|---|
| 680 | + payload.rd_length = 4096; |
|---|
| 647 | 681 | } |
|---|
| 648 | 682 | payload.offset = 0; |
|---|
| 649 | | - payload.func_specific = kzalloc(payload.length, GFP_KERNEL); |
|---|
| 683 | + payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); |
|---|
| 650 | 684 | if (!payload.func_specific) { |
|---|
| 651 | | - PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n")); |
|---|
| 685 | + pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n"); |
|---|
| 652 | 686 | return; |
|---|
| 653 | 687 | } |
|---|
| 654 | 688 | rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); |
|---|
| 655 | 689 | if (rc) { |
|---|
| 656 | 690 | kfree(payload.func_specific); |
|---|
| 657 | | - PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); |
|---|
| 691 | + pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); |
|---|
| 658 | 692 | return; |
|---|
| 659 | 693 | } |
|---|
| 660 | 694 | wait_for_completion(&completion); |
|---|
| .. | .. |
|---|
| 682 | 716 | sas_add[7] = sas_add[7] + 4; |
|---|
| 683 | 717 | memcpy(&pm8001_ha->phy[i].dev_sas_addr, |
|---|
| 684 | 718 | sas_add, SAS_ADDR_SIZE); |
|---|
| 685 | | - PM8001_INIT_DBG(pm8001_ha, |
|---|
| 686 | | - pm8001_printk("phy %d sas_addr = %016llx\n", i, |
|---|
| 687 | | - pm8001_ha->phy[i].dev_sas_addr)); |
|---|
| 719 | + pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, |
|---|
| 720 | + pm8001_ha->phy[i].dev_sas_addr); |
|---|
| 688 | 721 | } |
|---|
| 689 | 722 | kfree(payload.func_specific); |
|---|
| 690 | 723 | #else |
|---|
| .. | .. |
|---|
| 716 | 749 | /* SAS ADDRESS read from flash / EEPROM */ |
|---|
| 717 | 750 | payload.minor_function = 6; |
|---|
| 718 | 751 | payload.offset = 0; |
|---|
| 719 | | - payload.length = 4096; |
|---|
| 752 | + payload.rd_length = 4096; |
|---|
| 720 | 753 | payload.func_specific = kzalloc(4096, GFP_KERNEL); |
|---|
| 721 | 754 | if (!payload.func_specific) |
|---|
| 722 | 755 | return -ENOMEM; |
|---|
| .. | .. |
|---|
| 724 | 757 | rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); |
|---|
| 725 | 758 | if (rc) { |
|---|
| 726 | 759 | kfree(payload.func_specific); |
|---|
| 727 | | - PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); |
|---|
| 760 | + pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); |
|---|
| 728 | 761 | return -ENOMEM; |
|---|
| 729 | 762 | } |
|---|
| 730 | 763 | wait_for_completion(&completion); |
|---|
| .. | .. |
|---|
| 818 | 851 | break; |
|---|
| 819 | 852 | |
|---|
| 820 | 853 | default: |
|---|
| 821 | | - PM8001_INIT_DBG(pm8001_ha, |
|---|
| 822 | | - pm8001_printk("Unknown subsystem device=0x%.04x", |
|---|
| 823 | | - pm8001_ha->pdev->subsystem_device)); |
|---|
| 854 | + pm8001_dbg(pm8001_ha, INIT, |
|---|
| 855 | + "Unknown subsystem device=0x%.04x\n", |
|---|
| 856 | + pm8001_ha->pdev->subsystem_device); |
|---|
| 824 | 857 | } |
|---|
| 825 | 858 | } |
|---|
| 826 | 859 | |
|---|
| .. | .. |
|---|
| 884 | 917 | #ifdef PM8001_USE_MSIX |
|---|
| 885 | 918 | /** |
|---|
| 886 | 919 | * pm8001_setup_msix - enable MSI-X interrupt |
|---|
| 887 | | - * @chip_info: our ha struct. |
|---|
| 888 | | - * @irq_handler: irq_handler |
|---|
| 920 | + * @pm8001_ha: our ha struct. |
|---|
| 889 | 921 | */ |
|---|
| 890 | 922 | static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) |
|---|
| 891 | 923 | { |
|---|
| 892 | | - u32 i = 0, j = 0; |
|---|
| 893 | 924 | u32 number_of_intr; |
|---|
| 894 | | - int flag = 0; |
|---|
| 895 | | - int rc; |
|---|
| 896 | | - static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3]; |
|---|
| 925 | + int rc, cpu_online_count; |
|---|
| 926 | + unsigned int allocated_irq_vectors; |
|---|
| 897 | 927 | |
|---|
| 898 | 928 | /* SPCv controllers supports 64 msi-x */ |
|---|
| 899 | 929 | if (pm8001_ha->chip_id == chip_8001) { |
|---|
| 900 | 930 | number_of_intr = 1; |
|---|
| 901 | 931 | } else { |
|---|
| 902 | 932 | number_of_intr = PM8001_MAX_MSIX_VEC; |
|---|
| 903 | | - flag &= ~IRQF_SHARED; |
|---|
| 904 | 933 | } |
|---|
| 905 | 934 | |
|---|
| 935 | + cpu_online_count = num_online_cpus(); |
|---|
| 936 | + number_of_intr = min_t(int, cpu_online_count, number_of_intr); |
|---|
| 906 | 937 | rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, |
|---|
| 907 | 938 | number_of_intr, PCI_IRQ_MSIX); |
|---|
| 939 | + allocated_irq_vectors = rc; |
|---|
| 908 | 940 | if (rc < 0) |
|---|
| 909 | 941 | return rc; |
|---|
| 942 | + |
|---|
| 943 | + /* Assigns the number of interrupts */ |
|---|
| 944 | + number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr); |
|---|
| 910 | 945 | pm8001_ha->number_of_intr = number_of_intr; |
|---|
| 911 | 946 | |
|---|
| 912 | | - PM8001_INIT_DBG(pm8001_ha, pm8001_printk( |
|---|
| 913 | | - "pci_alloc_irq_vectors request ret:%d no of intr %d\n", |
|---|
| 914 | | - rc, pm8001_ha->number_of_intr)); |
|---|
| 947 | + /* Maximum queue number updating in HBA structure */ |
|---|
| 948 | + pm8001_ha->max_q_num = number_of_intr; |
|---|
| 915 | 949 | |
|---|
| 916 | | - for (i = 0; i < number_of_intr; i++) { |
|---|
| 917 | | - snprintf(intr_drvname[i], sizeof(intr_drvname[0]), |
|---|
| 918 | | - DRV_NAME"%d", i); |
|---|
| 950 | + pm8001_dbg(pm8001_ha, INIT, |
|---|
| 951 | + "pci_alloc_irq_vectors request ret:%d no of intr %d\n", |
|---|
| 952 | + rc, pm8001_ha->number_of_intr); |
|---|
| 953 | + return 0; |
|---|
| 954 | +} |
|---|
| 955 | + |
|---|
| 956 | +static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) |
|---|
| 957 | +{ |
|---|
| 958 | + u32 i = 0, j = 0; |
|---|
| 959 | + int flag = 0, rc = 0; |
|---|
| 960 | + |
|---|
| 961 | + if (pm8001_ha->chip_id != chip_8001) |
|---|
| 962 | + flag &= ~IRQF_SHARED; |
|---|
| 963 | + |
|---|
| 964 | + pm8001_dbg(pm8001_ha, INIT, |
|---|
| 965 | + "pci_enable_msix request number of intr %d\n", |
|---|
| 966 | + pm8001_ha->number_of_intr); |
|---|
| 967 | + |
|---|
| 968 | + for (i = 0; i < pm8001_ha->number_of_intr; i++) { |
|---|
| 969 | + snprintf(pm8001_ha->intr_drvname[i], |
|---|
| 970 | + sizeof(pm8001_ha->intr_drvname[0]), |
|---|
| 971 | + "%s-%d", pm8001_ha->name, i); |
|---|
| 919 | 972 | pm8001_ha->irq_vector[i].irq_id = i; |
|---|
| 920 | 973 | pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; |
|---|
| 921 | 974 | |
|---|
| 922 | 975 | rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), |
|---|
| 923 | 976 | pm8001_interrupt_handler_msix, flag, |
|---|
| 924 | | - intr_drvname[i], &(pm8001_ha->irq_vector[i])); |
|---|
| 977 | + pm8001_ha->intr_drvname[i], |
|---|
| 978 | + &(pm8001_ha->irq_vector[i])); |
|---|
| 925 | 979 | if (rc) { |
|---|
| 926 | 980 | for (j = 0; j < i; j++) { |
|---|
| 927 | 981 | free_irq(pci_irq_vector(pm8001_ha->pdev, i), |
|---|
| .. | .. |
|---|
| 936 | 990 | } |
|---|
| 937 | 991 | #endif |
|---|
| 938 | 992 | |
|---|
| 993 | +static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) |
|---|
| 994 | +{ |
|---|
| 995 | + struct pci_dev *pdev; |
|---|
| 996 | + |
|---|
| 997 | + pdev = pm8001_ha->pdev; |
|---|
| 998 | + |
|---|
| 999 | +#ifdef PM8001_USE_MSIX |
|---|
| 1000 | + if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) |
|---|
| 1001 | + return pm8001_setup_msix(pm8001_ha); |
|---|
| 1002 | + pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); |
|---|
| 1003 | +#endif |
|---|
| 1004 | + return 0; |
|---|
| 1005 | +} |
|---|
| 1006 | + |
|---|
| 939 | 1007 | /** |
|---|
| 940 | 1008 | * pm8001_request_irq - register interrupt |
|---|
| 941 | | - * @chip_info: our ha struct. |
|---|
| 1009 | + * @pm8001_ha: our ha struct. |
|---|
| 942 | 1010 | */ |
|---|
| 943 | 1011 | static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) |
|---|
| 944 | 1012 | { |
|---|
| .. | .. |
|---|
| 949 | 1017 | |
|---|
| 950 | 1018 | #ifdef PM8001_USE_MSIX |
|---|
| 951 | 1019 | if (pdev->msix_cap && pci_msi_enabled()) |
|---|
| 952 | | - return pm8001_setup_msix(pm8001_ha); |
|---|
| 1020 | + return pm8001_request_msix(pm8001_ha); |
|---|
| 953 | 1021 | else { |
|---|
| 954 | | - PM8001_INIT_DBG(pm8001_ha, |
|---|
| 955 | | - pm8001_printk("MSIX not supported!!!\n")); |
|---|
| 1022 | + pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); |
|---|
| 956 | 1023 | goto intx; |
|---|
| 957 | 1024 | } |
|---|
| 958 | 1025 | #endif |
|---|
| .. | .. |
|---|
| 962 | 1029 | pm8001_ha->irq_vector[0].irq_id = 0; |
|---|
| 963 | 1030 | pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; |
|---|
| 964 | 1031 | rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, |
|---|
| 965 | | - DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost)); |
|---|
| 1032 | + pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); |
|---|
| 966 | 1033 | return rc; |
|---|
| 967 | 1034 | } |
|---|
| 968 | 1035 | |
|---|
| .. | .. |
|---|
| 984 | 1051 | struct pm8001_hba_info *pm8001_ha; |
|---|
| 985 | 1052 | struct Scsi_Host *shost = NULL; |
|---|
| 986 | 1053 | const struct pm8001_chip_info *chip; |
|---|
| 1054 | + struct sas_ha_struct *sha; |
|---|
| 987 | 1055 | |
|---|
| 988 | 1056 | dev_printk(KERN_INFO, &pdev->dev, |
|---|
| 989 | 1057 | "pm80xx: driver version %s\n", DRV_VERSION); |
|---|
| .. | .. |
|---|
| 1012 | 1080 | goto err_out_regions; |
|---|
| 1013 | 1081 | } |
|---|
| 1014 | 1082 | chip = &pm8001_chips[ent->driver_data]; |
|---|
| 1015 | | - SHOST_TO_SAS_HA(shost) = |
|---|
| 1016 | | - kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); |
|---|
| 1017 | | - if (!SHOST_TO_SAS_HA(shost)) { |
|---|
| 1083 | + sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); |
|---|
| 1084 | + if (!sha) { |
|---|
| 1018 | 1085 | rc = -ENOMEM; |
|---|
| 1019 | 1086 | goto err_out_free_host; |
|---|
| 1020 | 1087 | } |
|---|
| 1088 | + SHOST_TO_SAS_HA(shost) = sha; |
|---|
| 1021 | 1089 | |
|---|
| 1022 | 1090 | rc = pm8001_prep_sas_ha_init(shost, chip); |
|---|
| 1023 | 1091 | if (rc) { |
|---|
| .. | .. |
|---|
| 1031 | 1099 | rc = -ENOMEM; |
|---|
| 1032 | 1100 | goto err_out_free; |
|---|
| 1033 | 1101 | } |
|---|
| 1034 | | - list_add_tail(&pm8001_ha->list, &hba_list); |
|---|
| 1102 | + |
|---|
| 1035 | 1103 | PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); |
|---|
| 1036 | 1104 | rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); |
|---|
| 1037 | 1105 | if (rc) { |
|---|
| 1038 | | - PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( |
|---|
| 1039 | | - "chip_init failed [ret: %d]\n", rc)); |
|---|
| 1106 | + pm8001_dbg(pm8001_ha, FAIL, |
|---|
| 1107 | + "chip_init failed [ret: %d]\n", rc); |
|---|
| 1040 | 1108 | goto err_out_ha_free; |
|---|
| 1041 | 1109 | } |
|---|
| 1110 | + |
|---|
| 1111 | + rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev); |
|---|
| 1112 | + if (rc) |
|---|
| 1113 | + goto err_out_enable; |
|---|
| 1042 | 1114 | |
|---|
| 1043 | 1115 | rc = scsi_add_host(shost, &pdev->dev); |
|---|
| 1044 | 1116 | if (rc) |
|---|
| 1045 | 1117 | goto err_out_ha_free; |
|---|
| 1046 | | - rc = pm8001_request_irq(pm8001_ha); |
|---|
| 1047 | | - if (rc) { |
|---|
| 1048 | | - PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( |
|---|
| 1049 | | - "pm8001_request_irq failed [ret: %d]\n", rc)); |
|---|
| 1050 | | - goto err_out_shost; |
|---|
| 1051 | | - } |
|---|
| 1052 | 1118 | |
|---|
| 1053 | 1119 | PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); |
|---|
| 1054 | 1120 | if (pm8001_ha->chip_id != chip_8001) { |
|---|
| .. | .. |
|---|
| 1066 | 1132 | |
|---|
| 1067 | 1133 | pm8001_post_sas_ha_init(shost, chip); |
|---|
| 1068 | 1134 | rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); |
|---|
| 1069 | | - if (rc) |
|---|
| 1135 | + if (rc) { |
|---|
| 1136 | + pm8001_dbg(pm8001_ha, FAIL, |
|---|
| 1137 | + "sas_register_ha failed [ret: %d]\n", rc); |
|---|
| 1070 | 1138 | goto err_out_shost; |
|---|
| 1139 | + } |
|---|
| 1140 | + list_add_tail(&pm8001_ha->list, &hba_list); |
|---|
| 1141 | + pm8001_ha->flags = PM8001F_RUN_TIME; |
|---|
| 1071 | 1142 | scsi_scan_host(pm8001_ha->shost); |
|---|
| 1072 | 1143 | return 0; |
|---|
| 1073 | 1144 | |
|---|
| .. | .. |
|---|
| 1076 | 1147 | err_out_ha_free: |
|---|
| 1077 | 1148 | pm8001_free(pm8001_ha); |
|---|
| 1078 | 1149 | err_out_free: |
|---|
| 1079 | | - kfree(SHOST_TO_SAS_HA(shost)); |
|---|
| 1150 | + kfree(sha); |
|---|
| 1080 | 1151 | err_out_free_host: |
|---|
| 1081 | 1152 | scsi_host_put(shost); |
|---|
| 1082 | 1153 | err_out_regions: |
|---|
| .. | .. |
|---|
| 1085 | 1156 | pci_disable_device(pdev); |
|---|
| 1086 | 1157 | err_out_enable: |
|---|
| 1087 | 1158 | return rc; |
|---|
| 1159 | +} |
|---|
| 1160 | + |
|---|
| 1161 | +/* |
|---|
| 1162 | + * pm8001_init_ccb_tag - allocate memory to CCB and tag. |
|---|
| 1163 | + * @pm8001_ha: our hba card information. |
|---|
| 1164 | + * @shost: scsi host which has been allocated outside. |
|---|
| 1165 | + */ |
|---|
| 1166 | +static int |
|---|
| 1167 | +pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost, |
|---|
| 1168 | + struct pci_dev *pdev) |
|---|
| 1169 | +{ |
|---|
| 1170 | + int i = 0; |
|---|
| 1171 | + u32 max_out_io, ccb_count; |
|---|
| 1172 | + u32 can_queue; |
|---|
| 1173 | + |
|---|
| 1174 | + max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; |
|---|
| 1175 | + ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); |
|---|
| 1176 | + |
|---|
| 1177 | + /* Update to the scsi host*/ |
|---|
| 1178 | + can_queue = ccb_count - PM8001_RESERVE_SLOT; |
|---|
| 1179 | + shost->can_queue = can_queue; |
|---|
| 1180 | + |
|---|
| 1181 | + pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL); |
|---|
| 1182 | + if (!pm8001_ha->tags) |
|---|
| 1183 | + goto err_out; |
|---|
| 1184 | + |
|---|
| 1185 | + /* Memory region for ccb_info*/ |
|---|
| 1186 | + pm8001_ha->ccb_info = (struct pm8001_ccb_info *) |
|---|
| 1187 | + kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); |
|---|
| 1188 | + if (!pm8001_ha->ccb_info) { |
|---|
| 1189 | + pm8001_dbg(pm8001_ha, FAIL, |
|---|
| 1190 | + "Unable to allocate memory for ccb\n"); |
|---|
| 1191 | + goto err_out_noccb; |
|---|
| 1192 | + } |
|---|
| 1193 | + for (i = 0; i < ccb_count; i++) { |
|---|
| 1194 | + pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev, |
|---|
| 1195 | + sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, |
|---|
| 1196 | + &pm8001_ha->ccb_info[i].ccb_dma_handle); |
|---|
| 1197 | + if (!pm8001_ha->ccb_info[i].buf_prd) { |
|---|
| 1198 | + pm8001_dbg(pm8001_ha, FAIL, |
|---|
| 1199 | + "pm80xx: ccb prd memory allocation error\n"); |
|---|
| 1200 | + goto err_out; |
|---|
| 1201 | + } |
|---|
| 1202 | + pm8001_ha->ccb_info[i].task = NULL; |
|---|
| 1203 | + pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; |
|---|
| 1204 | + pm8001_ha->ccb_info[i].device = NULL; |
|---|
| 1205 | + ++pm8001_ha->tags_num; |
|---|
| 1206 | + } |
|---|
| 1207 | + return 0; |
|---|
| 1208 | + |
|---|
| 1209 | +err_out_noccb: |
|---|
| 1210 | + kfree(pm8001_ha->devices); |
|---|
| 1211 | +err_out: |
|---|
| 1212 | + return -ENOMEM; |
|---|
| 1088 | 1213 | } |
|---|
| 1089 | 1214 | |
|---|
| 1090 | 1215 | static void pm8001_pci_remove(struct pci_dev *pdev) |
|---|
| .. | .. |
|---|
| 1215 | 1340 | /* chip soft rst only for spc */ |
|---|
| 1216 | 1341 | if (pm8001_ha->chip_id == chip_8001) { |
|---|
| 1217 | 1342 | PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); |
|---|
| 1218 | | - PM8001_INIT_DBG(pm8001_ha, |
|---|
| 1219 | | - pm8001_printk("chip soft reset successful\n")); |
|---|
| 1343 | + pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); |
|---|
| 1220 | 1344 | } |
|---|
| 1221 | 1345 | rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); |
|---|
| 1222 | 1346 | if (rc) |
|---|