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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Marvell 88SE64xx/88SE94xx pci init |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright 2007 Red Hat, Inc. |
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| 5 | 6 | * Copyright 2008 Marvell. <kewei@marvell.com> |
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| 6 | 7 | * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> |
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| 7 | | - * |
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| 8 | | - * This file is licensed under GPLv2. |
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| 9 | | - * |
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| 10 | | - * This program is free software; you can redistribute it and/or |
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| 11 | | - * modify it under the terms of the GNU General Public License as |
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| 12 | | - * published by the Free Software Foundation; version 2 of the |
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| 13 | | - * License. |
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| 14 | | - * |
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| 15 | | - * This program is distributed in the hope that it will be useful, |
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| 16 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | | - * General Public License for more details. |
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| 19 | | - * |
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| 20 | | - * You should have received a copy of the GNU General Public License |
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| 21 | | - * along with this program; if not, write to the Free Software |
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| 22 | | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 |
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| 23 | | - * USA |
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| 24 | 8 | */ |
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| 25 | 9 | |
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| 26 | 10 | |
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| .. | .. |
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| 41 | 25 | [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, |
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| 42 | 26 | }; |
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| 43 | 27 | |
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| 44 | | -struct device_attribute *mvst_host_attrs[]; |
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| 28 | +static struct device_attribute *mvst_host_attrs[]; |
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| 45 | 29 | |
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| 46 | 30 | #define SOC_SAS_NUM 2 |
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| 47 | 31 | |
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| .. | .. |
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| 49 | 33 | .module = THIS_MODULE, |
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| 50 | 34 | .name = DRV_NAME, |
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| 51 | 35 | .queuecommand = sas_queuecommand, |
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| 36 | + .dma_need_drain = ata_scsi_dma_need_drain, |
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| 52 | 37 | .target_alloc = sas_target_alloc, |
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| 53 | 38 | .slave_configure = sas_slave_configure, |
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| 54 | 39 | .scan_finished = mvs_scan_finished, |
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| .. | .. |
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| 59 | 44 | .this_id = -1, |
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| 60 | 45 | .sg_tablesize = SG_ALL, |
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| 61 | 46 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, |
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| 62 | | - .use_clustering = ENABLE_CLUSTERING, |
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| 63 | 47 | .eh_device_reset_handler = sas_eh_device_reset_handler, |
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| 64 | 48 | .eh_target_reset_handler = sas_eh_target_reset_handler, |
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| 65 | 49 | .slave_alloc = sas_slave_alloc, |
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| 66 | 50 | .target_destroy = sas_target_destroy, |
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| 67 | 51 | .ioctl = sas_ioctl, |
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| 52 | +#ifdef CONFIG_COMPAT |
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| 53 | + .compat_ioctl = sas_ioctl, |
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| 54 | +#endif |
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| 68 | 55 | .shost_attrs = mvst_host_attrs, |
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| 69 | 56 | .track_queue_depth = 1, |
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| 70 | 57 | }; |
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| .. | .. |
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| 191 | 178 | |
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| 192 | 179 | static irqreturn_t mvs_interrupt(int irq, void *opaque) |
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| 193 | 180 | { |
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| 194 | | - u32 core_nr; |
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| 195 | 181 | u32 stat; |
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| 196 | 182 | struct mvs_info *mvi; |
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| 197 | 183 | struct sas_ha_struct *sha = opaque; |
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| 198 | 184 | #ifndef CONFIG_SCSI_MVSAS_TASKLET |
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| 199 | 185 | u32 i; |
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| 200 | | -#endif |
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| 186 | + u32 core_nr; |
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| 201 | 187 | |
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| 202 | 188 | core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; |
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| 189 | +#endif |
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| 190 | + |
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| 203 | 191 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; |
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| 204 | 192 | |
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| 205 | 193 | if (unlikely(!mvi)) |
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| .. | .. |
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| 259 | 247 | &mvi->tx_dma, GFP_KERNEL); |
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| 260 | 248 | if (!mvi->tx) |
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| 261 | 249 | goto err_out; |
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| 262 | | - memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); |
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| 263 | 250 | mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, |
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| 264 | 251 | &mvi->rx_fis_dma, GFP_KERNEL); |
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| 265 | 252 | if (!mvi->rx_fis) |
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| 266 | 253 | goto err_out; |
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| 267 | | - memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); |
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| 268 | 254 | |
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| 269 | 255 | mvi->rx = dma_alloc_coherent(mvi->dev, |
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| 270 | 256 | sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), |
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| 271 | 257 | &mvi->rx_dma, GFP_KERNEL); |
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| 272 | 258 | if (!mvi->rx) |
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| 273 | 259 | goto err_out; |
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| 274 | | - memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); |
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| 275 | 260 | mvi->rx[0] = cpu_to_le32(0xfff); |
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| 276 | 261 | mvi->rx_cons = 0xfff; |
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| 277 | 262 | |
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| .. | .. |
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| 280 | 265 | &mvi->slot_dma, GFP_KERNEL); |
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| 281 | 266 | if (!mvi->slot) |
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| 282 | 267 | goto err_out; |
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| 283 | | - memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); |
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| 284 | 268 | |
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| 285 | 269 | mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, |
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| 286 | 270 | TRASH_BUCKET_SIZE, |
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| .. | .. |
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| 313 | 297 | |
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| 314 | 298 | int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) |
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| 315 | 299 | { |
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| 316 | | - unsigned long res_start, res_len, res_flag, res_flag_ex = 0; |
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| 300 | + unsigned long res_start, res_len, res_flag_ex = 0; |
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| 317 | 301 | struct pci_dev *pdev = mvi->pdev; |
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| 318 | 302 | if (bar_ex != -1) { |
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| 319 | 303 | /* |
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| .. | .. |
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| 341 | 325 | goto err_out; |
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| 342 | 326 | } |
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| 343 | 327 | |
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| 344 | | - res_flag = pci_resource_flags(pdev, bar); |
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| 345 | 328 | mvi->regs = ioremap(res_start, res_len); |
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| 346 | 329 | |
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| 347 | 330 | if (!mvi->regs) { |
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| .. | .. |
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| 404 | 387 | { |
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| 405 | 388 | int rc; |
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| 406 | 389 | |
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| 407 | | - if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
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| 408 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
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| 409 | | - if (rc) { |
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| 410 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
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| 411 | | - if (rc) { |
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| 412 | | - dev_printk(KERN_ERR, &pdev->dev, |
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| 413 | | - "64-bit DMA enable failed\n"); |
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| 414 | | - return rc; |
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| 415 | | - } |
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| 416 | | - } |
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| 417 | | - } else { |
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| 418 | | - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
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| 390 | + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
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| 391 | + if (rc) { |
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| 392 | + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
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| 419 | 393 | if (rc) { |
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| 420 | 394 | dev_printk(KERN_ERR, &pdev->dev, |
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| 421 | 395 | "32-bit DMA enable failed\n"); |
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| 422 | | - return rc; |
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| 423 | | - } |
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| 424 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
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| 425 | | - if (rc) { |
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| 426 | | - dev_printk(KERN_ERR, &pdev->dev, |
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| 427 | | - "32-bit consistent DMA enable failed\n"); |
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| 428 | 396 | return rc; |
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| 429 | 397 | } |
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| 430 | 398 | } |
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| .. | .. |
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| 678 | 646 | { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, |
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| 679 | 647 | { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, |
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| 680 | 648 | { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, |
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| 649 | + { PCI_VDEVICE(TTI, 0x2640), chip_6440 }, |
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| 681 | 650 | { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, |
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| 682 | 651 | { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, |
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| 683 | 652 | { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, |
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| .. | .. |
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| 729 | 698 | mvs_show_driver_version(struct device *cdev, |
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| 730 | 699 | struct device_attribute *attr, char *buffer) |
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| 731 | 700 | { |
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| 732 | | - return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); |
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| 701 | + return sysfs_emit(buffer, "%s\n", DRV_VERSION); |
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| 733 | 702 | } |
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| 734 | 703 | |
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| 735 | 704 | static DEVICE_ATTR(driver_version, |
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| .. | .. |
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| 781 | 750 | static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, |
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| 782 | 751 | struct device_attribute *attr, char *buffer) |
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| 783 | 752 | { |
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| 784 | | - return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); |
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| 753 | + return sysfs_emit(buffer, "%d\n", interrupt_coalescing); |
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| 785 | 754 | } |
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| 786 | 755 | |
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| 787 | 756 | static DEVICE_ATTR(interrupt_coalescing, |
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| .. | .. |
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| 789 | 758 | mvs_show_interrupt_coalescing, |
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| 790 | 759 | mvs_store_interrupt_coalescing); |
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| 791 | 760 | |
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| 792 | | -/* task handler */ |
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| 793 | | -struct task_struct *mvs_th; |
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| 794 | 761 | static int __init mvs_init(void) |
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| 795 | 762 | { |
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| 796 | 763 | int rc; |
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| .. | .. |
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| 815 | 782 | sas_release_transport(mvs_stt); |
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| 816 | 783 | } |
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| 817 | 784 | |
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| 818 | | -struct device_attribute *mvst_host_attrs[] = { |
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| 785 | +static struct device_attribute *mvst_host_attrs[] = { |
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| 819 | 786 | &dev_attr_driver_version, |
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| 820 | 787 | &dev_attr_interrupt_coalescing, |
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| 821 | 788 | NULL, |
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