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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h
....@@ -1,13 +1,13 @@
11 /* SPDX-License-Identifier: GPL-2.0 */
22 /*
3
- * Copyright 2000-2015 Avago Technologies.  All rights reserved.
3
+ * Copyright 2000-2020 Broadcom Inc. All rights reserved.
44  *
55  *
66  *          Name:  mpi2_cnfg.h
77  *         Title:  MPI Configuration messages and pages
88  * Creation Date:  November 10, 2006
99  *
10
- *    mpi2_cnfg.h Version:  02.00.42
10
+ *    mpi2_cnfg.h Version:  02.00.47
1111  *
1212  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
1313  *       prefix are for use only on MPI v2.5 products, and must not be used
....@@ -231,7 +231,26 @@
231231  *                     Added NOIOB field to PCIe Device Page 2.
232232  *                     Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to
233233  *                     the Capabilities field of PCIe Device Page 2.
234
+ * 07-22-18  02.00.43  Added defines for SAS3916 and SAS3816.
235
+ *                     Added WRiteCache defines to IO Unit Page 1.
236
+ *                     Added MaxEnclosureLevel to BIOS Page 1.
237
+ *                     Added OEMRD to SAS Enclosure Page 1.
238
+ *                     Added DMDReportPCIe to PCIe IO Unit Page 1.
239
+ *                     Added Flags field and flags for Retimers to
240
+ *                     PCIe Switch Page 1.
241
+ * 08-02-18  02.00.44  Added Slotx2, Slotx4 to ManPage 7.
242
+ * 08-15-18  02.00.45  Added ProductSpecific field at end of IOC Page 1
243
+ * 08-28-18  02.00.46  Added NVMs Write Cache flag to IOUnitPage1
244
+ *                     Added DMDReport Delay Time defines to
245
+ *                     PCIeIOUnitPage1
234246  * --------------------------------------------------------------------------
247
+ * 08-02-18  02.00.44  Added Slotx2, Slotx4 to ManPage 7.
248
+ * 08-15-18  02.00.45  Added ProductSpecific field at end of IOC Page 1
249
+ * 08-28-18  02.00.46  Added NVMs Write Cache flag to IOUnitPage1
250
+ *                     Added DMDReport Delay Time defines to PCIeIOUnitPage1
251
+ * 12-17-18  02.00.47  Swap locations of Slotx2 and Slotx4 in ManPage 7.
252
+ * 08-01-19  02.00.49  Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID
253
+ *                     Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT
235254  */
236255 
237256 #ifndef MPI2_CNFG_H
....@@ -536,7 +555,8 @@
536555 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
537556 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
538557 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
539
-#define MPI2_MFGPAGE_DEVID_SAS2308_MPI_EP           (0x02B0)
558
+#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP            (0x02B0)
559
+#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1          (0x02B1)
540560 
541561 /*MPI v2.5 SAS products */
542562 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
....@@ -568,8 +588,17 @@
568588 #define MPI26_MFGPAGE_DEVID_SAS3616                 (0x00D1)
569589 #define MPI26_MFGPAGE_DEVID_SAS3708                 (0x00D2)
570590 
571
-#define MPI26_MFGPAGE_DEVID_SAS3816                 (0x00A1)
572
-#define MPI26_MFGPAGE_DEVID_SAS3916                 (0x00A0)
591
+#define MPI26_MFGPAGE_DEVID_SEC_MASK_3916           (0x0003)
592
+#define MPI26_MFGPAGE_DEVID_INVALID0_3916           (0x00E0)
593
+#define MPI26_MFGPAGE_DEVID_CFG_SEC_3916            (0x00E1)
594
+#define MPI26_MFGPAGE_DEVID_HARD_SEC_3916           (0x00E2)
595
+#define MPI26_MFGPAGE_DEVID_INVALID1_3916           (0x00E3)
596
+
597
+#define MPI26_MFGPAGE_DEVID_SEC_MASK_3816           (0x0003)
598
+#define MPI26_MFGPAGE_DEVID_INVALID0_3816           (0x00E4)
599
+#define MPI26_MFGPAGE_DEVID_CFG_SEC_3816            (0x00E5)
600
+#define MPI26_MFGPAGE_DEVID_HARD_SEC_3816           (0x00E6)
601
+#define MPI26_MFGPAGE_DEVID_INVALID1_3816           (0x00E7)
573602 
574603 
575604 /*Manufacturing Page 0 */
....@@ -788,7 +817,8 @@
788817 	U8                          Location;               /*0x14 */
789818 	U8                          ReceptacleID;           /*0x15 */
790819 	U16                         Slot;                   /*0x16 */
791
-	U32                         Reserved2;              /*0x18 */
820
+	U16                         Slotx2;                 /*0x18 */
821
+	U16                         Slotx4;                 /*0x1A */
792822 } MPI2_MANPAGE7_CONNECTOR_INFO,
793823 	*PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
794824 	Mpi2ManPage7ConnectorInfo_t,
....@@ -863,6 +893,8 @@
863893 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
864894 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
865895 
896
+#define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT        (0x00000020)
897
+#define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID       (0x00000010)
866898 
867899 /*
868900  *Generic structure to use for product-specific manufacturing pages
....@@ -932,7 +964,12 @@
932964 
933965 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
934966 
935
-/*IO Unit Page 1 Flags defines */
967
+/* IO Unit Page 1 Flags defines */
968
+#define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK             (0x00030000)
969
+#define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT            (16)
970
+#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE        (0x00000000)
971
+#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE           (0x00010000)
972
+#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE          (0x00020000)
936973 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
937974 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
938975 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
....@@ -1372,7 +1409,7 @@
13721409 	U8                      PCIBusNum;                  /*0x0E */
13731410 	U8                      PCIDomainSegment;           /*0x0F */
13741411 	U32                     Reserved1;                  /*0x10 */
1375
-	U32                     Reserved2;                  /*0x14 */
1412
+	U32                     ProductSpecific;            /* 0x14 */
13761413 } MPI2_CONFIG_PAGE_IOC_1,
13771414 	*PTR_MPI2_CONFIG_PAGE_IOC_1,
13781415 	Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
....@@ -1511,7 +1548,7 @@
15111548 	U32                     BiosOptions;                /*0x04 */
15121549 	U32                     IOCSettings;                /*0x08 */
15131550 	U8                      SSUTimeout;                 /*0x0C */
1514
-	U8                      Reserved1;                  /*0x0D */
1551
+	U8                      MaxEnclosureLevel;          /*0x0D */
15151552 	U16                     Reserved2;                  /*0x0E */
15161553 	U32                     DeviceSettings;             /*0x10 */
15171554 	U16                     NumberOfDevices;            /*0x14 */
....@@ -1530,7 +1567,6 @@
15301567 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE    (0x00008000)
15311568 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG                  (0x00004000)
15321569 
1533
-#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
15341570 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
15351571 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL                        (0x00000000)
15361572 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE                   (0x00000800)
....@@ -3271,10 +3307,12 @@
32713307 	U16	NumSlots;			/*0x18 */
32723308 	U16	StartSlot;			/*0x1A */
32733309 	U8	ChassisSlot;			/*0x1C */
3274
-	U8	EnclosureLeve;			/*0x1D */
3310
+	U8	EnclosureLevel;			/*0x1D */
32753311 	U16	SEPDevHandle;			/*0x1E */
3276
-	U32	Reserved3;			/*0x20 */
3277
-	U32	Reserved4;			/*0x24 */
3312
+	U8	OEMRD;				/*0x20 */
3313
+	U8	Reserved1a;			/*0x21 */
3314
+	U16	Reserved2;			/*0x22 */
3315
+	U32	Reserved3;			/*0x24 */
32783316 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
32793317 	*PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
32803318 	Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
....@@ -3285,6 +3323,8 @@
32853323 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
32863324 
32873325 /*values for SAS Enclosure Page 0 Flags field */
3326
+#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID          (0x0080)
3327
+#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING     (0x0040)
32883328 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID    (0x0020)
32893329 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
32903330 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
....@@ -3298,6 +3338,8 @@
32983338 #define MPI26_ENCLOSURE0_PAGEVERSION        (0x04)
32993339 
33003340 /*Values for Enclosure Page 0 Flags field */
3341
+#define MPI26_ENCLS0_FLAGS_OEMRD_VALID              (0x0080)
3342
+#define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING         (0x0040)
33013343 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID       (0x0020)
33023344 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID         (0x0010)
33033345 #define MPI26_ENCLS0_FLAGS_MNG_MASK                 (0x000F)
....@@ -3696,8 +3738,9 @@
36963738 	Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
36973739 
36983740 /*values for LinkFlags */
3699
-#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS    (0x00)
3700
-#define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS     (0x01)
3741
+#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK     (0x00)
3742
+#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN                 (0x01)
3743
+#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN                 (0x02)
37013744 
37023745 /*
37033746  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
....@@ -3714,7 +3757,7 @@
37143757 	U16	AdditionalControlFlags;             /*0x0C */
37153758 	U16	NVMeMaxQueueDepth;                  /*0x0E */
37163759 	U8	NumPhys;                            /*0x10 */
3717
-	U8	Reserved1;                          /*0x11 */
3760
+	U8	DMDReportPCIe;                      /*0x11 */
37183761 	U16	Reserved2;                          /*0x12 */
37193762 	MPI26_PCIE_IO_UNIT1_PHY_DATA
37203763 		PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */
....@@ -3735,6 +3778,12 @@
37353778 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0                              (0x30)
37363779 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0                              (0x40)
37373780 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0                             (0x50)
3781
+
3782
+/*values for PCIe IO Unit Page 1 DMDReportPCIe */
3783
+#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK                          (0x80)
3784
+#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC                         (0x00)
3785
+#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC                        (0x80)
3786
+#define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK                    (0x7F)
37383787 
37393788 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
37403789  *values
....@@ -3788,6 +3837,9 @@
37883837 
37893838 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
37903839 
3840
+/* defines for the Flags field */
3841
+#define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE         (0x0002)
3842
+#define MPI26_PCIESWITCH1_RETIMER_PRESENCE           (0x0001)
37913843 
37923844 /****************************************************************************
37933845 *  PCIe Device Config Pages (MPI v2.6 and later)
....@@ -3849,19 +3901,21 @@
38493901  *field
38503902  */
38513903 
3852
-/*values for PCIe Device Page 0 Flags field */
3853
-#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE            (0x8000)
3854
-#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH              (0x4000)
3855
-#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE              (0x2000)
3856
-#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION      (0x0400)
3857
-#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION            (0x0200)
3858
-#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE             (0x0100)
3859
-#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED        (0x0080)
3860
-#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED            (0x0040)
3861
-#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED              (0x0020)
3862
-#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED              (0x0010)
3863
-#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID               (0x0002)
3864
-#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT                 (0x0001)
3904
+/*values for PCIe Device Page 0 Flags field*/
3905
+#define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE             (0x00020000)
3906
+#define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE               (0x00010000)
3907
+#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE            (0x00008000)
3908
+#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH              (0x00004000)
3909
+#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE              (0x00002000)
3910
+#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION      (0x00000400)
3911
+#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION            (0x00000200)
3912
+#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE             (0x00000100)
3913
+#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED        (0x00000080)
3914
+#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED            (0x00000040)
3915
+#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED              (0x00000020)
3916
+#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED              (0x00000010)
3917
+#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID               (0x00000002)
3918
+#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT                 (0x00000001)
38653919 
38663920 /* values for PCIe Device Page 0 SupportedLinkRates field */
38673921 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED             (0x08)
....@@ -3882,7 +3936,13 @@
38823936 	U32	MaximumDataTransferSize;	/*0x0C */
38833937 	U32	Capabilities;		/*0x10 */
38843938 	U16	NOIOB;		/* 0x14 */
3885
-	U16	Reserved2;		/* 0x16 */
3939
+	U16     ShutdownLatency;        /* 0x16 */
3940
+	U16     VendorID;               /* 0x18 */
3941
+	U16     DeviceID;               /* 0x1A */
3942
+	U16     SubsystemVendorID;      /* 0x1C */
3943
+	U16     SubsystemID;            /* 0x1E */
3944
+	U8      RevisionID;             /* 0x20 */
3945
+	U8      Reserved21[3];          /* 0x21 */
38863946 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
38873947 	Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
38883948