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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/pwm/pwm-crc.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2015 Intel Corporation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License version
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- * 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
124  *
135  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
146  */
....@@ -29,8 +21,8 @@
2921 
3022 #define PWM_MAX_LEVEL		0xFF
3123 
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-#define PWM_BASE_CLK		6000000  /* 6 MHz */
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-#define PWM_MAX_PERIOD_NS	21333    /* 46.875KHz */
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+#define PWM_BASE_CLK_MHZ	6	/* 6 MHz */
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+#define PWM_MAX_PERIOD_NS	5461334	/* 183 Hz */
3426 
3527 /**
3628  * struct crystalcove_pwm - Crystal Cove PWM controller
....@@ -47,59 +39,121 @@
4739 	return container_of(pc, struct crystalcove_pwm, chip);
4840 }
4941 
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-static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
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+static int crc_pwm_calc_clk_div(int period_ns)
5143 {
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-	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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+	int clk_div;
5345 
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-	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
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+	clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
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+	/* clk_div 1 - 128, maps to register values 0-127 */
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+	if (clk_div > 0)
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+		clk_div--;
5550 
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-	return 0;
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+	return clk_div;
5752 }
5853 
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-static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm)
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+static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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+			 const struct pwm_state *state)
6056 {
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-	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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-
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-	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
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-}
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-
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-static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
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-			  int duty_ns, int period_ns)
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-{
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-	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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+	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
7058 	struct device *dev = crc_pwm->chip.dev;
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-	int level;
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+	int err;
7260 
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-	if (period_ns > PWM_MAX_PERIOD_NS) {
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+	if (state->period > PWM_MAX_PERIOD_NS) {
7462 		dev_err(dev, "un-supported period_ns\n");
7563 		return -EINVAL;
7664 	}
7765 
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-	if (pwm_get_period(pwm) != period_ns) {
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-		int clk_div;
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+	if (state->polarity != PWM_POLARITY_NORMAL)
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+		return -EOPNOTSUPP;
8068 
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-		/* changing the clk divisor, need to disable fisrt */
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-		crc_pwm_disable(c, pwm);
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-		clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC;
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-
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-		regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
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-					clk_div | PWM_OUTPUT_ENABLE);
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-
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-		/* enable back */
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-		crc_pwm_enable(c, pwm);
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+	if (pwm_is_enabled(pwm) && !state->enabled) {
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+		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
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+		if (err) {
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+			dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
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+			return err;
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+		}
9075 	}
9176 
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-	/* change the pwm duty cycle */
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-	level = duty_ns * PWM_MAX_LEVEL / period_ns;
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-	regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
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+	if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||
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+	    pwm_get_period(pwm) != state->period) {
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+		u64 level = state->duty_cycle * PWM_MAX_LEVEL;
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+
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+		do_div(level, state->period);
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+
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+		err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
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+		if (err) {
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+			dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
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+			return err;
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+		}
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+	}
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+
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+	if (pwm_is_enabled(pwm) && state->enabled &&
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+	    pwm_get_period(pwm) != state->period) {
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+		/* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
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+		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
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+		if (err) {
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+			dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
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+			return err;
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+		}
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+	}
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+
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+	if (pwm_get_period(pwm) != state->period ||
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+	    pwm_is_enabled(pwm) != state->enabled) {
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+		int clk_div = crc_pwm_calc_clk_div(state->period);
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+		int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;
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+
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+		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
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+				   clk_div | pwm_output_enable);
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+		if (err) {
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+			dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
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+			return err;
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+		}
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+	}
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+
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+	if (!pwm_is_enabled(pwm) && state->enabled) {
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+		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
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+		if (err) {
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+			dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
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+			return err;
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+		}
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+	}
95120 
96121 	return 0;
97122 }
98123 
124
+static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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+			      struct pwm_state *state)
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+{
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+	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
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+	struct device *dev = crc_pwm->chip.dev;
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+	unsigned int clk_div, clk_div_reg, duty_cycle_reg;
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+	int error;
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+
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+	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
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+	if (error) {
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+		dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
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+		return;
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+	}
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+
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+	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
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+	if (error) {
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+		dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
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+		return;
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+	}
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+
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+	clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
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+
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+	state->period =
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+		DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
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+	state->duty_cycle =
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+		DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
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+	state->polarity = PWM_POLARITY_NORMAL;
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+	state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
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+}
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+
99154 static const struct pwm_ops crc_pwm_ops = {
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-	.config = crc_pwm_config,
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-	.enable = crc_pwm_enable,
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-	.disable = crc_pwm_disable,
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+	.apply = crc_pwm_apply,
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+	.get_state = crc_pwm_get_state,
103157 };
104158 
105159 static int crystalcove_pwm_probe(struct platform_device *pdev)