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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/pwm/pwm-atmel.c
....@@ -1,10 +1,22 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Driver for Atmel Pulse Width Modulation Controller
34  *
45  * Copyright (C) 2013 Atmel Corporation
56  *		 Bo Shen <voice.shen@atmel.com>
67  *
7
- * Licensed under GPLv2.
8
+ * Links to reference manuals for the supported PWM chips can be found in
9
+ * Documentation/arm/microchip.rst.
10
+ *
11
+ * Limitations:
12
+ * - Periods start with the inactive level.
13
+ * - Hardware has to be stopped in general to update settings.
14
+ *
15
+ * Software bugs/possible improvements:
16
+ * - When atmel_pwm_apply() is called with state->enabled=false a change in
17
+ *   state->polarity isn't honored.
18
+ * - Instead of sleeping to wait for a completed period, the interrupt
19
+ *   functionality could be used.
820  */
921 
1022 #include <linux/clk.h>
....@@ -48,15 +60,7 @@
4860 #define PWMV2_CPRD		0x0C
4961 #define PWMV2_CPRDUPD		0x10
5062 
51
-/*
52
- * Max value for duty and period
53
- *
54
- * Although the duty and period register is 32 bit,
55
- * however only the LSB 16 bits are significant.
56
- */
57
-#define PWM_MAX_DTY		0xFFFF
58
-#define PWM_MAX_PRD		0xFFFF
59
-#define PRD_MAX_PRES		10
63
+#define PWM_MAX_PRES		10
6064 
6165 struct atmel_pwm_registers {
6266 	u8 period;
....@@ -65,11 +69,20 @@
6569 	u8 duty_upd;
6670 };
6771 
72
+struct atmel_pwm_config {
73
+	u32 period_bits;
74
+};
75
+
76
+struct atmel_pwm_data {
77
+	struct atmel_pwm_registers regs;
78
+	struct atmel_pwm_config cfg;
79
+};
80
+
6881 struct atmel_pwm_chip {
6982 	struct pwm_chip chip;
7083 	struct clk *clk;
7184 	void __iomem *base;
72
-	const struct atmel_pwm_registers *regs;
85
+	const struct atmel_pwm_data *data;
7386 
7487 	unsigned int updated_pwms;
7588 	/* ISR is cleared when read, ensure only one thread does that */
....@@ -98,7 +111,7 @@
98111 {
99112 	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
100113 
101
-	return readl_relaxed(chip->base + base + offset);
114
+	return atmel_pwm_readl(chip, base + offset);
102115 }
103116 
104117 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
....@@ -107,7 +120,7 @@
107120 {
108121 	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
109122 
110
-	writel_relaxed(val, chip->base + base + offset);
123
+	atmel_pwm_writel(chip, base + offset, val);
111124 }
112125 
113126 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
....@@ -116,17 +129,27 @@
116129 {
117130 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
118131 	unsigned long long cycles = state->period;
132
+	int shift;
119133 
120134 	/* Calculate the period cycles and prescale value */
121135 	cycles *= clk_get_rate(atmel_pwm->clk);
122136 	do_div(cycles, NSEC_PER_SEC);
123137 
124
-	for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
125
-		(*pres)++;
138
+	/*
139
+	 * The register for the period length is cfg.period_bits bits wide.
140
+	 * So for each bit the number of clock cycles is wider divide the input
141
+	 * clock frequency by two using pres and shift cprd accordingly.
142
+	 */
143
+	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
126144 
127
-	if (*pres > PRD_MAX_PRES) {
145
+	if (shift > PWM_MAX_PRES) {
128146 		dev_err(chip->dev, "pres exceeds the maximum value\n");
129147 		return -EINVAL;
148
+	} else if (shift > 0) {
149
+		*pres = shift;
150
+		cycles >>= *pres;
151
+	} else {
152
+		*pres = 0;
130153 	}
131154 
132155 	*cprd = cycles;
....@@ -150,15 +173,15 @@
150173 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
151174 	u32 val;
152175 
153
-	if (atmel_pwm->regs->duty_upd ==
154
-	    atmel_pwm->regs->period_upd) {
176
+	if (atmel_pwm->data->regs.duty_upd ==
177
+	    atmel_pwm->data->regs.period_upd) {
155178 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
156179 		val &= ~PWM_CMR_UPD_CDTY;
157180 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
158181 	}
159182 
160183 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
161
-			    atmel_pwm->regs->duty_upd, cdty);
184
+			    atmel_pwm->data->regs.duty_upd, cdty);
162185 }
163186 
164187 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
....@@ -168,9 +191,9 @@
168191 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
169192 
170193 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
171
-			    atmel_pwm->regs->duty, cdty);
194
+			    atmel_pwm->data->regs.duty, cdty);
172195 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
173
-			    atmel_pwm->regs->period, cprd);
196
+			    atmel_pwm->data->regs.period, cprd);
174197 }
175198 
176199 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
....@@ -210,7 +233,7 @@
210233 }
211234 
212235 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
213
-			   struct pwm_state *state)
236
+			   const struct pwm_state *state)
214237 {
215238 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
216239 	struct pwm_state cstate;
....@@ -225,7 +248,7 @@
225248 		    cstate.polarity == state->polarity &&
226249 		    cstate.period == state->period) {
227250 			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
228
-						  atmel_pwm->regs->period);
251
+						  atmel_pwm->data->regs.period);
229252 			atmel_pwm_calculate_cdty(state, cprd, &cdty);
230253 			atmel_pwm_update_cdty(chip, pwm, cdty);
231254 			return 0;
....@@ -272,81 +295,122 @@
272295 	return 0;
273296 }
274297 
298
+static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
299
+				struct pwm_state *state)
300
+{
301
+	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
302
+	u32 sr, cmr;
303
+
304
+	sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
305
+	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
306
+
307
+	if (sr & (1 << pwm->hwpwm)) {
308
+		unsigned long rate = clk_get_rate(atmel_pwm->clk);
309
+		u32 cdty, cprd, pres;
310
+		u64 tmp;
311
+
312
+		pres = cmr & PWM_CMR_CPRE_MSK;
313
+
314
+		cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
315
+					  atmel_pwm->data->regs.period);
316
+		tmp = (u64)cprd * NSEC_PER_SEC;
317
+		tmp <<= pres;
318
+		state->period = DIV64_U64_ROUND_UP(tmp, rate);
319
+
320
+		cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
321
+					  atmel_pwm->data->regs.duty);
322
+		tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
323
+		tmp <<= pres;
324
+		state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
325
+
326
+		state->enabled = true;
327
+	} else {
328
+		state->enabled = false;
329
+	}
330
+
331
+	if (cmr & PWM_CMR_CPOL)
332
+		state->polarity = PWM_POLARITY_INVERSED;
333
+	else
334
+		state->polarity = PWM_POLARITY_NORMAL;
335
+}
336
+
275337 static const struct pwm_ops atmel_pwm_ops = {
276338 	.apply = atmel_pwm_apply,
339
+	.get_state = atmel_pwm_get_state,
277340 	.owner = THIS_MODULE,
278341 };
279342 
280
-static const struct atmel_pwm_registers atmel_pwm_regs_v1 = {
281
-	.period		= PWMV1_CPRD,
282
-	.period_upd	= PWMV1_CUPD,
283
-	.duty		= PWMV1_CDTY,
284
-	.duty_upd	= PWMV1_CUPD,
285
-};
286
-
287
-static const struct atmel_pwm_registers atmel_pwm_regs_v2 = {
288
-	.period		= PWMV2_CPRD,
289
-	.period_upd	= PWMV2_CPRDUPD,
290
-	.duty		= PWMV2_CDTY,
291
-	.duty_upd	= PWMV2_CDTYUPD,
292
-};
293
-
294
-static const struct platform_device_id atmel_pwm_devtypes[] = {
295
-	{
296
-		.name = "at91sam9rl-pwm",
297
-		.driver_data = (kernel_ulong_t)&atmel_pwm_regs_v1,
298
-	}, {
299
-		.name = "sama5d3-pwm",
300
-		.driver_data = (kernel_ulong_t)&atmel_pwm_regs_v2,
301
-	}, {
302
-		/* sentinel */
343
+static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
344
+	.regs = {
345
+		.period		= PWMV1_CPRD,
346
+		.period_upd	= PWMV1_CUPD,
347
+		.duty		= PWMV1_CDTY,
348
+		.duty_upd	= PWMV1_CUPD,
349
+	},
350
+	.cfg = {
351
+		/* 16 bits to keep period and duty. */
352
+		.period_bits	= 16,
303353 	},
304354 };
305
-MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
355
+
356
+static const struct atmel_pwm_data atmel_sama5_pwm_data = {
357
+	.regs = {
358
+		.period		= PWMV2_CPRD,
359
+		.period_upd	= PWMV2_CPRDUPD,
360
+		.duty		= PWMV2_CDTY,
361
+		.duty_upd	= PWMV2_CDTYUPD,
362
+	},
363
+	.cfg = {
364
+		/* 16 bits to keep period and duty. */
365
+		.period_bits	= 16,
366
+	},
367
+};
368
+
369
+static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
370
+	.regs = {
371
+		.period		= PWMV1_CPRD,
372
+		.period_upd	= PWMV1_CUPD,
373
+		.duty		= PWMV1_CDTY,
374
+		.duty_upd	= PWMV1_CUPD,
375
+	},
376
+	.cfg = {
377
+		/* 32 bits to keep period and duty. */
378
+		.period_bits	= 32,
379
+	},
380
+};
306381 
307382 static const struct of_device_id atmel_pwm_dt_ids[] = {
308383 	{
309384 		.compatible = "atmel,at91sam9rl-pwm",
310
-		.data = &atmel_pwm_regs_v1,
385
+		.data = &atmel_sam9rl_pwm_data,
311386 	}, {
312387 		.compatible = "atmel,sama5d3-pwm",
313
-		.data = &atmel_pwm_regs_v2,
388
+		.data = &atmel_sama5_pwm_data,
314389 	}, {
315390 		.compatible = "atmel,sama5d2-pwm",
316
-		.data = &atmel_pwm_regs_v2,
391
+		.data = &atmel_sama5_pwm_data,
392
+	}, {
393
+		.compatible = "microchip,sam9x60-pwm",
394
+		.data = &mchp_sam9x60_pwm_data,
317395 	}, {
318396 		/* sentinel */
319397 	},
320398 };
321399 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
322400 
323
-static inline const struct atmel_pwm_registers *
324
-atmel_pwm_get_driver_data(struct platform_device *pdev)
325
-{
326
-	const struct platform_device_id *id;
327
-
328
-	if (pdev->dev.of_node)
329
-		return of_device_get_match_data(&pdev->dev);
330
-
331
-	id = platform_get_device_id(pdev);
332
-
333
-	return (struct atmel_pwm_registers *)id->driver_data;
334
-}
335
-
336401 static int atmel_pwm_probe(struct platform_device *pdev)
337402 {
338
-	const struct atmel_pwm_registers *regs;
339403 	struct atmel_pwm_chip *atmel_pwm;
340404 	struct resource *res;
341405 	int ret;
342406 
343
-	regs = atmel_pwm_get_driver_data(pdev);
344
-	if (!regs)
345
-		return -ENODEV;
346
-
347407 	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
348408 	if (!atmel_pwm)
349409 		return -ENOMEM;
410
+
411
+	mutex_init(&atmel_pwm->isr_lock);
412
+	atmel_pwm->data = of_device_get_match_data(&pdev->dev);
413
+	atmel_pwm->updated_pwms = 0;
350414 
351415 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
352416 	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
....@@ -365,17 +429,10 @@
365429 
366430 	atmel_pwm->chip.dev = &pdev->dev;
367431 	atmel_pwm->chip.ops = &atmel_pwm_ops;
368
-
369
-	if (pdev->dev.of_node) {
370
-		atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
371
-		atmel_pwm->chip.of_pwm_n_cells = 3;
372
-	}
373
-
432
+	atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
433
+	atmel_pwm->chip.of_pwm_n_cells = 3;
374434 	atmel_pwm->chip.base = -1;
375435 	atmel_pwm->chip.npwm = 4;
376
-	atmel_pwm->regs = regs;
377
-	atmel_pwm->updated_pwms = 0;
378
-	mutex_init(&atmel_pwm->isr_lock);
379436 
380437 	ret = pwmchip_add(&atmel_pwm->chip);
381438 	if (ret < 0) {
....@@ -407,7 +464,6 @@
407464 		.name = "atmel-pwm",
408465 		.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
409466 	},
410
-	.id_table = atmel_pwm_devtypes,
411467 	.probe = atmel_pwm_probe,
412468 	.remove = atmel_pwm_remove,
413469 };