forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/pinctrl/pinctrl-single.c
....@@ -42,6 +42,7 @@
4242  * struct pcs_func_vals - mux function register offset and value pair
4343  * @reg:	register virtual address
4444  * @val:	register value
45
+ * @mask:	mask
4546  */
4647 struct pcs_func_vals {
4748 	void __iomem *reg;
....@@ -83,6 +84,8 @@
8384  * @nvals:	number of entries in vals array
8485  * @pgnames:	array of pingroup names the function uses
8586  * @npgnames:	number of pingroup names the function uses
87
+ * @conf:	array of pin configurations
88
+ * @nconfs:	number of pin configurations available
8689  * @node:	list node
8790  */
8891 struct pcs_function {
....@@ -267,20 +270,44 @@
267270 	writel(val, reg);
268271 }
269272 
273
+static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
274
+					   unsigned int pin)
275
+{
276
+	unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
277
+
278
+	if (pcs->bits_per_mux) {
279
+		unsigned int pin_offset_bytes;
280
+
281
+		pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
282
+		return (pin_offset_bytes / mux_bytes) * mux_bytes;
283
+	}
284
+
285
+	return pin * mux_bytes;
286
+}
287
+
288
+static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
289
+					  unsigned int pin)
290
+{
291
+	return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
292
+}
293
+
270294 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
271295 					struct seq_file *s,
272296 					unsigned pin)
273297 {
274298 	struct pcs_device *pcs;
275
-	unsigned val, mux_bytes;
299
+	unsigned int val;
276300 	unsigned long offset;
277301 	size_t pa;
278302 
279303 	pcs = pinctrl_dev_get_drvdata(pctldev);
280304 
281
-	mux_bytes = pcs->width / BITS_PER_BYTE;
282
-	offset = pin * mux_bytes;
305
+	offset = pcs_pin_reg_offset_get(pcs, pin);
283306 	val = pcs->read(pcs->base + offset);
307
+
308
+	if (pcs->bits_per_mux)
309
+		val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
310
+
284311 	pa = pcs->res->start + offset;
285312 
286313 	seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
....@@ -381,7 +408,6 @@
381408 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
382409 	struct pcs_gpiofunc_range *frange = NULL;
383410 	struct list_head *pos, *tmp;
384
-	int mux_bytes = 0;
385411 	unsigned data;
386412 
387413 	/* If function mask is null, return directly. */
....@@ -389,29 +415,27 @@
389415 		return -ENOTSUPP;
390416 
391417 	list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
418
+		u32 offset;
419
+
392420 		frange = list_entry(pos, struct pcs_gpiofunc_range, node);
393421 		if (pin >= frange->offset + frange->npins
394422 			|| pin < frange->offset)
395423 			continue;
396
-		mux_bytes = pcs->width / BITS_PER_BYTE;
424
+
425
+		offset = pcs_pin_reg_offset_get(pcs, pin);
397426 
398427 		if (pcs->bits_per_mux) {
399
-			int byte_num, offset, pin_shift;
400
-
401
-			byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
402
-			offset = (byte_num / mux_bytes) * mux_bytes;
403
-			pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
404
-				    pcs->bits_per_pin;
428
+			int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
405429 
406430 			data = pcs->read(pcs->base + offset);
407431 			data &= ~(pcs->fmask << pin_shift);
408432 			data |= frange->gpiofunc << pin_shift;
409433 			pcs->write(data, pcs->base + offset);
410434 		} else {
411
-			data = pcs->read(pcs->base + pin * mux_bytes);
435
+			data = pcs->read(pcs->base + offset);
412436 			data &= ~pcs->fmask;
413437 			data |= frange->gpiofunc;
414
-			pcs->write(data, pcs->base + pin * mux_bytes);
438
+			pcs->write(data, pcs->base + offset);
415439 		}
416440 		break;
417441 	}
....@@ -560,7 +584,7 @@
560584 			case PIN_CONFIG_BIAS_PULL_UP:
561585 				if (arg)
562586 					pcs_pinconf_clear_bias(pctldev, pin);
563
-				/* fall through */
587
+				fallthrough;
564588 			case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
565589 				data &= ~func->conf[i].mask;
566590 				if (arg)
....@@ -654,8 +678,7 @@
654678  * @pcs: pcs driver instance
655679  * @offset: register offset from base
656680  */
657
-static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
658
-		unsigned pin_pos)
681
+static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
659682 {
660683 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
661684 	struct pinctrl_pin_desc *pin;
....@@ -703,7 +726,7 @@
703726 
704727 	mux_bytes = pcs->width / BITS_PER_BYTE;
705728 
706
-	if (pcs->bits_per_mux) {
729
+	if (pcs->bits_per_mux && pcs->fmask) {
707730 		pcs->bits_per_pin = fls(pcs->fmask);
708731 		nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
709732 		num_pins_in_register = pcs->width / pcs->bits_per_pin;
....@@ -724,17 +747,9 @@
724747 	for (i = 0; i < pcs->desc.npins; i++) {
725748 		unsigned offset;
726749 		int res;
727
-		int byte_num;
728
-		int pin_pos = 0;
729750 
730
-		if (pcs->bits_per_mux) {
731
-			byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
732
-			offset = (byte_num / mux_bytes) * mux_bytes;
733
-			pin_pos = i % num_pins_in_register;
734
-		} else {
735
-			offset = i * mux_bytes;
736
-		}
737
-		res = pcs_add_pin(pcs, offset, pin_pos);
751
+		offset = pcs_pin_reg_offset_get(pcs, i);
752
+		res = pcs_add_pin(pcs, offset);
738753 		if (res < 0) {
739754 			dev_err(pcs->dev, "error adding pins: %i\n", res);
740755 			return res;
....@@ -958,8 +973,7 @@
958973 }
959974 
960975 /**
961
- * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
962
- * @pctldev: pin controller device
976
+ * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
963977  * @pcs: pinctrl driver instance
964978  * @np: device node of the mux entry
965979  * @map: map entry
....@@ -1011,25 +1025,32 @@
10111025 		if (res)
10121026 			return res;
10131027 
1014
-		if (pinctrl_spec.args_count < 2) {
1028
+		if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
10151029 			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
10161030 				pinctrl_spec.args_count);
10171031 			break;
10181032 		}
10191033 
1020
-		/* Index plus one value cell */
10211034 		offset = pinctrl_spec.args[0];
10221035 		vals[found].reg = pcs->base + offset;
1023
-		vals[found].val = pinctrl_spec.args[1];
10241036 
1025
-		dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1026
-			pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1037
+		switch (pinctrl_spec.args_count) {
1038
+		case 2:
1039
+			vals[found].val = pinctrl_spec.args[1];
1040
+			break;
1041
+		case 3:
1042
+			vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1043
+			break;
1044
+		}
1045
+
1046
+		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1047
+			pinctrl_spec.np, offset, vals[found].val);
10271048 
10281049 		pin = pcs_get_pin_by_offset(pcs, offset);
10291050 		if (pin < 0) {
10301051 			dev_err(pcs->dev,
1031
-				"could not add functions for %s %ux\n",
1032
-				np->name, offset);
1052
+				"could not add functions for %pOFn %ux\n",
1053
+				np, offset);
10331054 			break;
10341055 		}
10351056 		pins[found++] = pin;
....@@ -1138,8 +1159,8 @@
11381159 		val = pinctrl_spec.args[1];
11391160 		mask = pinctrl_spec.args[2];
11401161 
1141
-		dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1142
-			pinctrl_spec.np->name, offset, val, mask);
1162
+		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1163
+			pinctrl_spec.np, offset, val, mask);
11431164 
11441165 		/* Parse pins in each row from LSB */
11451166 		while (mask) {
....@@ -1151,8 +1172,8 @@
11511172 
11521173 			if ((mask & mask_pos) == 0) {
11531174 				dev_err(pcs->dev,
1154
-					"Invalid mask for %s at 0x%x\n",
1155
-					np->name, offset);
1175
+					"Invalid mask for %pOFn at 0x%x\n",
1176
+					np, offset);
11561177 				break;
11571178 			}
11581179 
....@@ -1160,8 +1181,8 @@
11601181 
11611182 			if (submask != mask_pos) {
11621183 				dev_warn(pcs->dev,
1163
-						"Invalid submask 0x%x for %s at 0x%x\n",
1164
-						submask, np->name, offset);
1184
+						"Invalid submask 0x%x for %pOFn at 0x%x\n",
1185
+						submask, np, offset);
11651186 				continue;
11661187 			}
11671188 
....@@ -1172,8 +1193,8 @@
11721193 			pin = pcs_get_pin_by_offset(pcs, offset);
11731194 			if (pin < 0) {
11741195 				dev_err(pcs->dev,
1175
-					"could not add functions for %s %ux\n",
1176
-					np->name, offset);
1196
+					"could not add functions for %pOFn %ux\n",
1197
+					np, offset);
11771198 				break;
11781199 			}
11791200 			pins[found++] = pin + pin_num_from_lsb;
....@@ -1258,16 +1279,16 @@
12581279 		ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
12591280 				num_maps, pgnames);
12601281 		if (ret < 0) {
1261
-			dev_err(pcs->dev, "no pins entries for %s\n",
1262
-				np_config->name);
1282
+			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1283
+				np_config);
12631284 			goto free_pgnames;
12641285 		}
12651286 	} else {
12661287 		ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
12671288 				num_maps, pgnames);
12681289 		if (ret < 0) {
1269
-			dev_err(pcs->dev, "no pins entries for %s\n",
1270
-				np_config->name);
1290
+			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1291
+				np_config);
12711292 			goto free_pgnames;
12721293 		}
12731294 	}
....@@ -1347,7 +1368,9 @@
13471368 	}
13481369 	return ret;
13491370 }
1371
+
13501372 /**
1373
+ * struct pcs_interrupt
13511374  * @reg:	virtual address of interrupt register
13521375  * @hwirq:	hardware irq number
13531376  * @irq:	virtual irq number
....@@ -1362,6 +1385,9 @@
13621385 
13631386 /**
13641387  * pcs_irq_set() - enables or disables an interrupt
1388
+ * @pcs_soc: SoC specific settings
1389
+ * @irq: interrupt
1390
+ * @enable: enable or disable the interrupt
13651391  *
13661392  * Note that this currently assumes one interrupt per pinctrl
13671393  * register that is typically used for wake-up events.
....@@ -1442,7 +1468,7 @@
14421468 
14431469 /**
14441470  * pcs_irq_handle() - common interrupt handler
1445
- * @pcs_irq: interrupt data
1471
+ * @pcs_soc: SoC specific settings
14461472  *
14471473  * Note that this currently assumes we have one interrupt bit per
14481474  * mux register. This interrupt is typically used for wake-up events.
....@@ -1490,7 +1516,6 @@
14901516 
14911517 /**
14921518  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1493
- * @irq: interrupt
14941519  * @desc: interrupt descriptor
14951520  *
14961521  * Use this if you have a separate interrupt for each