~hc/RK356X_SDK_RELEASE.git

..	..	@@ -20,10 +20,10 @@
20	20	#include <linux/platform_device.h>
21	21	#include <linux/io.h>
22	22	#include <linux/bitops.h>
23		-#include <linux/gpio.h>
	23	+#include <linux/gpio/driver.h>
24	24	#include <linux/of_address.h>
25		-#include <linux/of_irq.h>
26	25	#include <linux/of_device.h>
	26	+#include <linux/of_irq.h>
27	27	#include <linux/pinctrl/machine.h>
28	28	#include <linux/pinctrl/pinconf.h>
29	29	#include <linux/pinctrl/pinctrl.h>
..	..	@@ -40,7 +40,7 @@
40	40	#include "pinconf.h"
41	41	#include "pinctrl-rockchip.h"
42	42
43		-/**
	43	+/*
44	44	* Generate a bitmask for setting a value (v) with a write mask bit in hiword
45	45	* register 31:16 area.
46	46	*/
..	..	@@ -117,6 +117,25 @@
117	117	{ .drv_type = type2, .offset = -1 }, \
118	118	{ .drv_type = type3, .offset = -1 }, \
119	119	}, \
	120	+ }
	121	+
	122	+#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
	123	+ iom2, iom3, pull0, pull1, \
	124	+ pull2, pull3) \
	125	+ { \
	126	+ .bank_num = id, \
	127	+ .nr_pins = pins, \
	128	+ .name = label, \
	129	+ .iomux = { \
	130	+ { .type = iom0, .offset = -1 }, \
	131	+ { .type = iom1, .offset = -1 }, \
	132	+ { .type = iom2, .offset = -1 }, \
	133	+ { .type = iom3, .offset = -1 }, \
	134	+ }, \
	135	+ .pull_type[0] = pull0, \
	136	+ .pull_type[1] = pull1, \
	137	+ .pull_type[2] = pull2, \
	138	+ .pull_type[3] = pull3, \
120	139	}
121	140
122	141	#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
..	..	@@ -204,7 +223,7 @@
204	223	.route_location = FLAG, \
205	224	}
206	225
207		-#define PX30S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
	226	+#define S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
208	227	PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(ID, PIN, LABEL, \
209	228	MTYPE, MTYPE, MTYPE, MTYPE, \
210	229	DTYPE, DTYPE, DTYPE, DTYPE, \
..	..	@@ -218,6 +237,12 @@
218	237
219	238	#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
220	239	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
	240	+
	241	+#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
	242	+ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
	243	+
	244	+static struct pinctrl_dev *g_pctldev;
	245	+static DEFINE_MUTEX(iomux_lock);
221	246
222	247	static struct regmap_config rockchip_regmap_config = {
223	248	.reg_bits = 32,
..	..	@@ -309,6 +334,7 @@
309	334	{
310	335	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
311	336	const struct rockchip_pin_group *grp;
	337	+ struct device *dev = info->dev;
312	338	struct pinctrl_map *new_map;
313	339	struct device_node *parent;
314	340	int map_num = 1;
..	..	@@ -320,8 +346,7 @@
320	346	*/
321	347	grp = pinctrl_name_to_group(info, np->name);
322	348	if (!grp) {
323		- dev_err(info->dev, "unable to find group for node %pOFn\n",
324		- np);
	349	+ dev_err(dev, "unable to find group for node %pOFn\n", np);
325	350	return -EINVAL;
326	351	}
327	352
..	..	@@ -355,7 +380,7 @@
355	380	new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
356	381	}
357	382
358		- dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
	383	+ dev_dbg(dev, "maps: function %s group %s num %d\n",
359	384	(map)->data.mux.function, (map)->data.mux.group, map_num);
360	385
361	386	return 0;
..	..	@@ -510,159 +535,110 @@
510	535
511	536	static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
512	537	{
	538	+ /* gpio1b6_sel */
513	539	.num = 1,
514	540	.pin = 14,
515	541	.reg = 0x28,
516	542	.bit = 12,
517	543	.mask = 0xf
518	544	}, {
	545	+ /* gpio1b7_sel */
519	546	.num = 1,
520	547	.pin = 15,
521	548	.reg = 0x2c,
522	549	.bit = 0,
523	550	.mask = 0x3
524	551	}, {
	552	+ /* gpio1c2_sel */
525	553	.num = 1,
526	554	.pin = 18,
527	555	.reg = 0x30,
528	556	.bit = 4,
529	557	.mask = 0xf
530	558	}, {
	559	+ /* gpio1c3_sel */
531	560	.num = 1,
532	561	.pin = 19,
533	562	.reg = 0x30,
534	563	.bit = 8,
535	564	.mask = 0xf
536	565	}, {
	566	+ /* gpio1c4_sel */
537	567	.num = 1,
538	568	.pin = 20,
539	569	.reg = 0x30,
540	570	.bit = 12,
541	571	.mask = 0xf
542	572	}, {
	573	+ /* gpio1c5_sel */
543	574	.num = 1,
544	575	.pin = 21,
545	576	.reg = 0x34,
546	577	.bit = 0,
547	578	.mask = 0xf
548	579	}, {
	580	+ /* gpio1c6_sel */
549	581	.num = 1,
550	582	.pin = 22,
551	583	.reg = 0x34,
552	584	.bit = 4,
553	585	.mask = 0xf
554	586	}, {
	587	+ /* gpio1c7_sel */
555	588	.num = 1,
556	589	.pin = 23,
557	590	.reg = 0x34,
558	591	.bit = 8,
559	592	.mask = 0xf
560	593	}, {
561		- .num = 3,
562		- .pin = 12,
563		- .reg = 0x68,
564		- .bit = 8,
565		- .mask = 0xf
566		- }, {
567		- .num = 3,
568		- .pin = 13,
569		- .reg = 0x68,
570		- .bit = 12,
571		- .mask = 0xf
572		- },
573		-};
574		-
575		-static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
576		- {
577		- .num = 1,
578		- .pin = 14,
579		- .reg = 0x28,
580		- .bit = 12,
581		- .mask = 0xf
582		- }, {
583		- .num = 1,
584		- .pin = 15,
585		- .reg = 0x2c,
586		- .bit = 0,
587		- .mask = 0x3
588		- }, {
589		- .num = 1,
590		- .pin = 18,
591		- .reg = 0x30,
592		- .bit = 4,
593		- .mask = 0xf
594		- }, {
595		- .num = 1,
596		- .pin = 19,
597		- .reg = 0x30,
598		- .bit = 8,
599		- .mask = 0xf
600		- }, {
601		- .num = 1,
602		- .pin = 20,
603		- .reg = 0x30,
604		- .bit = 12,
605		- .mask = 0xf
606		- }, {
607		- .num = 1,
608		- .pin = 21,
609		- .reg = 0x34,
610		- .bit = 0,
611		- .mask = 0xf
612		- }, {
613		- .num = 1,
614		- .pin = 22,
615		- .reg = 0x34,
616		- .bit = 4,
617		- .mask = 0xf
618		- }, {
619		- .num = 1,
620		- .pin = 23,
621		- .reg = 0x34,
622		- .bit = 8,
623		- .mask = 0xf
624		- }, {
625		- .num = 3,
626		- .pin = 12,
627		- .reg = 0x68,
628		- .bit = 8,
629		- .mask = 0xf
630		- }, {
631		- .num = 3,
632		- .pin = 13,
633		- .reg = 0x68,
634		- .bit = 12,
635		- .mask = 0xf
636		- }, {
	594	+ /* gpio2a2_sel_plus */
637	595	.num = 2,
638	596	.pin = 2,
639	597	.reg = 0x608,
640	598	.bit = 0,
641	599	.mask = 0x7
642	600	}, {
	601	+ /* gpio2a3_sel_plus */
643	602	.num = 2,
644	603	.pin = 3,
645	604	.reg = 0x608,
646	605	.bit = 4,
647	606	.mask = 0x7
648	607	}, {
	608	+ /* gpio2c0_sel_plus */
649	609	.num = 2,
650	610	.pin = 16,
651	611	.reg = 0x610,
652	612	.bit = 8,
653	613	.mask = 0x7
654	614	}, {
	615	+ /* gpio3b2_sel_plus */
655	616	.num = 3,
656	617	.pin = 10,
657	618	.reg = 0x610,
658	619	.bit = 0,
659	620	.mask = 0x7
660	621	}, {
	622	+ /* gpio3b3_sel_plus */
661	623	.num = 3,
662	624	.pin = 11,
663	625	.reg = 0x610,
664	626	.bit = 4,
665	627	.mask = 0x7
	628	+ }, {
	629	+ /* gpio3b4_sel */
	630	+ .num = 3,
	631	+ .pin = 12,
	632	+ .reg = 0x68,
	633	+ .bit = 8,
	634	+ .mask = 0xf
	635	+ }, {
	636	+ /* gpio3b5_sel */
	637	+ .num = 3,
	638	+ .pin = 13,
	639	+ .reg = 0x68,
	640	+ .bit = 12,
	641	+ .mask = 0xf
666	642	},
667	643	};
668	644
..	..	@@ -726,14 +702,23 @@
726	702
727	703	static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
728	704	RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
	705	+ RK_MUXROUTE_GRF(3, RK_PD1, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_RX_M0 */
	706	+ RK_MUXROUTE_GRF(3, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_TX_M0 */
729	707	RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
	708	+ RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_RX_M1 */
	709	+ RK_MUXROUTE_GRF(3, RK_PA4, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_TX_M1 */
730	710
731	711	RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
	712	+ RK_MUXROUTE_GRF(1, RK_PA1, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_SCLK_M0 */
732	713	RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
	714	+ RK_MUXROUTE_GRF(1, RK_PD6, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_SCLK_M1 */
733	715	RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
	716	+ RK_MUXROUTE_GRF(2, RK_PD1, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_SCLK_M2 */
734	717
735	718	RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
	719	+ RK_MUXROUTE_GRF(1, RK_PC6, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_SCLK_M0 */
736	720	RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
	721	+ RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_SCLK_M1 */
737	722
738	723	RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
739	724	RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
..	..	@@ -914,22 +899,6 @@
914	899	RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) \| BIT(0)), /* rtc_clk */
915	900	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3)), /* uart2_rxm0 */
916	901	RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3) \| BIT(2)), /* uart2_rxm1 */
917		- RK_MUXROUTE_SAME(0, RK_PC7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
918		- RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) \| BIT(4)), /* i2c3_sdam1 */
919		- RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
920		- RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
921		- RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) \| BIT(3)), /* i2s-8ch-1-sclktxm1 */
922		- RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) \| BIT(3)), /* i2s-8ch-1-sclkrxm1 */
923		- RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) \| BIT(16 + 13)), /* pdm-clkm0 */
924		- RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) \| BIT(16 + 13) \| BIT(12)), /* pdm-clkm1 */
925		- RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) \| BIT(16 + 13) \| BIT(13)), /* pdm-clkm2 */
926		- RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) \| BIT(2)), /* pdm-clkm-m2 */
927		-};
928		-
929		-static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
930		- RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) \| BIT(0)), /* rtc_clk */
931		- RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3)), /* uart2_rxm0 */
932		- RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3) \| BIT(2)), /* uart2_rxm1 */
933	902	RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) \| BIT(16 + 9)), /* i2c3_sdam0 */
934	903	RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) \| BIT(16 + 9) \| BIT(8)), /* i2c3_sdam1 */
935	904	RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) \| BIT(16 + 9) \| BIT(9)), /* i2c3_sdam2 */
..	..	@@ -963,7 +932,9 @@
963	932	RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
964	933	RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) \| BIT(3)), /* pdm_sdi0m1 */
965	934	RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) \| BIT(16 + 5) \| BIT(5)), /* spi_rxdm2 */
	935	+ RK_MUXROUTE_SAME(1, RK_PC6, 1, 0x50, BIT(16 + 6)), /* i2s2_sclkm0 */
966	936	RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
	937	+ RK_MUXROUTE_SAME(3, RK_PA0, 6, 0x50, BIT(16 + 6) \| BIT(6)), /* i2s2_sclkm1 */
967	938	RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) \| BIT(6)), /* i2s2_sdim1 */
968	939	RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) \| BIT(7)), /* card_iom1 */
969	940	RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) \| BIT(8)), /* tsp_d5m1 */
..	..	@@ -1052,25 +1023,25 @@
1052	1023	RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1053	1024	RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1054	1025	RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1055		- RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1056		- RK_MUXROUTE_GRF(1, RK_PA3, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux sclk tx M0 */
1057		- RK_MUXROUTE_GRF(1, RK_PA4, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux sclk rx M0 */
1058		- RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1059		- RK_MUXROUTE_GRF(3, RK_PC7, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux sclk tx M1 */
1060		- RK_MUXROUTE_GRF(4, RK_PA6, 5, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux sclk rx M1 */
1061		- RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1062		- RK_MUXROUTE_GRF(2, RK_PD1, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux sclk tx M2 */
1063		- RK_MUXROUTE_GRF(3, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux sclk rx M2 */
1064		- RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1065		- RK_MUXROUTE_GRF(2, RK_PC2, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux sclk tx M0 */
1066		- RK_MUXROUTE_GRF(2, RK_PB7, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux sclk rx M0 */
1067		- RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1068		- RK_MUXROUTE_GRF(4, RK_PB7, 4, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S1 IO mux sclk tx M1 */
1069		- RK_MUXROUTE_GRF(4, RK_PC1, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S1 IO mux sclk rx M1 */
1070		- RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1071		- RK_MUXROUTE_GRF(3, RK_PA3, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux sclk M0 */
1072		- RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1073		- RK_MUXROUTE_GRF(4, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux sclk M1 */
	1026	+ RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 MCLK mux M0 */
	1027	+ RK_MUXROUTE_GRF(1, RK_PA4, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 SCLKRX mux M0 */
	1028	+ RK_MUXROUTE_GRF(1, RK_PA3, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 SCLKTX mux M0 */
	1029	+ RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 MCLK mux M1 */
	1030	+ RK_MUXROUTE_GRF(4, RK_PA6, 5, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 SCLKRX mux M1 */
	1031	+ RK_MUXROUTE_GRF(3, RK_PC7, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 SCLKTX mux M1 */
	1032	+ RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 MCLK mux M2 */
	1033	+ RK_MUXROUTE_GRF(3, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 SCLKRX mux M2 */
	1034	+ RK_MUXROUTE_GRF(2, RK_PD1, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 SCLKTX mux M2 */
	1035	+ RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 MCLK mux M0 */
	1036	+ RK_MUXROUTE_GRF(2, RK_PB7, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 SCLKRX mux M0 */
	1037	+ RK_MUXROUTE_GRF(2, RK_PC2, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 SCLKTX mux M0 */
	1038	+ RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 MCLK mux M1 */
	1039	+ RK_MUXROUTE_GRF(4, RK_PC1, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 SCLKRX mux M1 */
	1040	+ RK_MUXROUTE_GRF(4, RK_PB7, 4, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 SCLKTX mux M1 */
	1041	+ RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 MCLK mux M0 */
	1042	+ RK_MUXROUTE_GRF(3, RK_PA3, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 SCLK mux M0 */
	1043	+ RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 MCLK mux M1 */
	1044	+ RK_MUXROUTE_GRF(4, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 SCLK mux M1 */
1074	1045	RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1075	1046	RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1076	1047	RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
..	..	@@ -1115,6 +1086,7 @@
1115	1086	static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1116	1087	{
1117	1088	struct rockchip_pinctrl *info = bank->drvdata;
	1089	+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
1118	1090	int iomux_num = (pin / 8);
1119	1091	struct regmap *regmap;
1120	1092	unsigned int val;
..	..	@@ -1160,6 +1132,27 @@
1160	1132	if (bank->recalced_mask & BIT(pin))
1161	1133	rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1162	1134
	1135	+ if (ctrl->type == RK3588) {
	1136	+ if (bank->bank_num == 0) {
	1137	+ if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
	1138	+ u32 reg0 = 0;
	1139	+
	1140	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1141	+ ret = regmap_read(regmap, reg0, &val);
	1142	+ if (ret)
	1143	+ return ret;
	1144	+
	1145	+ if (((val >> bit) & mask) != 8)
	1146	+ return ((val >> bit) & mask);
	1147	+
	1148	+ reg = reg + 0x8000; /* BUS_IOC_BASE */
	1149	+ regmap = info->regmap_base;
	1150	+ }
	1151	+ } else if (bank->bank_num > 0) {
	1152	+ reg += 0x8000; /* BUS_IOC_BASE */
	1153	+ }
	1154	+ }
	1155	+
1163	1156	ret = regmap_read(regmap, reg, &val);
1164	1157	if (ret)
1165	1158	return ret;
..	..	@@ -1171,20 +1164,20 @@
1171	1164	int pin, int mux)
1172	1165	{
1173	1166	struct rockchip_pinctrl *info = bank->drvdata;
	1167	+ struct device *dev = info->dev;
1174	1168	int iomux_num = (pin / 8);
1175	1169
1176	1170	if (iomux_num > 3)
1177	1171	return -EINVAL;
1178	1172
1179	1173	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1180		- dev_err(info->dev, "pin %d is unrouted\n", pin);
	1174	+ dev_err(dev, "pin %d is unrouted\n", pin);
1181	1175	return -EINVAL;
1182	1176	}
1183	1177
1184	1178	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1185	1179	if (mux != RK_FUNC_GPIO) {
1186		- dev_err(info->dev,
1187		- "pin %d only supports a gpio mux\n", pin);
	1180	+ dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1188	1181	return -ENOTSUPP;
1189	1182	}
1190	1183	}
..	..	@@ -1208,6 +1201,8 @@
1208	1201	static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1209	1202	{
1210	1203	struct rockchip_pinctrl *info = bank->drvdata;
	1204	+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
	1205	+ struct device *dev = info->dev;
1211	1206	int iomux_num = (pin / 8);
1212	1207	struct regmap *regmap;
1213	1208	int reg, ret, mask, mux_type;
..	..	@@ -1221,8 +1216,7 @@
1221	1216	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1222	1217	return 0;
1223	1218
1224		- dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1225		- bank->bank_num, pin, mux);
	1219	+ dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1226	1220
1227	1221	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1228	1222	regmap = info->regmap_pmu;
..	..	@@ -1251,6 +1245,64 @@
1251	1245
1252	1246	if (bank->recalced_mask & BIT(pin))
1253	1247	rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
	1248	+
	1249	+ /* rk3562 force jtag m1 */
	1250	+ if (ctrl->type == RK3562) {
	1251	+ if (bank->bank_num == 1) {
	1252	+ if ((pin == RK_PB5) \|\| (pin == RK_PB6)) {
	1253	+ if (mux == 1) {
	1254	+ regmap_update_bits(regmap, 0x504, 0x10001, 0x10001);
	1255	+ } else {
	1256	+ regmap_update_bits(regmap, 0x504, 0x10001, 0x10000);
	1257	+ }
	1258	+ }
	1259	+ }
	1260	+ }
	1261	+
	1262	+ if (ctrl->type == RK3588) {
	1263	+ if (bank->bank_num == 0) {
	1264	+ if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
	1265	+ if (mux < 8) {
	1266	+ u32 reg0 = 0;
	1267	+
	1268	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1269	+ data = (mask << (bit + 16));
	1270	+ rmask = data \| (data >> 16);
	1271	+ data \|= (mux & mask) << bit;
	1272	+ ret = regmap_update_bits(regmap, reg0, rmask, data);
	1273	+
	1274	+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
	1275	+ data = (mask << (bit + 16));
	1276	+ rmask = data \| (data >> 16);
	1277	+ regmap = info->regmap_base;
	1278	+ ret \|= regmap_update_bits(regmap, reg0, rmask, data);
	1279	+ } else {
	1280	+ u32 reg0 = 0;
	1281	+
	1282	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1283	+ data = (mask << (bit + 16));
	1284	+ rmask = data \| (data >> 16);
	1285	+ data \|= 8 << bit;
	1286	+ ret = regmap_update_bits(regmap, reg0, rmask, data);
	1287	+
	1288	+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
	1289	+ data = (mask << (bit + 16));
	1290	+ rmask = data \| (data >> 16);
	1291	+ data \|= (mux & mask) << bit;
	1292	+ regmap = info->regmap_base;
	1293	+ ret \|= regmap_update_bits(regmap, reg0, rmask, data);
	1294	+ }
	1295	+ } else {
	1296	+ data = (mask << (bit + 16));
	1297	+ rmask = data \| (data >> 16);
	1298	+ data \|= (mux & mask) << bit;
	1299	+ ret = regmap_update_bits(regmap, reg, rmask, data);
	1300	+ }
	1301	+ return ret;
	1302	+ } else if (bank->bank_num > 0) {
	1303	+ reg += 0x8000; /* BUS_IOC_BASE */
	1304	+ }
	1305	+ }
1254	1306
1255	1307	if (mux > mask)
1256	1308	return -EINVAL;
..	..	@@ -1300,9 +1352,9 @@
1300	1352	#define PX30_PULL_PINS_PER_REG 8
1301	1353	#define PX30_PULL_BANK_STRIDE 16
1302	1354
1303		-static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1304		- int pin_num, struct regmap **regmap,
1305		- int reg, u8 bit)
	1355	+static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1356	+ int pin_num, struct regmap **regmap,
	1357	+ int reg, u8 bit)
1306	1358	{
1307	1359	struct rockchip_pinctrl *info = bank->drvdata;
1308	1360
..	..	@@ -1322,6 +1374,8 @@
1322	1374	reg += ((pin_num / PX30_PULL_PINS_PER_REG) 4);
1323	1375	*bit = (pin_num % PX30_PULL_PINS_PER_REG);
1324	1376	bit = PX30_PULL_BITS_PER_PIN;
	1377	+
	1378	+ return 0;
1325	1379	}
1326	1380
1327	1381	#define PX30_DRV_PMU_OFFSET 0x20
..	..	@@ -1330,9 +1384,9 @@
1330	1384	#define PX30_DRV_PINS_PER_REG 8
1331	1385	#define PX30_DRV_BANK_STRIDE 16
1332	1386
1333		-static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1334		- int pin_num, struct regmap **regmap,
1335		- int reg, u8 bit)
	1387	+static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1388	+ int pin_num, struct regmap **regmap,
	1389	+ int reg, u8 bit)
1336	1390	{
1337	1391	struct rockchip_pinctrl *info = bank->drvdata;
1338	1392
..	..	@@ -1352,6 +1406,8 @@
1352	1406	reg += ((pin_num / PX30_DRV_PINS_PER_REG) 4);
1353	1407	*bit = (pin_num % PX30_DRV_PINS_PER_REG);
1354	1408	bit = PX30_DRV_BITS_PER_PIN;
	1409	+
	1410	+ return 0;
1355	1411	}
1356	1412
1357	1413	#define PX30_SCHMITT_PMU_OFFSET 0x38
..	..	@@ -1385,15 +1441,175 @@
1385	1441	return 0;
1386	1442	}
1387	1443
	1444	+#define RV1106_DRV_BITS_PER_PIN 8
	1445	+#define RV1106_DRV_PINS_PER_REG 2
	1446	+#define RV1106_DRV_GPIO0_OFFSET 0x10
	1447	+#define RV1106_DRV_GPIO1_OFFSET 0x80
	1448	+#define RV1106_DRV_GPIO2_OFFSET 0x100C0
	1449	+#define RV1106_DRV_GPIO3_OFFSET 0x20100
	1450	+#define RV1106_DRV_GPIO4_OFFSET 0x30020
	1451	+
	1452	+static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1453	+ int pin_num, struct regmap **regmap,
	1454	+ int reg, u8 bit)
	1455	+{
	1456	+ struct rockchip_pinctrl *info = bank->drvdata;
	1457	+
	1458	+ /* GPIO0_IOC is located in PMU */
	1459	+ switch (bank->bank_num) {
	1460	+ case 0:
	1461	+ *regmap = info->regmap_pmu;
	1462	+ *reg = RV1106_DRV_GPIO0_OFFSET;
	1463	+ break;
	1464	+
	1465	+ case 1:
	1466	+ *regmap = info->regmap_base;
	1467	+ *reg = RV1106_DRV_GPIO1_OFFSET;
	1468	+ break;
	1469	+
	1470	+ case 2:
	1471	+ *regmap = info->regmap_base;
	1472	+ *reg = RV1106_DRV_GPIO2_OFFSET;
	1473	+ break;
	1474	+
	1475	+ case 3:
	1476	+ *regmap = info->regmap_base;
	1477	+ *reg = RV1106_DRV_GPIO3_OFFSET;
	1478	+ break;
	1479	+
	1480	+ case 4:
	1481	+ *regmap = info->regmap_base;
	1482	+ *reg = RV1106_DRV_GPIO4_OFFSET;
	1483	+ break;
	1484	+
	1485	+ default:
	1486	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1487	+ break;
	1488	+ }
	1489	+
	1490	+ reg += ((pin_num / RV1106_DRV_PINS_PER_REG) 4);
	1491	+ *bit = pin_num % RV1106_DRV_PINS_PER_REG;
	1492	+ bit = RV1106_DRV_BITS_PER_PIN;
	1493	+
	1494	+ return 0;
	1495	+}
	1496	+
	1497	+#define RV1106_PULL_BITS_PER_PIN 2
	1498	+#define RV1106_PULL_PINS_PER_REG 8
	1499	+#define RV1106_PULL_GPIO0_OFFSET 0x38
	1500	+#define RV1106_PULL_GPIO1_OFFSET 0x1C0
	1501	+#define RV1106_PULL_GPIO2_OFFSET 0x101D0
	1502	+#define RV1106_PULL_GPIO3_OFFSET 0x201E0
	1503	+#define RV1106_PULL_GPIO4_OFFSET 0x30070
	1504	+
	1505	+static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1506	+ int pin_num, struct regmap **regmap,
	1507	+ int reg, u8 bit)
	1508	+{
	1509	+ struct rockchip_pinctrl *info = bank->drvdata;
	1510	+
	1511	+ /* GPIO0_IOC is located in PMU */
	1512	+ switch (bank->bank_num) {
	1513	+ case 0:
	1514	+ *regmap = info->regmap_pmu;
	1515	+ *reg = RV1106_PULL_GPIO0_OFFSET;
	1516	+ break;
	1517	+
	1518	+ case 1:
	1519	+ *regmap = info->regmap_base;
	1520	+ *reg = RV1106_PULL_GPIO1_OFFSET;
	1521	+ break;
	1522	+
	1523	+ case 2:
	1524	+ *regmap = info->regmap_base;
	1525	+ *reg = RV1106_PULL_GPIO2_OFFSET;
	1526	+ break;
	1527	+
	1528	+ case 3:
	1529	+ *regmap = info->regmap_base;
	1530	+ *reg = RV1106_PULL_GPIO3_OFFSET;
	1531	+ break;
	1532	+
	1533	+ case 4:
	1534	+ *regmap = info->regmap_base;
	1535	+ *reg = RV1106_PULL_GPIO4_OFFSET;
	1536	+ break;
	1537	+
	1538	+ default:
	1539	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1540	+ break;
	1541	+ }
	1542	+
	1543	+ reg += ((pin_num / RV1106_PULL_PINS_PER_REG) 4);
	1544	+ *bit = pin_num % RV1106_PULL_PINS_PER_REG;
	1545	+ bit = RV1106_PULL_BITS_PER_PIN;
	1546	+
	1547	+ return 0;
	1548	+}
	1549	+
	1550	+#define RV1106_SMT_BITS_PER_PIN 1
	1551	+#define RV1106_SMT_PINS_PER_REG 8
	1552	+#define RV1106_SMT_GPIO0_OFFSET 0x40
	1553	+#define RV1106_SMT_GPIO1_OFFSET 0x280
	1554	+#define RV1106_SMT_GPIO2_OFFSET 0x10290
	1555	+#define RV1106_SMT_GPIO3_OFFSET 0x202A0
	1556	+#define RV1106_SMT_GPIO4_OFFSET 0x300A0
	1557	+
	1558	+static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1559	+ int pin_num,
	1560	+ struct regmap **regmap,
	1561	+ int reg, u8 bit)
	1562	+{
	1563	+ struct rockchip_pinctrl *info = bank->drvdata;
	1564	+
	1565	+ /* GPIO0_IOC is located in PMU */
	1566	+ switch (bank->bank_num) {
	1567	+ case 0:
	1568	+ *regmap = info->regmap_pmu;
	1569	+ *reg = RV1106_SMT_GPIO0_OFFSET;
	1570	+ break;
	1571	+
	1572	+ case 1:
	1573	+ *regmap = info->regmap_base;
	1574	+ *reg = RV1106_SMT_GPIO1_OFFSET;
	1575	+ break;
	1576	+
	1577	+ case 2:
	1578	+ *regmap = info->regmap_base;
	1579	+ *reg = RV1106_SMT_GPIO2_OFFSET;
	1580	+ break;
	1581	+
	1582	+ case 3:
	1583	+ *regmap = info->regmap_base;
	1584	+ *reg = RV1106_SMT_GPIO3_OFFSET;
	1585	+ break;
	1586	+
	1587	+ case 4:
	1588	+ *regmap = info->regmap_base;
	1589	+ *reg = RV1106_SMT_GPIO4_OFFSET;
	1590	+ break;
	1591	+
	1592	+ default:
	1593	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1594	+ break;
	1595	+ }
	1596	+
	1597	+ reg += ((pin_num / RV1106_SMT_PINS_PER_REG) 4);
	1598	+ *bit = pin_num % RV1106_SMT_PINS_PER_REG;
	1599	+ bit = RV1106_SMT_BITS_PER_PIN;
	1600	+
	1601	+ return 0;
	1602	+}
	1603	+
1388	1604	#define RV1108_PULL_PMU_OFFSET 0x10
1389	1605	#define RV1108_PULL_OFFSET 0x110
1390	1606	#define RV1108_PULL_PINS_PER_REG 8
1391	1607	#define RV1108_PULL_BITS_PER_PIN 2
1392	1608	#define RV1108_PULL_BANK_STRIDE 16
1393	1609
1394		-static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1395		- int pin_num, struct regmap **regmap,
1396		- int reg, u8 bit)
	1610	+static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1611	+ int pin_num, struct regmap **regmap,
	1612	+ int reg, u8 bit)
1397	1613	{
1398	1614	struct rockchip_pinctrl *info = bank->drvdata;
1399	1615
..	..	@@ -1412,6 +1628,8 @@
1412	1628	reg += ((pin_num / RV1108_PULL_PINS_PER_REG) 4);
1413	1629	*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1414	1630	bit = RV1108_PULL_BITS_PER_PIN;
	1631	+
	1632	+ return 0;
1415	1633	}
1416	1634
1417	1635	#define RV1108_DRV_PMU_OFFSET 0x20
..	..	@@ -1420,9 +1638,9 @@
1420	1638	#define RV1108_DRV_PINS_PER_REG 8
1421	1639	#define RV1108_DRV_BANK_STRIDE 16
1422	1640
1423		-static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1424		- int pin_num, struct regmap **regmap,
1425		- int reg, u8 bit)
	1641	+static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1642	+ int pin_num, struct regmap **regmap,
	1643	+ int reg, u8 bit)
1426	1644	{
1427	1645	struct rockchip_pinctrl *info = bank->drvdata;
1428	1646
..	..	@@ -1442,6 +1660,8 @@
1442	1660	reg += ((pin_num / RV1108_DRV_PINS_PER_REG) 4);
1443	1661	*bit = pin_num % RV1108_DRV_PINS_PER_REG;
1444	1662	bit = RV1108_DRV_BITS_PER_PIN;
	1663	+
	1664	+ return 0;
1445	1665	}
1446	1666
1447	1667	#define RV1108_SCHMITT_PMU_OFFSET 0x30
..	..	@@ -1481,9 +1701,9 @@
1481	1701	#define RV1126_PULL_BANK_STRIDE 16
1482	1702	#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1483	1703
1484		-static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1485		- int pin_num, struct regmap **regmap,
1486		- int reg, u8 bit)
	1704	+static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1705	+ int pin_num, struct regmap **regmap,
	1706	+ int reg, u8 bit)
1487	1707	{
1488	1708	struct rockchip_pinctrl *info = bank->drvdata;
1489	1709
..	..	@@ -1495,7 +1715,7 @@
1495	1715	reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) 4);
1496	1716	*bit = pin_num % RV1126_PULL_PINS_PER_REG;
1497	1717	bit = RV1126_PULL_BITS_PER_PIN;
1498		- return;
	1718	+ return 0;
1499	1719	}
1500	1720	*regmap = info->regmap_pmu;
1501	1721	*reg = RV1126_PULL_PMU_OFFSET;
..	..	@@ -1508,6 +1728,8 @@
1508	1728	reg += ((pin_num / RV1126_PULL_PINS_PER_REG) 4);
1509	1729	*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1510	1730	bit = RV1126_PULL_BITS_PER_PIN;
	1731	+
	1732	+ return 0;
1511	1733	}
1512	1734
1513	1735	#define RV1126_DRV_PMU_OFFSET 0x20
..	..	@@ -1516,9 +1738,9 @@
1516	1738	#define RV1126_DRV_PINS_PER_REG 4
1517	1739	#define RV1126_DRV_BANK_STRIDE 32
1518	1740
1519		-static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1520		- int pin_num, struct regmap **regmap,
1521		- int reg, u8 bit)
	1741	+static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1742	+ int pin_num, struct regmap **regmap,
	1743	+ int reg, u8 bit)
1522	1744	{
1523	1745	struct rockchip_pinctrl *info = bank->drvdata;
1524	1746
..	..	@@ -1531,7 +1753,7 @@
1531	1753	*reg -= 0x4;
1532	1754	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1533	1755	bit = RV1126_DRV_BITS_PER_PIN;
1534		- return;
	1756	+ return 0;
1535	1757	}
1536	1758	*regmap = info->regmap_pmu;
1537	1759	*reg = RV1126_DRV_PMU_OFFSET;
..	..	@@ -1544,6 +1766,8 @@
1544	1766	reg += ((pin_num / RV1126_DRV_PINS_PER_REG) 4);
1545	1767	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1546	1768	bit = RV1126_DRV_BITS_PER_PIN;
	1769	+
	1770	+ return 0;
1547	1771	}
1548	1772
1549	1773	#define RV1126_SCHMITT_PMU_OFFSET 0x60
..	..	@@ -1583,15 +1807,35 @@
1583	1807	return 0;
1584	1808	}
1585	1809
	1810	+#define RK3308_SCHMITT_PINS_PER_REG 8
	1811	+#define RK3308_SCHMITT_BANK_STRIDE 16
	1812	+#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
	1813	+
	1814	+static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1815	+ int pin_num, struct regmap **regmap,
	1816	+ int reg, u8 bit)
	1817	+{
	1818	+ struct rockchip_pinctrl *info = bank->drvdata;
	1819	+
	1820	+ *regmap = info->regmap_base;
	1821	+ *reg = RK3308_SCHMITT_GRF_OFFSET;
	1822	+
	1823	+ reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
	1824	+ reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
	1825	+ *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
	1826	+
	1827	+ return 0;
	1828	+}
	1829	+
1586	1830	#define RK1808_PULL_PMU_OFFSET 0x10
1587	1831	#define RK1808_PULL_GRF_OFFSET 0x80
1588	1832	#define RK1808_PULL_PINS_PER_REG 8
1589	1833	#define RK1808_PULL_BITS_PER_PIN 2
1590	1834	#define RK1808_PULL_BANK_STRIDE 16
1591	1835
1592		-static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1593		- int pin_num, struct regmap **regmap,
1594		- int reg, u8 bit)
	1836	+static int rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1837	+ int pin_num, struct regmap **regmap,
	1838	+ int reg, u8 bit)
1595	1839	{
1596	1840	struct rockchip_pinctrl *info = bank->drvdata;
1597	1841
..	..	@@ -1607,6 +1851,8 @@
1607	1851	reg += ((pin_num / RK1808_PULL_PINS_PER_REG) 4);
1608	1852	*bit = (pin_num % RK1808_PULL_PINS_PER_REG);
1609	1853	bit = RK1808_PULL_BITS_PER_PIN;
	1854	+
	1855	+ return 0;
1610	1856	}
1611	1857
1612	1858	#define RK1808_DRV_PMU_OFFSET 0x20
..	..	@@ -1615,10 +1861,10 @@
1615	1861	#define RK1808_DRV_PINS_PER_REG 8
1616	1862	#define RK1808_DRV_BANK_STRIDE 16
1617	1863
1618		-static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1619		- int pin_num,
1620		- struct regmap **regmap,
1621		- int reg, u8 bit)
	1864	+static int rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1865	+ int pin_num,
	1866	+ struct regmap **regmap,
	1867	+ int reg, u8 bit)
1622	1868	{
1623	1869	struct rockchip_pinctrl *info = bank->drvdata;
1624	1870
..	..	@@ -1634,6 +1880,8 @@
1634	1880	reg += ((pin_num / RK1808_DRV_PINS_PER_REG) 4);
1635	1881	*bit = pin_num % RK1808_DRV_PINS_PER_REG;
1636	1882	bit = RK1808_DRV_BITS_PER_PIN;
	1883	+
	1884	+ return 0;
1637	1885	}
1638	1886
1639	1887	#define RK1808_SR_PMU_OFFSET 0x0030
..	..	@@ -1692,9 +1940,9 @@
1692	1940	#define RK2928_PULL_PINS_PER_REG 16
1693	1941	#define RK2928_PULL_BANK_STRIDE 8
1694	1942
1695		-static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1696		- int pin_num, struct regmap **regmap,
1697		- int reg, u8 bit)
	1943	+static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1944	+ int pin_num, struct regmap **regmap,
	1945	+ int reg, u8 bit)
1698	1946	{
1699	1947	struct rockchip_pinctrl *info = bank->drvdata;
1700	1948
..	..	@@ -1704,13 +1952,15 @@
1704	1952	reg += (pin_num / RK2928_PULL_PINS_PER_REG) 4;
1705	1953
1706	1954	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
	1955	+
	1956	+ return 0;
1707	1957	};
1708	1958
1709	1959	#define RK3128_PULL_OFFSET 0x118
1710	1960
1711		-static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1712		- int pin_num, struct regmap **regmap,
1713		- int reg, u8 bit)
	1961	+static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1962	+ int pin_num, struct regmap **regmap,
	1963	+ int reg, u8 bit)
1714	1964	{
1715	1965	struct rockchip_pinctrl *info = bank->drvdata;
1716	1966
..	..	@@ -1720,6 +1970,8 @@
1720	1970	reg += ((pin_num / RK2928_PULL_PINS_PER_REG) 4);
1721	1971
1722	1972	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
	1973	+
	1974	+ return 0;
1723	1975	}
1724	1976
1725	1977	#define RK3188_PULL_OFFSET 0x164
..	..	@@ -1728,9 +1980,9 @@
1728	1980	#define RK3188_PULL_BANK_STRIDE 16
1729	1981	#define RK3188_PULL_PMU_OFFSET 0x64
1730	1982
1731		-static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1732		- int pin_num, struct regmap **regmap,
1733		- int reg, u8 bit)
	1983	+static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1984	+ int pin_num, struct regmap **regmap,
	1985	+ int reg, u8 bit)
1734	1986	{
1735	1987	struct rockchip_pinctrl *info = bank->drvdata;
1736	1988
..	..	@@ -1760,12 +2012,14 @@
1760	2012	*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1761	2013	bit = RK3188_PULL_BITS_PER_PIN;
1762	2014	}
	2015	+
	2016	+ return 0;
1763	2017	}
1764	2018
1765	2019	#define RK3288_PULL_OFFSET 0x140
1766		-static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1767		- int pin_num, struct regmap **regmap,
1768		- int reg, u8 bit)
	2020	+static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2021	+ int pin_num, struct regmap **regmap,
	2022	+ int reg, u8 bit)
1769	2023	{
1770	2024	struct rockchip_pinctrl *info = bank->drvdata;
1771	2025
..	..	@@ -1789,6 +2043,8 @@
1789	2043	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1790	2044	bit = RK3188_PULL_BITS_PER_PIN;
1791	2045	}
	2046	+
	2047	+ return 0;
1792	2048	}
1793	2049
1794	2050	#define RK3288_DRV_PMU_OFFSET 0x70
..	..	@@ -1797,9 +2053,9 @@
1797	2053	#define RK3288_DRV_PINS_PER_REG 8
1798	2054	#define RK3288_DRV_BANK_STRIDE 16
1799	2055
1800		-static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1801		- int pin_num, struct regmap **regmap,
1802		- int reg, u8 bit)
	2056	+static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2057	+ int pin_num, struct regmap **regmap,
	2058	+ int reg, u8 bit)
1803	2059	{
1804	2060	struct rockchip_pinctrl *info = bank->drvdata;
1805	2061
..	..	@@ -1823,13 +2079,15 @@
1823	2079	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1824	2080	bit = RK3288_DRV_BITS_PER_PIN;
1825	2081	}
	2082	+
	2083	+ return 0;
1826	2084	}
1827	2085
1828	2086	#define RK3228_PULL_OFFSET 0x100
1829	2087
1830		-static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1831		- int pin_num, struct regmap **regmap,
1832		- int reg, u8 bit)
	2088	+static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2089	+ int pin_num, struct regmap **regmap,
	2090	+ int reg, u8 bit)
1833	2091	{
1834	2092	struct rockchip_pinctrl *info = bank->drvdata;
1835	2093
..	..	@@ -1840,13 +2098,15 @@
1840	2098
1841	2099	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1842	2100	bit = RK3188_PULL_BITS_PER_PIN;
	2101	+
	2102	+ return 0;
1843	2103	}
1844	2104
1845	2105	#define RK3228_DRV_GRF_OFFSET 0x200
1846	2106
1847		-static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1848		- int pin_num, struct regmap **regmap,
1849		- int reg, u8 bit)
	2107	+static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2108	+ int pin_num, struct regmap **regmap,
	2109	+ int reg, u8 bit)
1850	2110	{
1851	2111	struct rockchip_pinctrl *info = bank->drvdata;
1852	2112
..	..	@@ -1857,13 +2117,15 @@
1857	2117
1858	2118	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1859	2119	bit = RK3288_DRV_BITS_PER_PIN;
	2120	+
	2121	+ return 0;
1860	2122	}
1861	2123
1862	2124	#define RK3308_PULL_OFFSET 0xa0
1863	2125
1864		-static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1865		- int pin_num, struct regmap **regmap,
1866		- int reg, u8 bit)
	2126	+static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2127	+ int pin_num, struct regmap **regmap,
	2128	+ int reg, u8 bit)
1867	2129	{
1868	2130	struct rockchip_pinctrl *info = bank->drvdata;
1869	2131
..	..	@@ -1874,13 +2136,15 @@
1874	2136
1875	2137	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1876	2138	bit = RK3188_PULL_BITS_PER_PIN;
	2139	+
	2140	+ return 0;
1877	2141	}
1878	2142
1879	2143	#define RK3308_DRV_GRF_OFFSET 0x100
1880	2144
1881		-static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1882		- int pin_num, struct regmap **regmap,
1883		- int reg, u8 bit)
	2145	+static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2146	+ int pin_num, struct regmap **regmap,
	2147	+ int reg, u8 bit)
1884	2148	{
1885	2149	struct rockchip_pinctrl *info = bank->drvdata;
1886	2150
..	..	@@ -1891,14 +2155,39 @@
1891	2155
1892	2156	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1893	2157	bit = RK3288_DRV_BITS_PER_PIN;
	2158	+
	2159	+ return 0;
	2160	+}
	2161	+
	2162	+#define RK3308_SLEW_RATE_GRF_OFFSET 0x150
	2163	+#define RK3308_SLEW_RATE_BANK_STRIDE 16
	2164	+#define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8
	2165	+
	2166	+static int rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
	2167	+ int pin_num,
	2168	+ struct regmap **regmap,
	2169	+ int reg, u8 bit)
	2170	+{
	2171	+ struct rockchip_pinctrl *info = bank->drvdata;
	2172	+ int pins_per_reg;
	2173	+
	2174	+ *regmap = info->regmap_base;
	2175	+ *reg = RK3308_SLEW_RATE_GRF_OFFSET;
	2176	+ reg += (bank->bank_num) RK3308_SLEW_RATE_BANK_STRIDE;
	2177	+ pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG;
	2178	+
	2179	+ reg += ((pin_num / pins_per_reg) 4);
	2180	+ *bit = pin_num % pins_per_reg;
	2181	+
	2182	+ return 0;
1894	2183	}
1895	2184
1896	2185	#define RK3368_PULL_GRF_OFFSET 0x100
1897	2186	#define RK3368_PULL_PMU_OFFSET 0x10
1898	2187
1899		-static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1900		- int pin_num, struct regmap **regmap,
1901		- int reg, u8 bit)
	2188	+static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2189	+ int pin_num, struct regmap **regmap,
	2190	+ int reg, u8 bit)
1902	2191	{
1903	2192	struct rockchip_pinctrl *info = bank->drvdata;
1904	2193
..	..	@@ -1922,14 +2211,16 @@
1922	2211	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1923	2212	bit = RK3188_PULL_BITS_PER_PIN;
1924	2213	}
	2214	+
	2215	+ return 0;
1925	2216	}
1926	2217
1927	2218	#define RK3368_DRV_PMU_OFFSET 0x20
1928	2219	#define RK3368_DRV_GRF_OFFSET 0x200
1929	2220
1930		-static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1931		- int pin_num, struct regmap **regmap,
1932		- int reg, u8 bit)
	2221	+static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2222	+ int pin_num, struct regmap **regmap,
	2223	+ int reg, u8 bit)
1933	2224	{
1934	2225	struct rockchip_pinctrl *info = bank->drvdata;
1935	2226
..	..	@@ -1953,15 +2244,17 @@
1953	2244	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1954	2245	bit = RK3288_DRV_BITS_PER_PIN;
1955	2246	}
	2247	+
	2248	+ return 0;
1956	2249	}
1957	2250
1958	2251	#define RK3399_PULL_GRF_OFFSET 0xe040
1959	2252	#define RK3399_PULL_PMU_OFFSET 0x40
1960	2253	#define RK3399_DRV_3BITS_PER_PIN 3
1961	2254
1962		-static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1963		- int pin_num, struct regmap **regmap,
1964		- int reg, u8 bit)
	2255	+static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2256	+ int pin_num, struct regmap **regmap,
	2257	+ int reg, u8 bit)
1965	2258	{
1966	2259	struct rockchip_pinctrl *info = bank->drvdata;
1967	2260
..	..	@@ -1987,11 +2280,13 @@
1987	2280	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1988	2281	bit = RK3188_PULL_BITS_PER_PIN;
1989	2282	}
	2283	+
	2284	+ return 0;
1990	2285	}
1991	2286
1992		-static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1993		- int pin_num, struct regmap **regmap,
1994		- int reg, u8 bit)
	2287	+static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2288	+ int pin_num, struct regmap **regmap,
	2289	+ int reg, u8 bit)
1995	2290	{
1996	2291	struct rockchip_pinctrl *info = bank->drvdata;
1997	2292	int drv_num = (pin_num / 8);
..	..	@@ -2008,6 +2303,297 @@
2008	2303	bit = (pin_num % 8) 3;
2009	2304	else
2010	2305	bit = (pin_num % 8) 2;
	2306	+
	2307	+ return 0;
	2308	+}
	2309	+
	2310	+#define RK3528_DRV_BITS_PER_PIN 8
	2311	+#define RK3528_DRV_PINS_PER_REG 2
	2312	+#define RK3528_DRV_GPIO0_OFFSET 0x100
	2313	+#define RK3528_DRV_GPIO1_OFFSET 0x20120
	2314	+#define RK3528_DRV_GPIO2_OFFSET 0x30160
	2315	+#define RK3528_DRV_GPIO3_OFFSET 0x20190
	2316	+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
	2317	+
	2318	+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2319	+ int pin_num, struct regmap **regmap,
	2320	+ int reg, u8 bit)
	2321	+{
	2322	+ struct rockchip_pinctrl *info = bank->drvdata;
	2323	+
	2324	+ *regmap = info->regmap_base;
	2325	+ switch (bank->bank_num) {
	2326	+ case 0:
	2327	+ *reg = RK3528_DRV_GPIO0_OFFSET;
	2328	+ break;
	2329	+
	2330	+ case 1:
	2331	+ *reg = RK3528_DRV_GPIO1_OFFSET;
	2332	+ break;
	2333	+
	2334	+ case 2:
	2335	+ *reg = RK3528_DRV_GPIO2_OFFSET;
	2336	+ break;
	2337	+
	2338	+ case 3:
	2339	+ *reg = RK3528_DRV_GPIO3_OFFSET;
	2340	+ break;
	2341	+
	2342	+ case 4:
	2343	+ *reg = RK3528_DRV_GPIO4_OFFSET;
	2344	+ break;
	2345	+
	2346	+ default:
	2347	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2348	+ break;
	2349	+ }
	2350	+
	2351	+ reg += ((pin_num / RK3528_DRV_PINS_PER_REG) 4);
	2352	+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
	2353	+ bit = RK3528_DRV_BITS_PER_PIN;
	2354	+
	2355	+ return 0;
	2356	+}
	2357	+
	2358	+#define RK3528_PULL_BITS_PER_PIN 2
	2359	+#define RK3528_PULL_PINS_PER_REG 8
	2360	+#define RK3528_PULL_GPIO0_OFFSET 0x200
	2361	+#define RK3528_PULL_GPIO1_OFFSET 0x20210
	2362	+#define RK3528_PULL_GPIO2_OFFSET 0x30220
	2363	+#define RK3528_PULL_GPIO3_OFFSET 0x20230
	2364	+#define RK3528_PULL_GPIO4_OFFSET 0x10240
	2365	+
	2366	+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2367	+ int pin_num, struct regmap **regmap,
	2368	+ int reg, u8 bit)
	2369	+{
	2370	+ struct rockchip_pinctrl *info = bank->drvdata;
	2371	+
	2372	+ *regmap = info->regmap_base;
	2373	+ switch (bank->bank_num) {
	2374	+ case 0:
	2375	+ *reg = RK3528_PULL_GPIO0_OFFSET;
	2376	+ break;
	2377	+
	2378	+ case 1:
	2379	+ *reg = RK3528_PULL_GPIO1_OFFSET;
	2380	+ break;
	2381	+
	2382	+ case 2:
	2383	+ *reg = RK3528_PULL_GPIO2_OFFSET;
	2384	+ break;
	2385	+
	2386	+ case 3:
	2387	+ *reg = RK3528_PULL_GPIO3_OFFSET;
	2388	+ break;
	2389	+
	2390	+ case 4:
	2391	+ *reg = RK3528_PULL_GPIO4_OFFSET;
	2392	+ break;
	2393	+
	2394	+ default:
	2395	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2396	+ break;
	2397	+ }
	2398	+
	2399	+ reg += ((pin_num / RK3528_PULL_PINS_PER_REG) 4);
	2400	+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
	2401	+ bit = RK3528_PULL_BITS_PER_PIN;
	2402	+
	2403	+ return 0;
	2404	+}
	2405	+
	2406	+#define RK3528_SMT_BITS_PER_PIN 1
	2407	+#define RK3528_SMT_PINS_PER_REG 8
	2408	+#define RK3528_SMT_GPIO0_OFFSET 0x400
	2409	+#define RK3528_SMT_GPIO1_OFFSET 0x20410
	2410	+#define RK3528_SMT_GPIO2_OFFSET 0x30420
	2411	+#define RK3528_SMT_GPIO3_OFFSET 0x20430
	2412	+#define RK3528_SMT_GPIO4_OFFSET 0x10440
	2413	+
	2414	+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2415	+ int pin_num,
	2416	+ struct regmap **regmap,
	2417	+ int reg, u8 bit)
	2418	+{
	2419	+ struct rockchip_pinctrl *info = bank->drvdata;
	2420	+
	2421	+ *regmap = info->regmap_base;
	2422	+ switch (bank->bank_num) {
	2423	+ case 0:
	2424	+ *reg = RK3528_SMT_GPIO0_OFFSET;
	2425	+ break;
	2426	+
	2427	+ case 1:
	2428	+ *reg = RK3528_SMT_GPIO1_OFFSET;
	2429	+ break;
	2430	+
	2431	+ case 2:
	2432	+ *reg = RK3528_SMT_GPIO2_OFFSET;
	2433	+ break;
	2434	+
	2435	+ case 3:
	2436	+ *reg = RK3528_SMT_GPIO3_OFFSET;
	2437	+ break;
	2438	+
	2439	+ case 4:
	2440	+ *reg = RK3528_SMT_GPIO4_OFFSET;
	2441	+ break;
	2442	+
	2443	+ default:
	2444	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2445	+ break;
	2446	+ }
	2447	+
	2448	+ reg += ((pin_num / RK3528_SMT_PINS_PER_REG) 4);
	2449	+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
	2450	+ bit = RK3528_SMT_BITS_PER_PIN;
	2451	+ return 0;
	2452	+}
	2453	+
	2454	+#define RK3562_DRV_BITS_PER_PIN 8
	2455	+#define RK3562_DRV_PINS_PER_REG 2
	2456	+#define RK3562_DRV_GPIO0_OFFSET 0x20070
	2457	+#define RK3562_DRV_GPIO1_OFFSET 0x200
	2458	+#define RK3562_DRV_GPIO2_OFFSET 0x240
	2459	+#define RK3562_DRV_GPIO3_OFFSET 0x10280
	2460	+#define RK3562_DRV_GPIO4_OFFSET 0x102C0
	2461	+
	2462	+static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2463	+ int pin_num, struct regmap **regmap,
	2464	+ int reg, u8 bit)
	2465	+{
	2466	+ struct rockchip_pinctrl *info = bank->drvdata;
	2467	+
	2468	+ *regmap = info->regmap_base;
	2469	+ switch (bank->bank_num) {
	2470	+ case 0:
	2471	+ *reg = RK3562_DRV_GPIO0_OFFSET;
	2472	+ break;
	2473	+
	2474	+ case 1:
	2475	+ *reg = RK3562_DRV_GPIO1_OFFSET;
	2476	+ break;
	2477	+
	2478	+ case 2:
	2479	+ *reg = RK3562_DRV_GPIO2_OFFSET;
	2480	+ break;
	2481	+
	2482	+ case 3:
	2483	+ *reg = RK3562_DRV_GPIO3_OFFSET;
	2484	+ break;
	2485	+
	2486	+ case 4:
	2487	+ *reg = RK3562_DRV_GPIO4_OFFSET;
	2488	+ break;
	2489	+
	2490	+ default:
	2491	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2492	+ break;
	2493	+ }
	2494	+
	2495	+ reg += ((pin_num / RK3562_DRV_PINS_PER_REG) 4);
	2496	+ *bit = pin_num % RK3562_DRV_PINS_PER_REG;
	2497	+ bit = RK3562_DRV_BITS_PER_PIN;
	2498	+
	2499	+ return 0;
	2500	+}
	2501	+
	2502	+#define RK3562_PULL_BITS_PER_PIN 2
	2503	+#define RK3562_PULL_PINS_PER_REG 8
	2504	+#define RK3562_PULL_GPIO0_OFFSET 0x20020
	2505	+#define RK3562_PULL_GPIO1_OFFSET 0x80
	2506	+#define RK3562_PULL_GPIO2_OFFSET 0x90
	2507	+#define RK3562_PULL_GPIO3_OFFSET 0x100A0
	2508	+#define RK3562_PULL_GPIO4_OFFSET 0x100B0
	2509	+
	2510	+static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2511	+ int pin_num, struct regmap **regmap,
	2512	+ int reg, u8 bit)
	2513	+{
	2514	+ struct rockchip_pinctrl *info = bank->drvdata;
	2515	+
	2516	+ *regmap = info->regmap_base;
	2517	+ switch (bank->bank_num) {
	2518	+ case 0:
	2519	+ *reg = RK3562_PULL_GPIO0_OFFSET;
	2520	+ break;
	2521	+
	2522	+ case 1:
	2523	+ *reg = RK3562_PULL_GPIO1_OFFSET;
	2524	+ break;
	2525	+
	2526	+ case 2:
	2527	+ *reg = RK3562_PULL_GPIO2_OFFSET;
	2528	+ break;
	2529	+
	2530	+ case 3:
	2531	+ *reg = RK3562_PULL_GPIO3_OFFSET;
	2532	+ break;
	2533	+
	2534	+ case 4:
	2535	+ *reg = RK3562_PULL_GPIO4_OFFSET;
	2536	+ break;
	2537	+
	2538	+ default:
	2539	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2540	+ break;
	2541	+ }
	2542	+
	2543	+ reg += ((pin_num / RK3562_PULL_PINS_PER_REG) 4);
	2544	+ *bit = pin_num % RK3562_PULL_PINS_PER_REG;
	2545	+ bit = RK3562_PULL_BITS_PER_PIN;
	2546	+
	2547	+ return 0;
	2548	+}
	2549	+
	2550	+#define RK3562_SMT_BITS_PER_PIN 2
	2551	+#define RK3562_SMT_PINS_PER_REG 8
	2552	+#define RK3562_SMT_GPIO0_OFFSET 0x20030
	2553	+#define RK3562_SMT_GPIO1_OFFSET 0xC0
	2554	+#define RK3562_SMT_GPIO2_OFFSET 0xD0
	2555	+#define RK3562_SMT_GPIO3_OFFSET 0x100E0
	2556	+#define RK3562_SMT_GPIO4_OFFSET 0x100F0
	2557	+
	2558	+static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2559	+ int pin_num,
	2560	+ struct regmap **regmap,
	2561	+ int reg, u8 bit)
	2562	+{
	2563	+ struct rockchip_pinctrl *info = bank->drvdata;
	2564	+
	2565	+ *regmap = info->regmap_base;
	2566	+ switch (bank->bank_num) {
	2567	+ case 0:
	2568	+ *reg = RK3562_SMT_GPIO0_OFFSET;
	2569	+ break;
	2570	+
	2571	+ case 1:
	2572	+ *reg = RK3562_SMT_GPIO1_OFFSET;
	2573	+ break;
	2574	+
	2575	+ case 2:
	2576	+ *reg = RK3562_SMT_GPIO2_OFFSET;
	2577	+ break;
	2578	+
	2579	+ case 3:
	2580	+ *reg = RK3562_SMT_GPIO3_OFFSET;
	2581	+ break;
	2582	+
	2583	+ case 4:
	2584	+ *reg = RK3562_SMT_GPIO4_OFFSET;
	2585	+ break;
	2586	+
	2587	+ default:
	2588	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2589	+ break;
	2590	+ }
	2591	+
	2592	+ reg += ((pin_num / RK3562_SMT_PINS_PER_REG) 4);
	2593	+ *bit = pin_num % RK3562_SMT_PINS_PER_REG;
	2594	+ bit = RK3562_SMT_BITS_PER_PIN;
	2595	+
	2596	+ return 0;
2011	2597	}
2012	2598
2013	2599	#define RK3568_SR_PMU_OFFSET 0x60
..	..	@@ -2044,9 +2630,9 @@
2044	2630	#define RK3568_PULL_PINS_PER_REG 8
2045	2631	#define RK3568_PULL_BANK_STRIDE 0x10
2046	2632
2047		-static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2048		- int pin_num, struct regmap **regmap,
2049		- int reg, u8 bit)
	2633	+static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2634	+ int pin_num, struct regmap **regmap,
	2635	+ int reg, u8 bit)
2050	2636	{
2051	2637	struct rockchip_pinctrl *info = bank->drvdata;
2052	2638
..	..	@@ -2067,6 +2653,8 @@
2067	2653	*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2068	2654	bit = RK3568_PULL_BITS_PER_PIN;
2069	2655	}
	2656	+
	2657	+ return 0;
2070	2658	}
2071	2659
2072	2660	#define RK3568_DRV_PMU_OFFSET 0x70
..	..	@@ -2075,9 +2663,9 @@
2075	2663	#define RK3568_DRV_PINS_PER_REG 2
2076	2664	#define RK3568_DRV_BANK_STRIDE 0x40
2077	2665
2078		-static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2079		- int pin_num, struct regmap **regmap,
2080		- int reg, u8 bit)
	2666	+static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2667	+ int pin_num, struct regmap **regmap,
	2668	+ int reg, u8 bit)
2081	2669	{
2082	2670	struct rockchip_pinctrl *info = bank->drvdata;
2083	2671
..	..	@@ -2104,6 +2692,197 @@
2104	2692	((bank->bank_num == 2 \|\| bank->bank_num == 3 \|\| bank->bank_num == 4) &&
2105	2693	(pin_num == 7 \|\| pin_num == 15 \|\| pin_num == 23 \|\| pin_num == 31)))
2106	2694	*bit -= RK3568_DRV_BITS_PER_PIN;
	2695	+
	2696	+ return 0;
	2697	+}
	2698	+
	2699	+#define RK3588_PMU1_IOC_REG (0x0000)
	2700	+#define RK3588_PMU2_IOC_REG (0x4000)
	2701	+#define RK3588_BUS_IOC_REG (0x8000)
	2702	+#define RK3588_VCCIO1_4_IOC_REG (0x9000)
	2703	+#define RK3588_VCCIO3_5_IOC_REG (0xA000)
	2704	+#define RK3588_VCCIO2_IOC_REG (0xB000)
	2705	+#define RK3588_VCCIO6_IOC_REG (0xC000)
	2706	+#define RK3588_EMMC_IOC_REG (0xD000)
	2707	+
	2708	+static const u32 rk3588_ds_regs[][2] = {
	2709	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
	2710	+ {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
	2711	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
	2712	+ {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
	2713	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
	2714	+ {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
	2715	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
	2716	+ {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
	2717	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
	2718	+ {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
	2719	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
	2720	+ {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
	2721	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
	2722	+ {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
	2723	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
	2724	+ {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
	2725	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
	2726	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
	2727	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
	2728	+ {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
	2729	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
	2730	+ {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
	2731	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
	2732	+ {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
	2733	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
	2734	+ {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
	2735	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
	2736	+ {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
	2737	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
	2738	+ {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
	2739	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
	2740	+ {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
	2741	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
	2742	+ {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
	2743	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
	2744	+ {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
	2745	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
	2746	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
	2747	+ {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
	2748	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
	2749	+};
	2750	+
	2751	+static const u32 rk3588_p_regs[][2] = {
	2752	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
	2753	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
	2754	+ {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
	2755	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
	2756	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
	2757	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
	2758	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
	2759	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
	2760	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
	2761	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
	2762	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120},
	2763	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
	2764	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
	2765	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
	2766	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
	2767	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
	2768	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
	2769	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
	2770	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
	2771	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
	2772	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
	2773	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
	2774	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
	2775	+};
	2776	+
	2777	+static const u32 rk3588_smt_regs[][2] = {
	2778	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
	2779	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
	2780	+ {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
	2781	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
	2782	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
	2783	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
	2784	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
	2785	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
	2786	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
	2787	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
	2788	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220},
	2789	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
	2790	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
	2791	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
	2792	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
	2793	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
	2794	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
	2795	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
	2796	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
	2797	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
	2798	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
	2799	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
	2800	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
	2801	+};
	2802	+
	2803	+#define RK3588_PULL_BITS_PER_PIN 2
	2804	+#define RK3588_PULL_PINS_PER_REG 8
	2805	+
	2806	+static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2807	+ int pin_num, struct regmap **regmap,
	2808	+ int reg, u8 bit)
	2809	+{
	2810	+ struct rockchip_pinctrl *info = bank->drvdata;
	2811	+ u8 bank_num = bank->bank_num;
	2812	+ u32 pin = bank_num * 32 + pin_num;
	2813	+ int i;
	2814	+
	2815	+ for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
	2816	+ if (pin >= rk3588_p_regs[i][0]) {
	2817	+ *reg = rk3588_p_regs[i][1];
	2818	+ break;
	2819	+ }
	2820	+ BUG_ON(i == 0);
	2821	+ }
	2822	+
	2823	+ *regmap = info->regmap_base;
	2824	+ reg += ((pin - rk3588_p_regs[i][0]) / RK3588_PULL_PINS_PER_REG) 4;
	2825	+ *bit = pin_num % RK3588_PULL_PINS_PER_REG;
	2826	+ bit = RK3588_PULL_BITS_PER_PIN;
	2827	+
	2828	+ return 0;
	2829	+}
	2830	+
	2831	+#define RK3588_DRV_BITS_PER_PIN 4
	2832	+#define RK3588_DRV_PINS_PER_REG 4
	2833	+
	2834	+static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2835	+ int pin_num, struct regmap **regmap,
	2836	+ int reg, u8 bit)
	2837	+{
	2838	+ struct rockchip_pinctrl *info = bank->drvdata;
	2839	+ u8 bank_num = bank->bank_num;
	2840	+ u32 pin = bank_num * 32 + pin_num;
	2841	+ int i;
	2842	+
	2843	+ for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
	2844	+ if (pin >= rk3588_ds_regs[i][0]) {
	2845	+ *reg = rk3588_ds_regs[i][1];
	2846	+ break;
	2847	+ }
	2848	+ BUG_ON(i == 0);
	2849	+ }
	2850	+
	2851	+ *regmap = info->regmap_base;
	2852	+ reg += ((pin - rk3588_ds_regs[i][0]) / RK3588_DRV_PINS_PER_REG) 4;
	2853	+ *bit = pin_num % RK3588_DRV_PINS_PER_REG;
	2854	+ bit = RK3588_DRV_BITS_PER_PIN;
	2855	+
	2856	+ return 0;
	2857	+}
	2858	+
	2859	+#define RK3588_SMT_BITS_PER_PIN 1
	2860	+#define RK3588_SMT_PINS_PER_REG 8
	2861	+
	2862	+static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2863	+ int pin_num,
	2864	+ struct regmap **regmap,
	2865	+ int reg, u8 bit)
	2866	+{
	2867	+ struct rockchip_pinctrl *info = bank->drvdata;
	2868	+ u8 bank_num = bank->bank_num;
	2869	+ u32 pin = bank_num * 32 + pin_num;
	2870	+ int i;
	2871	+
	2872	+ for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
	2873	+ if (pin >= rk3588_smt_regs[i][0]) {
	2874	+ *reg = rk3588_smt_regs[i][1];
	2875	+ break;
	2876	+ }
	2877	+ BUG_ON(i == 0);
	2878	+ }
	2879	+
	2880	+ *regmap = info->regmap_base;
	2881	+ reg += ((pin - rk3588_smt_regs[i][0]) / RK3588_SMT_PINS_PER_REG) 4;
	2882	+ *bit = pin_num % RK3588_SMT_PINS_PER_REG;
	2883	+ bit = RK3588_SMT_BITS_PER_PIN;
	2884	+
	2885	+ return 0;
2107	2886	}
2108	2887
2109	2888	static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
..	..	@@ -2120,13 +2899,16 @@
2120	2899	{
2121	2900	struct rockchip_pinctrl *info = bank->drvdata;
2122	2901	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	2902	+ struct device *dev = info->dev;
2123	2903	struct regmap *regmap;
2124	2904	int reg, ret;
2125	2905	u32 data, temp, rmask_bits;
2126	2906	u8 bit;
2127	2907	int drv_type = bank->drv[pin_num / 8].drv_type;
2128	2908
2129		- ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2909	+ ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2910	+ if (ret)
	2911	+ return ret;
2130	2912
2131	2913	switch (drv_type) {
2132	2914	case DRV_TYPE_IO_1V8_3V0_AUTO:
..	..	@@ -2165,7 +2947,7 @@
2165	2947	bit -= 16;
2166	2948	break;
2167	2949	default:
2168		- dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
	2950	+ dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2169	2951	bit, drv_type);
2170	2952	return -EINVAL;
2171	2953	}
..	..	@@ -2178,8 +2960,7 @@
2178	2960	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2179	2961	break;
2180	2962	default:
2181		- dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2182		- drv_type);
	2963	+ dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2183	2964	return -EINVAL;
2184	2965	}
2185	2966
..	..	@@ -2212,21 +2993,28 @@
2212	2993	{
2213	2994	struct rockchip_pinctrl *info = bank->drvdata;
2214	2995	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	2996	+ struct device *dev = info->dev;
2215	2997	struct regmap *regmap;
2216	2998	int reg, ret, i, err;
2217	2999	u32 data, rmask, rmask_bits, temp;
2218	3000	u8 bit;
2219	3001	int drv_type = bank->drv[pin_num / 8].drv_type;
2220	3002
2221		- dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
	3003	+ dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2222	3004	bank->bank_num, pin_num, strength);
2223	3005
2224		- ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2225		- if (ctrl->type == RV1126) {
	3006	+ ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3007	+ if (ret)
	3008	+ return ret;
	3009	+
	3010	+ if (ctrl->type == RV1126 \|\| ctrl->type == RK3588) {
2226	3011	rmask_bits = RV1126_DRV_BITS_PER_PIN;
2227	3012	ret = strength;
2228	3013	goto config;
2229		- } else if (ctrl->type == RK3568) {
	3014	+ } else if (ctrl->type == RV1106 \|\|
	3015	+ ctrl->type == RK3528 \|\|
	3016	+ ctrl->type == RK3562 \|\|
	3017	+ ctrl->type == RK3568) {
2230	3018	rmask_bits = RK3568_DRV_BITS_PER_PIN;
2231	3019	ret = (1 << (strength + 1)) - 1;
2232	3020	goto config;
..	..	@@ -2244,8 +3032,7 @@
2244	3032	}
2245	3033
2246	3034	if (ret < 0) {
2247		- dev_err(info->dev, "unsupported driver strength %d\n",
2248		- strength);
	3035	+ dev_err(dev, "unsupported driver strength %d\n", strength);
2249	3036	return ret;
2250	3037	}
2251	3038
..	..	@@ -2284,7 +3071,7 @@
2284	3071	bit -= 16;
2285	3072	break;
2286	3073	default:
2287		- dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
	3074	+ dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2288	3075	bit, drv_type);
2289	3076	return -EINVAL;
2290	3077	}
..	..	@@ -2296,8 +3083,7 @@
2296	3083	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2297	3084	break;
2298	3085	default:
2299		- dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2300		- drv_type);
	3086	+ dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2301	3087	return -EINVAL;
2302	3088	}
2303	3089
..	..	@@ -2366,6 +3152,7 @@
2366	3152	{
2367	3153	struct rockchip_pinctrl *info = bank->drvdata;
2368	3154	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3155	+ struct device *dev = info->dev;
2369	3156	struct regmap *regmap;
2370	3157	int reg, ret, pull_type;
2371	3158	u8 bit;
..	..	@@ -2375,7 +3162,9 @@
2375	3162	if (ctrl->type == RK3066B)
2376	3163	return PIN_CONFIG_BIAS_DISABLE;
2377	3164
2378		- ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3165	+ ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3166	+ if (ret)
	3167	+ return ret;
2379	3168
2380	3169	ret = regmap_read(regmap, reg, &data);
2381	3170	if (ret)
..	..	@@ -2388,6 +3177,7 @@
2388	3177	? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2389	3178	: PIN_CONFIG_BIAS_DISABLE;
2390	3179	case PX30:
	3180	+ case RV1106:
2391	3181	case RV1108:
2392	3182	case RV1126:
2393	3183	case RK1808:
..	..	@@ -2396,14 +3186,17 @@
2396	3186	case RK3308:
2397	3187	case RK3368:
2398	3188	case RK3399:
	3189	+ case RK3528:
	3190	+ case RK3562:
2399	3191	case RK3568:
	3192	+ case RK3588:
2400	3193	pull_type = bank->pull_type[pin_num / 8];
2401	3194	data >>= bit;
2402	3195	data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2403	3196
2404	3197	return rockchip_pull_list[pull_type][data];
2405	3198	default:
2406		- dev_err(info->dev, "unsupported pinctrl type\n");
	3199	+ dev_err(dev, "unsupported pinctrl type\n");
2407	3200	return -EINVAL;
2408	3201	};
2409	3202	}
..	..	@@ -2413,19 +3206,21 @@
2413	3206	{
2414	3207	struct rockchip_pinctrl *info = bank->drvdata;
2415	3208	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3209	+ struct device *dev = info->dev;
2416	3210	struct regmap *regmap;
2417	3211	int reg, ret, i, pull_type;
2418	3212	u8 bit;
2419	3213	u32 data, rmask;
2420	3214
2421		- dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2422		- bank->bank_num, pin_num, pull);
	3215	+ dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2423	3216
2424	3217	/* rk3066b does support any pulls */
2425	3218	if (ctrl->type == RK3066B)
2426	3219	return pull ? -EINVAL : 0;
2427	3220
2428		- ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3221	+ ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3222	+ if (ret)
	3223	+ return ret;
2429	3224
2430	3225	switch (ctrl->type) {
2431	3226	case RK2928:
..	..	@@ -2436,6 +3231,7 @@
2436	3231	ret = regmap_write(regmap, reg, data);
2437	3232	break;
2438	3233	case PX30:
	3234	+ case RV1106:
2439	3235	case RV1108:
2440	3236	case RV1126:
2441	3237	case RK1808:
..	..	@@ -2444,7 +3240,10 @@
2444	3240	case RK3308:
2445	3241	case RK3368:
2446	3242	case RK3399:
	3243	+ case RK3528:
	3244	+ case RK3562:
2447	3245	case RK3568:
	3246	+ case RK3588:
2448	3247	pull_type = bank->pull_type[pin_num / 8];
2449	3248	ret = -EINVAL;
2450	3249	for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
..	..	@@ -2455,7 +3254,7 @@
2455	3254	}
2456	3255	}
2457	3256	/*
2458		- * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
	3257	+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2459	3258	* where that pull up value becomes 3.
2460	3259	*/
2461	3260	if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
..	..	@@ -2464,8 +3263,7 @@
2464	3263	}
2465	3264
2466	3265	if (ret < 0) {
2467		- dev_err(info->dev, "unsupported pull setting %d\n",
2468		- pull);
	3266	+ dev_err(dev, "unsupported pull setting %d\n", pull);
2469	3267	return ret;
2470	3268	}
2471	3269
..	..	@@ -2477,32 +3275,11 @@
2477	3275	ret = regmap_update_bits(regmap, reg, rmask, data);
2478	3276	break;
2479	3277	default:
2480		- dev_err(info->dev, "unsupported pinctrl type\n");
	3278	+ dev_err(dev, "unsupported pinctrl type\n");
2481	3279	return -EINVAL;
2482	3280	}
2483	3281
2484	3282	return ret;
2485		-}
2486		-
2487		-#define RK3308_SCHMITT_PINS_PER_REG 8
2488		-#define RK3308_SCHMITT_BANK_STRIDE 16
2489		-#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
2490		-
2491		-static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2492		- int pin_num,
2493		- struct regmap **regmap,
2494		- int reg, u8 bit)
2495		-{
2496		- struct rockchip_pinctrl *info = bank->drvdata;
2497		-
2498		- *regmap = info->regmap_base;
2499		- *reg = RK3308_SCHMITT_GRF_OFFSET;
2500		-
2501		- reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
2502		- reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
2503		- *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
2504		-
2505		- return 0;
2506	3283	}
2507	3284
2508	3285	#define RK3328_SCHMITT_BITS_PER_PIN 1
..	..	@@ -2575,6 +3352,7 @@
2575	3352
2576	3353	data >>= bit;
2577	3354	switch (ctrl->type) {
	3355	+ case RK3562:
2578	3356	case RK3568:
2579	3357	return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2580	3358	default:
..	..	@@ -2589,12 +3367,13 @@
2589	3367	{
2590	3368	struct rockchip_pinctrl *info = bank->drvdata;
2591	3369	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3370	+ struct device *dev = info->dev;
2592	3371	struct regmap *regmap;
2593	3372	int reg, ret;
2594	3373	u8 bit;
2595	3374	u32 data, rmask;
2596	3375
2597		- dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
	3376	+ dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2598	3377	bank->bank_num, pin_num, enable);
2599	3378
2600	3379	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
..	..	@@ -2603,6 +3382,7 @@
2603	3382
2604	3383	/* enable the write to the equivalent lower bits */
2605	3384	switch (ctrl->type) {
	3385	+ case RK3562:
2606	3386	case RK3568:
2607	3387	data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2608	3388	rmask = data \| (data >> 16);
..	..	@@ -2737,10 +3517,11 @@
2737	3517	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2738	3518	const unsigned int *pins = info->groups[group].pins;
2739	3519	const struct rockchip_pin_config *data = info->groups[group].data;
	3520	+ struct device *dev = info->dev;
2740	3521	struct rockchip_pin_bank *bank;
2741	3522	int cnt, ret = 0;
2742	3523
2743		- dev_dbg(info->dev, "enable function %s group %s\n",
	3524	+ dev_dbg(dev, "enable function %s group %s\n",
2744	3525	info->functions[selector].name, info->groups[group].name);
2745	3526
2746	3527	/*
..	..	@@ -2788,6 +3569,7 @@
2788	3569	case RK3066B:
2789	3570	return pull ? false : true;
2790	3571	case PX30:
	3572	+ case RV1106:
2791	3573	case RV1108:
2792	3574	case RV1126:
2793	3575	case RK1808:
..	..	@@ -2796,11 +3578,32 @@
2796	3578	case RK3308:
2797	3579	case RK3368:
2798	3580	case RK3399:
	3581	+ case RK3528:
	3582	+ case RK3562:
2799	3583	case RK3568:
	3584	+ case RK3588:
2800	3585	return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2801	3586	}
2802	3587
2803	3588	return false;
	3589	+}
	3590	+
	3591	+static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
	3592	+ unsigned int pin, u32 param, u32 arg)
	3593	+{
	3594	+ struct rockchip_pin_deferred *cfg;
	3595	+
	3596	+ cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
	3597	+ if (!cfg)
	3598	+ return -ENOMEM;
	3599	+
	3600	+ cfg->pin = pin;
	3601	+ cfg->param = param;
	3602	+ cfg->arg = arg;
	3603	+
	3604	+ list_add_tail(&cfg->head, &bank->deferred_pins);
	3605	+
	3606	+ return 0;
2804	3607	}
2805	3608
2806	3609	/* set the pin config settings for a specified pin */
..	..	@@ -2818,6 +3621,25 @@
2818	3621	for (i = 0; i < num_configs; i++) {
2819	3622	param = pinconf_to_config_param(configs[i]);
2820	3623	arg = pinconf_to_config_argument(configs[i]);
	3624	+
	3625	+ if (param == PIN_CONFIG_OUTPUT \|\| param == PIN_CONFIG_INPUT_ENABLE) {
	3626	+ /*
	3627	+ * Check for gpio driver not being probed yet.
	3628	+ * The lock makes sure that either gpio-probe has completed
	3629	+ * or the gpio driver hasn't probed yet.
	3630	+ */
	3631	+ mutex_lock(&bank->deferred_lock);
	3632	+ if (!gpio \|\| !gpio->direction_output) {
	3633	+ rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
	3634	+ arg);
	3635	+ mutex_unlock(&bank->deferred_lock);
	3636	+ if (rc)
	3637	+ return rc;
	3638	+
	3639	+ break;
	3640	+ }
	3641	+ mutex_unlock(&bank->deferred_lock);
	3642	+ }
2821	3643
2822	3644	switch (param) {
2823	3645	case PIN_CONFIG_BIAS_DISABLE:
..	..	@@ -2844,10 +3666,8 @@
2844	3666	case PIN_CONFIG_OUTPUT:
2845	3667	rc = rockchip_set_mux(bank, pin - bank->pin_base,
2846	3668	RK_FUNC_GPIO);
2847		- if (rc != RK_FUNC_GPIO) {
2848		- dev_err(info->dev, "pin-%d fail to mux to gpio, %d\n", pin, rc);
	3669	+ if (rc != RK_FUNC_GPIO)
2849	3670	return -EINVAL;
2850		- }
2851	3671
2852	3672	rc = gpio->direction_output(gpio, pin - bank->pin_base,
2853	3673	arg);
..	..	@@ -2932,13 +3752,13 @@
2932	3752	break;
2933	3753	case PIN_CONFIG_OUTPUT:
2934	3754	rc = rockchip_get_mux(bank, pin - bank->pin_base);
2935		- if (rc != 0)
	3755	+ if (rc != RK_FUNC_GPIO)
2936	3756	return -EINVAL;
2937	3757
2938		- /* 0 for output, 1 for input */
2939		- rc = gpio->get_direction(gpio, pin - bank->pin_base);
2940		- if (rc)
2941		- return -EINVAL;
	3758	+ if (!gpio \|\| !gpio->get) {
	3759	+ arg = 0;
	3760	+ break;
	3761	+ }
2942	3762
2943	3763	rc = gpio->get(gpio, pin - bank->pin_base);
2944	3764	if (rc < 0)
..	..	@@ -2998,24 +3818,13 @@
2998	3818	{},
2999	3819	};
3000	3820
3001		-static bool is_function_node(const struct device_node *np)
3002		-{
3003		- if (of_match_node(rockchip_bank_match, np))
3004		- return false;
3005		-
3006		- if (!strncmp(np->name, "pcfg", 4))
3007		- return false;
3008		-
3009		- return true;
3010		-}
3011		-
3012	3821	static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
3013	3822	struct device_node *np)
3014	3823	{
3015	3824	struct device_node *child;
3016	3825
3017	3826	for_each_child_of_node(np, child) {
3018		- if (!is_function_node(child))
	3827	+ if (of_match_node(rockchip_bank_match, child))
3019	3828	continue;
3020	3829
3021	3830	info->nfunctions++;
..	..	@@ -3028,6 +3837,7 @@
3028	3837	struct rockchip_pinctrl *info,
3029	3838	u32 index)
3030	3839	{
	3840	+ struct device *dev = info->dev;
3031	3841	struct rockchip_pin_bank *bank;
3032	3842	int size;
3033	3843	const __be32 *list;
..	..	@@ -3035,7 +3845,7 @@
3035	3845	int i, j;
3036	3846	int ret;
3037	3847
3038		- dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
	3848	+ dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3039	3849
3040	3850	/* Initialise group */
3041	3851	grp->name = np->name;
..	..	@@ -3047,19 +3857,13 @@
3047	3857	list = of_get_property(np, "rockchip,pins", &size);
3048	3858	/* we do not check return since it's safe node passed down */
3049	3859	size /= sizeof(*list);
3050		- if (!size \|\| size % 4) {
3051		- dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
3052		- return -EINVAL;
3053		- }
	3860	+ if (!size \|\| size % 4)
	3861	+ return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
3054	3862
3055	3863	grp->npins = size / 4;
3056	3864
3057		- grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
3058		- GFP_KERNEL);
3059		- grp->data = devm_kcalloc(info->dev,
3060		- grp->npins,
3061		- sizeof(struct rockchip_pin_config),
3062		- GFP_KERNEL);
	3865	+ grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
	3866	+ grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3063	3867	if (!grp->pins \|\| !grp->data)
3064	3868	return -ENOMEM;
3065	3869
..	..	@@ -3093,6 +3897,7 @@
3093	3897	struct rockchip_pinctrl *info,
3094	3898	u32 index)
3095	3899	{
	3900	+ struct device *dev = info->dev;
3096	3901	struct device_node *child;
3097	3902	struct rockchip_pmx_func *func;
3098	3903	struct rockchip_pin_group *grp;
..	..	@@ -3100,7 +3905,7 @@
3100	3905	static u32 grp_index;
3101	3906	u32 i = 0;
3102	3907
3103		- dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
	3908	+ dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3104	3909
3105	3910	func = &info->functions[index];
3106	3911
..	..	@@ -3110,8 +3915,7 @@
3110	3915	if (func->ngroups <= 0)
3111	3916	return 0;
3112	3917
3113		- func->groups = devm_kcalloc(info->dev,
3114		- func->ngroups, sizeof(char *), GFP_KERNEL);
	3918	+ func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3115	3919	if (!func->groups)
3116	3920	return -ENOMEM;
3117	3921
..	..	@@ -3139,32 +3943,26 @@
3139	3943
3140	3944	rockchip_pinctrl_child_count(info, np);
3141	3945
3142		- dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
3143		- dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
	3946	+ dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
	3947	+ dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3144	3948
3145		- info->functions = devm_kcalloc(dev,
3146		- info->nfunctions,
3147		- sizeof(struct rockchip_pmx_func),
3148		- GFP_KERNEL);
	3949	+ info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3149	3950	if (!info->functions)
3150	3951	return -ENOMEM;
3151	3952
3152		- info->groups = devm_kcalloc(dev,
3153		- info->ngroups,
3154		- sizeof(struct rockchip_pin_group),
3155		- GFP_KERNEL);
	3953	+ info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3156	3954	if (!info->groups)
3157	3955	return -ENOMEM;
3158	3956
3159	3957	i = 0;
3160	3958
3161	3959	for_each_child_of_node(np, child) {
3162		- if (!is_function_node(child))
	3960	+ if (of_match_node(rockchip_bank_match, child))
3163	3961	continue;
3164	3962
3165	3963	ret = rockchip_pinctrl_parse_functions(child, info, i++);
3166	3964	if (ret) {
3167		- dev_err(&pdev->dev, "failed to parse function\n");
	3965	+ dev_err(dev, "failed to parse function\n");
3168	3966	of_node_put(child);
3169	3967	return ret;
3170	3968	}
..	..	@@ -3179,6 +3977,7 @@
3179	3977	struct pinctrl_desc *ctrldesc = &info->pctl;
3180	3978	struct pinctrl_pin_desc pindesc, pdesc;
3181	3979	struct rockchip_pin_bank *pin_bank;
	3980	+ struct device *dev = &pdev->dev;
3182	3981	int pin, bank, ret;
3183	3982	int k;
3184	3983
..	..	@@ -3188,9 +3987,7 @@
3188	3987	ctrldesc->pmxops = &rockchip_pmx_ops;
3189	3988	ctrldesc->confops = &rockchip_pinconf_ops;
3190	3989
3191		- pindesc = devm_kcalloc(&pdev->dev,
3192		- info->ctrl->nr_pins, sizeof(*pindesc),
3193		- GFP_KERNEL);
	3990	+ pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3194	3991	if (!pindesc)
3195	3992	return -ENOMEM;
3196	3993
..	..	@@ -3206,41 +4003,24 @@
3206	4003	pin_bank->name, pin);
3207	4004	pdesc++;
3208	4005	}
	4006	+
	4007	+ INIT_LIST_HEAD(&pin_bank->deferred_pins);
	4008	+ mutex_init(&pin_bank->deferred_lock);
3209	4009	}
3210	4010
3211	4011	ret = rockchip_pinctrl_parse_dt(pdev, info);
3212	4012	if (ret)
3213	4013	return ret;
3214	4014
3215		- info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3216		- if (IS_ERR(info->pctl_dev)) {
3217		- dev_err(&pdev->dev, "could not register pinctrl driver\n");
3218		- return PTR_ERR(info->pctl_dev);
3219		- }
	4015	+ info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
	4016	+ if (IS_ERR(info->pctl_dev))
	4017	+ return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3220	4018
3221	4019	return 0;
3222	4020	}
3223	4021
3224	4022	static const struct of_device_id rockchip_pinctrl_dt_match[];
3225		-
3226		-/* Ctrl data specially handle */
3227		-static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl)
3228		-{
3229		- /*
3230		- * Special for rk3308b, where we need to replace the recalced
3231		- * and routed arrays.
3232		- */
3233		- if (soc_is_rk3308b()) {
3234		- ctrl->iomux_recalced = rk3308b_mux_recalced_data;
3235		- ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data);
3236		- ctrl->iomux_routes = rk3308b_mux_route_data;
3237		- ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data);
3238		-
3239		- }
3240		-
3241		- return 0;
3242		-}
3243		-
	4023	+static struct rockchip_pin_bank rk3308bs_pin_banks[];
3244	4024	static struct rockchip_pin_bank px30s_pin_banks[];
3245	4025
3246	4026	/* retrieve the soc specific data */
..	..	@@ -3248,22 +4028,19 @@
3248	4028	struct rockchip_pinctrl *d,
3249	4029	struct platform_device *pdev)
3250	4030	{
	4031	+ struct device *dev = &pdev->dev;
	4032	+ struct device_node *node = dev->of_node;
3251	4033	const struct of_device_id *match;
3252		- struct device_node *node = pdev->dev.of_node;
3253	4034	struct rockchip_pin_ctrl *ctrl;
3254	4035	struct rockchip_pin_bank *bank;
3255	4036	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3256	4037
3257	4038	match = of_match_node(rockchip_pinctrl_dt_match, node);
3258	4039	ctrl = (struct rockchip_pin_ctrl *)match->data;
	4040	+ if (IS_ENABLED(CONFIG_CPU_RK3308) && soc_is_rk3308bs())
	4041	+ ctrl->pin_banks = rk3308bs_pin_banks;
3259	4042	if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
3260	4043	ctrl->pin_banks = px30s_pin_banks;
3261		-
3262		- /* Ctrl data re-initialize for some Socs */
3263		- if (ctrl->ctrl_data_re_init) {
3264		- if (ctrl->ctrl_data_re_init(ctrl))
3265		- return NULL;
3266		- }
3267	4044
3268	4045	grf_offs = ctrl->grf_mux_offset;
3269	4046	pmu_offs = ctrl->pmu_mux_offset;
..	..	@@ -3310,7 +4087,7 @@
3310	4087	drv_pmu_offs : drv_grf_offs;
3311	4088	}
3312	4089
3313		- dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
	4090	+ dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3314	4091	i, j, iom->offset, drv->offset);
3315	4092
3316	4093	/*
..	..	@@ -3417,60 +4194,56 @@
3417	4194
3418	4195	/* SoC data specially handle */
3419	4196
3420		-/* rk3308b SoC data initialize */
3421		-#define RK3308B_GRF_SOC_CON13 0x608
3422		-#define RK3308B_GRF_SOC_CON15 0x610
	4197	+/* rk3308 SoC data initialize */
	4198	+#define RK3308_GRF_SOC_CON13 0x608
	4199	+#define RK3308_GRF_SOC_CON15 0x610
3423	4200
3424		-/* RK3308B_GRF_SOC_CON13 */
3425		-#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) \| BIT(10))
3426		-#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
3427		-#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
	4201	+/* RK3308_GRF_SOC_CON13 */
	4202	+#define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) \| BIT(10))
	4203	+#define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
	4204	+#define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
3428	4205
3429		-/* RK3308B_GRF_SOC_CON15 */
3430		-#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) \| BIT(11))
3431		-#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
3432		-#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
	4206	+/* RK3308_GRF_SOC_CON15 */
	4207	+#define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) \| BIT(11))
	4208	+#define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
	4209	+#define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
3433	4210
3434		-static int rk3308b_soc_data_init(struct rockchip_pinctrl *info)
	4211	+static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
3435	4212	{
3436	4213	int ret;
3437	4214
3438	4215	/*
3439	4216	* Enable the special ctrl of selected sources.
3440	4217	*/
3441		- if (soc_is_rk3308b()) {
3442		- ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13,
3443		- RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL \|
3444		- RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL \|
3445		- RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL);
3446		- if (ret)
3447		- return ret;
3448	4218
3449		- ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15,
3450		- RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL \|
3451		- RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL \|
3452		- RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL);
3453		- if (ret)
3454		- return ret;
3455		- }
	4219	+ ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
	4220	+ RK3308_GRF_I2C3_IOFUNC_SRC_CTRL \|
	4221	+ RK3308_GRF_GPIO2A3_SEL_SRC_CTRL \|
	4222	+ RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
	4223	+ if (ret)
	4224	+ return ret;
3456	4225
3457		- return 0;
	4226	+ ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
	4227	+ RK3308_GRF_GPIO2C0_SEL_SRC_CTRL \|
	4228	+ RK3308_GRF_GPIO3B3_SEL_SRC_CTRL \|
	4229	+ RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
	4230	+
	4231	+ return ret;
	4232	+
3458	4233	}
3459	4234
3460	4235	static int rockchip_pinctrl_probe(struct platform_device *pdev)
3461	4236	{
3462	4237	struct rockchip_pinctrl *info;
3463	4238	struct device *dev = &pdev->dev;
	4239	+ struct device_node np = dev->of_node, node;
3464	4240	struct rockchip_pin_ctrl *ctrl;
3465		- struct device_node np = pdev->dev.of_node, node;
3466	4241	struct resource *res;
3467	4242	void __iomem *base;
3468	4243	int ret;
3469	4244
3470		- if (!dev->of_node) {
3471		- dev_err(dev, "device tree node not found\n");
3472		- return -ENODEV;
3473		- }
	4245	+ if (!dev->of_node)
	4246	+ return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
3474	4247
3475	4248	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3476	4249	if (!info)
..	..	@@ -3479,44 +4252,39 @@
3479	4252	info->dev = dev;
3480	4253
3481	4254	ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3482		- if (!ctrl) {
3483		- dev_err(dev, "driver data not available\n");
3484		- return -EINVAL;
3485		- }
	4255	+ if (!ctrl)
	4256	+ return dev_err_probe(dev, -EINVAL, "driver data not available\n");
3486	4257	info->ctrl = ctrl;
3487	4258
3488	4259	node = of_parse_phandle(np, "rockchip,grf", 0);
3489	4260	if (node) {
3490	4261	info->regmap_base = syscon_node_to_regmap(node);
	4262	+ of_node_put(node);
3491	4263	if (IS_ERR(info->regmap_base))
3492	4264	return PTR_ERR(info->regmap_base);
3493	4265	} else {
3494		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3495		- base = devm_ioremap_resource(&pdev->dev, res);
	4266	+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
3496	4267	if (IS_ERR(base))
3497	4268	return PTR_ERR(base);
3498	4269
3499	4270	rockchip_regmap_config.max_register = resource_size(res) - 4;
3500	4271	rockchip_regmap_config.name = "rockchip,pinctrl";
3501		- info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3502		- &rockchip_regmap_config);
	4272	+ info->regmap_base =
	4273	+ devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3503	4274
3504	4275	/* to check for the old dt-bindings */
3505	4276	info->reg_size = resource_size(res);
3506	4277
3507	4278	/* Honor the old binding, with pull registers as 2nd resource */
3508	4279	if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3509		- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3510		- base = devm_ioremap_resource(&pdev->dev, res);
	4280	+ base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
3511	4281	if (IS_ERR(base))
3512	4282	return PTR_ERR(base);
3513	4283
3514		- rockchip_regmap_config.max_register =
3515		- resource_size(res) - 4;
	4284	+ rockchip_regmap_config.max_register = resource_size(res) - 4;
3516	4285	rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3517		- info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3518		- base,
3519		- &rockchip_regmap_config);
	4286	+ info->regmap_pull =
	4287	+ devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3520	4288	}
3521	4289	}
3522	4290
..	..	@@ -3524,13 +4292,13 @@
3524	4292	node = of_parse_phandle(np, "rockchip,pmu", 0);
3525	4293	if (node) {
3526	4294	info->regmap_pmu = syscon_node_to_regmap(node);
	4295	+ of_node_put(node);
3527	4296	if (IS_ERR(info->regmap_pmu))
3528	4297	return PTR_ERR(info->regmap_pmu);
3529	4298	}
3530	4299
3531		- /* Special handle for some Socs */
3532		- if (ctrl->soc_data_init) {
3533		- ret = ctrl->soc_data_init(info);
	4300	+ if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) {
	4301	+ ret = rk3308_soc_data_init(info);
3534	4302	if (ret)
3535	4303	return ret;
3536	4304	}
..	..	@@ -3540,16 +4308,49 @@
3540	4308	return ret;
3541	4309
3542	4310	platform_set_drvdata(pdev, info);
	4311	+ g_pctldev = info->pctl_dev;
3543	4312
3544		- ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
3545		- if (ret) {
3546		- dev_err(&pdev->dev, "failed to register gpio device\n");
3547		- return ret;
3548		- }
	4313	+ ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
	4314	+ if (ret)
	4315	+ return dev_err_probe(dev, ret, "failed to register gpio device\n");
	4316	+
3549	4317	dev_info(dev, "probed %s\n", dev_name(dev));
3550	4318
3551	4319	return 0;
3552	4320	}
	4321	+
	4322	+static int rockchip_pinctrl_remove(struct platform_device *pdev)
	4323	+{
	4324	+ struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
	4325	+ struct rockchip_pin_bank *bank;
	4326	+ struct rockchip_pin_deferred *cfg;
	4327	+ int i;
	4328	+
	4329	+ g_pctldev = NULL;
	4330	+ of_platform_depopulate(&pdev->dev);
	4331	+
	4332	+ for (i = 0; i < info->ctrl->nr_banks; i++) {
	4333	+ bank = &info->ctrl->pin_banks[i];
	4334	+
	4335	+ mutex_lock(&bank->deferred_lock);
	4336	+ while (!list_empty(&bank->deferred_pins)) {
	4337	+ cfg = list_first_entry(&bank->deferred_pins,
	4338	+ struct rockchip_pin_deferred, head);
	4339	+ list_del(&cfg->head);
	4340	+ kfree(cfg);
	4341	+ }
	4342	+ mutex_unlock(&bank->deferred_lock);
	4343	+ }
	4344	+
	4345	+ return 0;
	4346	+}
	4347	+
	4348	+static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
	4349	+ S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
	4350	+ S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4351	+ S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4352	+ S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4353	+};
3553	4354
3554	4355	static struct rockchip_pin_bank px30_pin_banks[] = {
3555	4356	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
..	..	@@ -3574,13 +4375,6 @@
3574	4375	),
3575	4376	};
3576	4377
3577		-static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
3578		- PX30S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
3579		- PX30S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3580		- PX30S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3581		- PX30S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3582		-};
3583		-
3584	4378	static struct rockchip_pin_ctrl px30_pin_ctrl __maybe_unused = {
3585	4379	.pin_banks = px30_pin_banks,
3586	4380	.nr_banks = ARRAY_SIZE(px30_pin_banks),
..	..	@@ -3594,6 +4388,48 @@
3594	4388	.drv_calc_reg = px30_calc_drv_reg_and_bit,
3595	4389	.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3596	4390	.slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
	4391	+};
	4392	+
	4393	+static struct rockchip_pin_bank rv1106_pin_banks[] = {
	4394	+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
	4395	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4396	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4397	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4398	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU),
	4399	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4400	+ IOMUX_WIDTH_4BIT,
	4401	+ IOMUX_WIDTH_4BIT,
	4402	+ IOMUX_WIDTH_4BIT,
	4403	+ IOMUX_WIDTH_4BIT,
	4404	+ 0, 0x08, 0x10, 0x18),
	4405	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4406	+ IOMUX_WIDTH_4BIT,
	4407	+ IOMUX_WIDTH_4BIT,
	4408	+ IOMUX_WIDTH_4BIT,
	4409	+ IOMUX_WIDTH_4BIT,
	4410	+ 0x10020, 0x10028, 0, 0),
	4411	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4412	+ IOMUX_WIDTH_4BIT,
	4413	+ IOMUX_WIDTH_4BIT,
	4414	+ IOMUX_WIDTH_4BIT,
	4415	+ IOMUX_WIDTH_4BIT,
	4416	+ 0x20040, 0x20048, 0x20050, 0x20058),
	4417	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4",
	4418	+ IOMUX_WIDTH_4BIT,
	4419	+ IOMUX_WIDTH_4BIT,
	4420	+ IOMUX_WIDTH_4BIT,
	4421	+ 0,
	4422	+ 0x30000, 0x30008, 0x30010, 0),
	4423	+};
	4424	+
	4425	+static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
	4426	+ .pin_banks = rv1106_pin_banks,
	4427	+ .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
	4428	+ .label = "RV1106-GPIO",
	4429	+ .type = RV1106,
	4430	+ .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
	4431	+ .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
	4432	+ .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
3597	4433	};
3598	4434
3599	4435	static struct rockchip_pin_bank rv1108_pin_banks[] = {
..	..	@@ -3866,6 +4702,14 @@
3866	4702	.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3867	4703	};
3868	4704
	4705	+static struct rockchip_pin_bank rk3308bs_pin_banks[] __maybe_unused = {
	4706	+ S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4707	+ S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4708	+ S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4709	+ S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4710	+ S_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4711	+};
	4712	+
3869	4713	static struct rockchip_pin_bank rk3308_pin_banks[] = {
3870	4714	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3871	4715	IOMUX_WIDTH_2BIT,
..	..	@@ -3899,11 +4743,10 @@
3899	4743	.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3900	4744	.iomux_routes = rk3308_mux_route_data,
3901	4745	.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3902		- .ctrl_data_re_init = rk3308b_ctrl_data_re_init,
3903		- .soc_data_init = rk3308b_soc_data_init,
3904	4746	.pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3905	4747	.drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3906	4748	.schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
	4749	+ .slew_rate_calc_reg = rk3308_calc_slew_rate_reg_and_bit,
3907	4750	};
3908	4751
3909	4752	static struct rockchip_pin_bank rk3328_pin_banks[] = {
..	..	@@ -4025,6 +4868,92 @@
4025	4868	.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4026	4869	};
4027	4870
	4871	+static struct rockchip_pin_bank rk3528_pin_banks[] = {
	4872	+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
	4873	+ IOMUX_WIDTH_4BIT,
	4874	+ IOMUX_WIDTH_4BIT,
	4875	+ IOMUX_WIDTH_4BIT,
	4876	+ IOMUX_WIDTH_4BIT,
	4877	+ 0, 0, 0, 0),
	4878	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4879	+ IOMUX_WIDTH_4BIT,
	4880	+ IOMUX_WIDTH_4BIT,
	4881	+ IOMUX_WIDTH_4BIT,
	4882	+ IOMUX_WIDTH_4BIT,
	4883	+ 0x20020, 0x20028, 0x20030, 0x20038),
	4884	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4885	+ IOMUX_WIDTH_4BIT,
	4886	+ IOMUX_WIDTH_4BIT,
	4887	+ IOMUX_WIDTH_4BIT,
	4888	+ IOMUX_WIDTH_4BIT,
	4889	+ 0x30040, 0, 0, 0),
	4890	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4891	+ IOMUX_WIDTH_4BIT,
	4892	+ IOMUX_WIDTH_4BIT,
	4893	+ IOMUX_WIDTH_4BIT,
	4894	+ IOMUX_WIDTH_4BIT,
	4895	+ 0x20060, 0x20068, 0x20070, 0),
	4896	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
	4897	+ IOMUX_WIDTH_4BIT,
	4898	+ IOMUX_WIDTH_4BIT,
	4899	+ IOMUX_WIDTH_4BIT,
	4900	+ IOMUX_WIDTH_4BIT,
	4901	+ 0x10080, 0x10088, 0x10090, 0x10098),
	4902	+};
	4903	+
	4904	+static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = {
	4905	+ .pin_banks = rk3528_pin_banks,
	4906	+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
	4907	+ .label = "RK3528-GPIO",
	4908	+ .type = RK3528,
	4909	+ .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
	4910	+ .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
	4911	+ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
	4912	+};
	4913	+
	4914	+static struct rockchip_pin_bank rk3562_pin_banks[] = {
	4915	+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
	4916	+ IOMUX_WIDTH_4BIT,
	4917	+ IOMUX_WIDTH_4BIT,
	4918	+ IOMUX_WIDTH_4BIT,
	4919	+ IOMUX_WIDTH_4BIT,
	4920	+ 0x20000, 0x20008, 0x20010, 0x20018),
	4921	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4922	+ IOMUX_WIDTH_4BIT,
	4923	+ IOMUX_WIDTH_4BIT,
	4924	+ IOMUX_WIDTH_4BIT,
	4925	+ IOMUX_WIDTH_4BIT,
	4926	+ 0, 0x08, 0x10, 0x18),
	4927	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4928	+ IOMUX_WIDTH_4BIT,
	4929	+ IOMUX_WIDTH_4BIT,
	4930	+ IOMUX_WIDTH_4BIT,
	4931	+ IOMUX_WIDTH_4BIT,
	4932	+ 0x20, 0, 0, 0),
	4933	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4934	+ IOMUX_WIDTH_4BIT,
	4935	+ IOMUX_WIDTH_4BIT,
	4936	+ IOMUX_WIDTH_4BIT,
	4937	+ IOMUX_WIDTH_4BIT,
	4938	+ 0x10040, 0x10048, 0x10050, 0x10058),
	4939	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
	4940	+ IOMUX_WIDTH_4BIT,
	4941	+ IOMUX_WIDTH_4BIT,
	4942	+ 0,
	4943	+ 0,
	4944	+ 0x10060, 0x10068, 0, 0),
	4945	+};
	4946	+
	4947	+static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
	4948	+ .pin_banks = rk3562_pin_banks,
	4949	+ .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
	4950	+ .label = "RK3562-GPIO",
	4951	+ .type = RK3562,
	4952	+ .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
	4953	+ .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
	4954	+ .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
	4955	+};
	4956	+
4028	4957	static struct rockchip_pin_bank rk3568_pin_banks[] = {
4029	4958	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU \| IOMUX_WIDTH_4BIT,
4030	4959	IOMUX_SOURCE_PMU \| IOMUX_WIDTH_4BIT,
..	..	@@ -4065,12 +4994,39 @@
4065	4994	.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4066	4995	};
4067	4996
	4997	+static struct rockchip_pin_bank rk3588_pin_banks[] = {
	4998	+ RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
	4999	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5000	+ RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
	5001	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5002	+ RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
	5003	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5004	+ RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
	5005	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5006	+ RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
	5007	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5008	+};
	5009	+
	5010	+static struct rockchip_pin_ctrl rk3588_pin_ctrl __maybe_unused = {
	5011	+ .pin_banks = rk3588_pin_banks,
	5012	+ .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
	5013	+ .label = "RK3588-GPIO",
	5014	+ .type = RK3588,
	5015	+ .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
	5016	+ .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
	5017	+ .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
	5018	+};
	5019	+
4068	5020	static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4069	5021	#ifdef CONFIG_CPU_PX30
4070	5022	{ .compatible = "rockchip,px30-pinctrl",
4071	5023	.data = &px30_pin_ctrl },
4072	5024	#endif
4073		-#ifdef CONFIG_CPU_RV110X
	5025	+#ifdef CONFIG_CPU_RV1106
	5026	+ { .compatible = "rockchip,rv1106-pinctrl",
	5027	+ .data = &rv1106_pin_ctrl },
	5028	+#endif
	5029	+#ifdef CONFIG_CPU_RV1108
4074	5030	{ .compatible = "rockchip,rv1108-pinctrl",
4075	5031	.data = &rv1108_pin_ctrl },
4076	5032	#endif
..	..	@@ -4128,15 +5084,28 @@
4128	5084	{ .compatible = "rockchip,rk3399-pinctrl",
4129	5085	.data = &rk3399_pin_ctrl },
4130	5086	#endif
	5087	+#ifdef CONFIG_CPU_RK3528
	5088	+ { .compatible = "rockchip,rk3528-pinctrl",
	5089	+ .data = &rk3528_pin_ctrl },
	5090	+#endif
	5091	+#ifdef CONFIG_CPU_RK3562
	5092	+ { .compatible = "rockchip,rk3562-pinctrl",
	5093	+ .data = &rk3562_pin_ctrl },
	5094	+#endif
4131	5095	#ifdef CONFIG_CPU_RK3568
4132	5096	{ .compatible = "rockchip,rk3568-pinctrl",
4133	5097	.data = &rk3568_pin_ctrl },
	5098	+#endif
	5099	+#ifdef CONFIG_CPU_RK3588
	5100	+ { .compatible = "rockchip,rk3588-pinctrl",
	5101	+ .data = &rk3588_pin_ctrl },
4134	5102	#endif
4135	5103	{},
4136	5104	};
4137	5105
4138	5106	static struct platform_driver rockchip_pinctrl_driver = {
4139	5107	.probe = rockchip_pinctrl_probe,
	5108	+ .remove = rockchip_pinctrl_remove,
4140	5109	.driver = {
4141	5110	.name = "rockchip-pinctrl",
4142	5111	.pm = &rockchip_pinctrl_dev_pm_ops,
..	..	@@ -4156,6 +5125,103 @@
4156	5125	}
4157	5126	module_exit(rockchip_pinctrl_drv_unregister);
4158	5127
	5128	+/**
	5129	+ * rk_iomux_set - set the rockchip iomux by pin number.
	5130	+ *
	5131	+ * @bank: the gpio bank index, from 0 to the max bank num.
	5132	+ * @pin: the gpio pin index, from 0 to 31.
	5133	+ * @mux: the pointer to store mux value.
	5134	+ *
	5135	+ * Return 0 if set success, else return error code.
	5136	+ */
	5137	+int rk_iomux_set(int bank, int pin, int mux)
	5138	+{
	5139	+ struct pinctrl_dev *pctldev = g_pctldev;
	5140	+ struct rockchip_pinctrl *info;
	5141	+ struct rockchip_pin_bank *gpio;
	5142	+ struct rockchip_pin_group *grp = NULL;
	5143	+ struct rockchip_pin_config *cfg = NULL;
	5144	+ int i, j, ret;
	5145	+
	5146	+ if (!g_pctldev)
	5147	+ return -ENODEV;
	5148	+
	5149	+ info = pinctrl_dev_get_drvdata(pctldev);
	5150	+ if (bank >= info->ctrl->nr_banks)
	5151	+ return -EINVAL;
	5152	+
	5153	+ if (pin > 31 \|\| pin < 0)
	5154	+ return -EINVAL;
	5155	+
	5156	+ gpio = &info->ctrl->pin_banks[bank];
	5157	+
	5158	+ mutex_lock(&iomux_lock);
	5159	+ for (i = 0; i < info->ngroups; i++) {
	5160	+ grp = &info->groups[i];
	5161	+ for (j = 0; j < grp->npins; i++) {
	5162	+ if (grp->pins[i] == (gpio->pin_base + pin)) {
	5163	+ cfg = grp->data;
	5164	+ break;
	5165	+ }
	5166	+ }
	5167	+ }
	5168	+
	5169	+ ret = rockchip_set_mux(gpio, pin, mux);
	5170	+ if (ret) {
	5171	+ dev_err(info->dev, "mux GPIO%d-%d %d fail\n", bank, pin, mux);
	5172	+ goto out;
	5173	+ }
	5174	+
	5175	+ if (cfg && (cfg->func != mux))
	5176	+ cfg->func = mux;
	5177	+
	5178	+out:
	5179	+ mutex_unlock(&iomux_lock);
	5180	+
	5181	+ return ret;
	5182	+}
	5183	+EXPORT_SYMBOL_GPL(rk_iomux_set);
	5184	+
	5185	+/**
	5186	+ * rk_iomux_get - get the rockchip iomux by pin number.
	5187	+ *
	5188	+ * @bank: the gpio bank index, from 0 to the max bank num.
	5189	+ * @pin: the gpio pin index, from 0 to 31.
	5190	+ * @mux: the pointer to store mux value.
	5191	+ *
	5192	+ * Return 0 if get success, else return error code.
	5193	+ */
	5194	+int rk_iomux_get(int bank, int pin, int *mux)
	5195	+{
	5196	+ struct pinctrl_dev *pctldev = g_pctldev;
	5197	+ struct rockchip_pinctrl *info;
	5198	+ struct rockchip_pin_bank *gpio;
	5199	+ int ret;
	5200	+
	5201	+ if (!g_pctldev)
	5202	+ return -ENODEV;
	5203	+ if (!mux)
	5204	+ return -EINVAL;
	5205	+
	5206	+ info = pinctrl_dev_get_drvdata(pctldev);
	5207	+ if (bank >= info->ctrl->nr_banks)
	5208	+ return -EINVAL;
	5209	+
	5210	+ if (pin > 31 \|\| pin < 0)
	5211	+ return -EINVAL;
	5212	+
	5213	+ gpio = &info->ctrl->pin_banks[bank];
	5214	+
	5215	+ mutex_lock(&iomux_lock);
	5216	+ ret = rockchip_get_mux(gpio, pin);
	5217	+ mutex_unlock(&iomux_lock);
	5218	+
	5219	+ *mux = ret;
	5220	+
	5221	+ return (ret >= 0) ? 0 : ret;
	5222	+}
	5223	+EXPORT_SYMBOL_GPL(rk_iomux_get);
	5224	+
4159	5225	MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4160	5226	MODULE_LICENSE("GPL");
4161	5227	MODULE_ALIAS("platform:pinctrl-rockchip");