forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
....@@ -1,17 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Rockchip USB2.0 PHY with Innosilicon IP block driver
34  *
45  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
156  */
167 
178 #include <linux/clk.h>
....@@ -34,10 +25,13 @@
3425 #include <linux/pm_runtime.h>
3526 #include <linux/power_supply.h>
3627 #include <linux/regmap.h>
28
+#include <linux/reset.h>
3729 #include <linux/rockchip/cpu.h>
3830 #include <linux/mfd/syscon.h>
3931 #include <linux/usb/of.h>
4032 #include <linux/usb/otg.h>
33
+#include <linux/usb/role.h>
34
+#include <linux/usb/typec_mux.h>
4135 #include <linux/wakelock.h>
4236 
4337 #define BIT_WRITEABLE_SHIFT	16
....@@ -63,16 +57,16 @@
6357 };
6458 
6559 /**
66
- * Different states involved in USB charger detection.
67
- * USB_CHG_STATE_UNDEFINED	USB charger is not connected or detection
60
+ * enum usb_chg_state - Different states involved in USB charger detection.
61
+ * @USB_CHG_STATE_UNDEFINED:	USB charger is not connected or detection
6862  *				process is not yet started.
69
- * USB_CHG_STATE_WAIT_FOR_DCD	Waiting for Data pins contact.
70
- * USB_CHG_STATE_DCD_DONE	Data pin contact is detected.
71
- * USB_CHG_STATE_PRIMARY_DONE	Primary detection is completed (Detects
63
+ * @USB_CHG_STATE_WAIT_FOR_DCD:	Waiting for Data pins contact.
64
+ * @USB_CHG_STATE_DCD_DONE:	Data pin contact is detected.
65
+ * @USB_CHG_STATE_PRIMARY_DONE:	Primary detection is completed (Detects
7266  *				between SDP and DCP/CDP).
73
- * USB_CHG_STATE_SECONDARY_DONE	Secondary detection is completed (Detects
74
- *				between DCP and CDP).
75
- * USB_CHG_STATE_DETECTED	USB charger type is determined.
67
+ * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
68
+ *				  between DCP and CDP).
69
+ * @USB_CHG_STATE_DETECTED:	USB charger type is determined.
7670  */
7771 enum usb_chg_state {
7872 	USB_CHG_STATE_UNDEFINED = 0,
....@@ -103,7 +97,7 @@
10397 };
10498 
10599 /**
106
- * struct rockchip_chg_det_reg: usb charger detect registers
100
+ * struct rockchip_chg_det_reg - usb charger detect registers
107101  * @cp_det: charging port detected successfully.
108102  * @dcp_det: dedicated charging port detected successfully.
109103  * @dp_det: assert data pin connect successfully.
....@@ -129,18 +123,27 @@
129123 };
130124 
131125 /**
132
- * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
126
+ * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
133127  * @phy_sus: phy suspend register.
128
+ * @pipe_phystatus: select pipe phystatus from grf or phy.
134129  * @bvalid_det_en: vbus valid rise detection enable register.
135130  * @bvalid_det_st: vbus valid rise detection status register.
136131  * @bvalid_det_clr: vbus valid rise detection clear register.
137
- * @bvalid_set: bvalid select and set to usb controller.
132
+ * @bvalid_grf_con: vbus valid software control.
133
+ * @bvalid_grf_sel: vbus valid software control select.
134
+ * @bvalid_phy_con: vbus valid external select and enable.
138135  * @bypass_dm_en: usb bypass uart DM enable register.
139136  * @bypass_sel: usb bypass uart select register.
140137  * @bypass_iomux: usb bypass uart GRF iomux register.
141138  * @bypass_bc: bypass battery charging module.
142139  * @bypass_otg: bypass otg module.
143140  * @bypass_host: bypass host module.
141
+ * @disfall_en: host disconnect fall edge detection enable.
142
+ * @disfall_st: host disconnect fall edge detection state.
143
+ * @disfall_clr: host disconnect fall edge detection clear.
144
+ * @disrise_en: host disconnect rise edge detection enable.
145
+ * @disrise_st: host disconnect rise edge detection state.
146
+ * @disrise_clr: host disconnect rise edge detection clear.
144147  * @ls_det_en: linestate detection enable register.
145148  * @ls_det_st: linestate detection state register.
146149  * @ls_det_clr: linestate detection clear register.
....@@ -163,16 +166,25 @@
163166  */
164167 struct rockchip_usb2phy_port_cfg {
165168 	struct usb2phy_reg	phy_sus;
169
+	struct usb2phy_reg	pipe_phystatus;
166170 	struct usb2phy_reg	bvalid_det_en;
167171 	struct usb2phy_reg	bvalid_det_st;
168172 	struct usb2phy_reg	bvalid_det_clr;
169
-	struct usb2phy_reg	bvalid_set;
173
+	struct usb2phy_reg	bvalid_grf_con;
174
+	struct usb2phy_reg	bvalid_grf_sel;
175
+	struct usb2phy_reg	bvalid_phy_con;
170176 	struct usb2phy_reg	bypass_dm_en;
171177 	struct usb2phy_reg	bypass_sel;
172178 	struct usb2phy_reg	bypass_iomux;
173179 	struct usb2phy_reg	bypass_bc;
174180 	struct usb2phy_reg	bypass_otg;
175181 	struct usb2phy_reg	bypass_host;
182
+	struct usb2phy_reg	disfall_en;
183
+	struct usb2phy_reg	disfall_st;
184
+	struct usb2phy_reg	disfall_clr;
185
+	struct usb2phy_reg	disrise_en;
186
+	struct usb2phy_reg	disrise_st;
187
+	struct usb2phy_reg	disrise_clr;
176188 	struct usb2phy_reg	ls_det_en;
177189 	struct usb2phy_reg	ls_det_st;
178190 	struct usb2phy_reg	ls_det_clr;
....@@ -194,21 +206,23 @@
194206 };
195207 
196208 /**
197
- * struct rockchip_usb2phy_cfg: usb-phy configuration.
209
+ * struct rockchip_usb2phy_cfg - usb-phy configuration.
198210  * @reg: the address offset of grf for usb-phy config.
199211  * @num_ports: specify how many ports that the phy has.
200
- * @phy_tuning: phy default parameters tunning.
212
+ * @phy_tuning: phy default parameters tuning.
201213  * @vbus_detect: vbus voltage level detection function.
202214  * @clkout_ctl: keep on/turn off output clk of phy via commonon bit.
203215  * @clkout_ctl_phy: keep on/turn off output clk of phy via phy inner
204216  *		    debug register.
217
+ * @ls_filter_con: set linestate filter time.
218
+ * @port_cfgs: usb-phy port configurations.
205219  * @ls_filter_con: set linestate filter time.
206220  * @chg_det: charger detection registers.
207221  */
208222 struct rockchip_usb2phy_cfg {
209223 	unsigned int	reg;
210224 	unsigned int	num_ports;
211
-	int (*phy_tuning)(struct rockchip_usb2phy *);
225
+	int (*phy_tuning)(struct rockchip_usb2phy *rphy);
212226 	int (*vbus_detect)(struct rockchip_usb2phy *rphy,
213227 			   const struct usb2phy_reg *vbus_det_en,
214228 			   bool en);
....@@ -220,19 +234,24 @@
220234 };
221235 
222236 /**
223
- * struct rockchip_usb2phy_port: usb-phy port data.
237
+ * struct rockchip_usb2phy_port - usb-phy port data.
238
+ * @phy: generic phy.
224239  * @port_id: flag for otg port or host port.
225240  * @low_power_en: enable enter low power when suspend.
226241  * @perip_connected: flag for periphyeral connect status.
227242  * @prev_iddig: previous otg port id pin status.
243
+ * @sel_pipe_phystatus: select pipe phystatus from grf.
228244  * @suspended: phy suspended flag.
245
+ * @typec_vbus_det: Type-C otg vbus detect.
229246  * @utmi_avalid: utmi avalid status usage flag.
230247  *	true	- use avalid to get vbus status
231
- *	flase	- use bvalid to get vbus status
248
+ *	false	- use bvalid to get vbus status
232249  * @vbus_attached: otg device vbus status.
233250  * @vbus_always_on: otg vbus is always powered on.
234251  * @vbus_enabled: vbus regulator status.
235252  * @bypass_uart_en: usb bypass uart enable, passed from DT.
253
+ * @host_disconnect: usb host disconnect status.
254
+ * @dis_u2_susphy: disable usb2 phy suspend.
236255  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
237256  * @ls_irq: IRQ number assigned for linestate detection.
238257  * @id_irq: IRQ number assigned for id fall or rise detection.
....@@ -244,7 +263,8 @@
244263  * @otg_sm_work: OTG state machine work.
245264  * @sm_work: HOST state machine work.
246265  * @vbus: vbus regulator supply on few rockchip boards.
247
- * @phy_cfg: port register configuration, assigned by driver data.
266
+ * @sw: orientation switch, communicate with TCPM (Type-C Port Manager).
267
+ * @port_cfg: port register configuration, assigned by driver data.
248268  * @event_nb: hold event notification callback.
249269  * @state: define OTG enumeration states before device reset.
250270  * @mode: the dr_mode of the controller.
....@@ -255,12 +275,15 @@
255275 	bool		low_power_en;
256276 	bool		perip_connected;
257277 	bool		prev_iddig;
278
+	bool		sel_pipe_phystatus;
258279 	bool		suspended;
280
+	bool		typec_vbus_det;
259281 	bool		utmi_avalid;
260282 	bool		vbus_attached;
261283 	bool		vbus_always_on;
262284 	bool		vbus_enabled;
263285 	bool		bypass_uart_en;
286
+	bool		host_disconnect;
264287 	bool		dis_u2_susphy;
265288 	int		bvalid_irq;
266289 	int		ls_irq;
....@@ -272,6 +295,7 @@
272295 	struct		delayed_work otg_sm_work;
273296 	struct		delayed_work sm_work;
274297 	struct		regulator *vbus;
298
+	struct		typec_switch *sw;
275299 	const struct	rockchip_usb2phy_port_cfg *port_cfg;
276300 	struct notifier_block	event_nb;
277301 	struct wake_lock	wakelock;
....@@ -280,13 +304,16 @@
280304 };
281305 
282306 /**
283
- * struct rockchip_usb2phy: usb2.0 phy driver data.
307
+ * struct rockchip_usb2phy - usb2.0 phy driver data.
308
+ * @dev: pointer to device.
284309  * @grf: General Register Files regmap.
285310  * @usbgrf: USB General Register Files regmap.
311
+ * @usbctrl_grf: USB Controller General Register Files regmap.
286312  * *phy_base: the base address of USB PHY.
313
+ * @phy_reset: phy reset control.
287314  * @clks: array of phy input clocks.
288315  * @clk480m: clock struct of phy output clk.
289
- * @clk_hw: clock struct of phy output clk management.
316
+ * @clk480m_hw: clock struct of phy output clk management.
290317  * @num_clks: number of phy input clocks.
291318  * @chg_state: states involved in USB charger detection.
292319  * @chg_type: USB charger types.
....@@ -306,7 +333,9 @@
306333 	struct device	*dev;
307334 	struct regmap	*grf;
308335 	struct regmap	*usbgrf;
336
+	struct regmap	*usbctrl_grf;
309337 	void __iomem	*phy_base;
338
+	struct reset_control	*phy_reset;
310339 	struct clk_bulk_data	*clks;
311340 	struct clk	*clk480m;
312341 	struct clk_hw	clk480m_hw;
....@@ -376,6 +405,53 @@
376405 	orig = readl(base + reg->offset);
377406 	tmp = (orig & mask) >> reg->bitstart;
378407 	return tmp == reg->enable;
408
+}
409
+
410
+static inline void phy_clear_bits(void __iomem *reg, u32 bits)
411
+{
412
+	u32 tmp = readl(reg);
413
+
414
+	tmp &= ~bits;
415
+	writel(tmp, reg);
416
+}
417
+
418
+static inline void phy_set_bits(void __iomem *reg, u32 bits)
419
+{
420
+	u32 tmp = readl(reg);
421
+
422
+	tmp |= bits;
423
+	writel(tmp, reg);
424
+}
425
+
426
+static inline void phy_update_bits(void __iomem *reg, u32 mask, u32 val)
427
+{
428
+	u32 tmp = readl(reg);
429
+
430
+	tmp &= ~mask;
431
+	tmp |= val & mask;
432
+	writel(tmp, reg);
433
+}
434
+
435
+static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
436
+{
437
+	int ret;
438
+
439
+	if (!rphy->phy_reset)
440
+		return 0;
441
+
442
+	ret = reset_control_assert(rphy->phy_reset);
443
+	if (ret)
444
+		return ret;
445
+
446
+	udelay(10);
447
+
448
+	ret = reset_control_deassert(rphy->phy_reset);
449
+	if (ret)
450
+		return ret;
451
+
452
+	usleep_range(100, 200);
453
+
454
+	return 0;
379455 }
380456 
381457 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
....@@ -595,6 +671,29 @@
595671 	return ret;
596672 }
597673 
674
+static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy,
675
+						 struct rockchip_usb2phy_port *rport,
676
+						 bool en)
677
+{
678
+	int ret;
679
+
680
+	ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
681
+	if (ret)
682
+		goto out;
683
+
684
+	ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
685
+	if (ret)
686
+		goto out;
687
+
688
+	ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
689
+	if (ret)
690
+		goto out;
691
+
692
+	ret = property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
693
+out:
694
+	return ret;
695
+}
696
+
598697 static int rockchip_usb_bypass_uart(struct rockchip_usb2phy_port *rport,
599698 				    bool en)
600699 {
....@@ -693,8 +792,13 @@
693792 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
694793 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
695794 	int ret = 0;
795
+	unsigned int ul, ul_mask;
696796 
697797 	mutex_lock(&rport->mutex);
798
+
799
+	if (rport->sel_pipe_phystatus)
800
+		property_enable(rphy->usbctrl_grf,
801
+				&rport->port_cfg->pipe_phystatus, true);
698802 
699803 	if (rport->port_id == USB2PHY_PORT_OTG &&
700804 	    (rport->mode == USB_DR_MODE_PERIPHERAL ||
....@@ -721,11 +825,24 @@
721825 					"failed to enable bvalid irq\n");
722826 				goto out;
723827 			}
724
-
725828 			schedule_delayed_work(&rport->otg_sm_work,
726
-					      OTG_SCHEDULE_DELAY);
829
+					      rport->typec_vbus_det ? 0 : OTG_SCHEDULE_DELAY);
727830 		}
728831 	} else if (rport->port_id == USB2PHY_PORT_HOST) {
832
+		if (rport->port_cfg->disfall_en.offset) {
833
+			ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
834
+			if (ret < 0)
835
+				goto out;
836
+			ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
837
+					  rport->port_cfg->utmi_ls.bitstart);
838
+			rport->host_disconnect = (ul & ul_mask) == 0 ? true : false;
839
+			ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true);
840
+			if (ret) {
841
+				dev_err(rphy->dev, "failed to enable disconnect irq\n");
842
+				goto out;
843
+			}
844
+		}
845
+
729846 		/* clear linestate and enable linestate detect irq */
730847 		ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
731848 		if (ret) {
....@@ -773,6 +890,21 @@
773890 	ret = property_enable(base, &rport->port_cfg->phy_sus, false);
774891 	if (ret)
775892 		goto unlock;
893
+
894
+	/*
895
+	 * For rk3588, it needs to reset phy when exit from
896
+	 * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC,
897
+	 * Bias, and PLL blocks are powered down) for lower
898
+	 * power consumption. If you don't want to reset phy,
899
+	 * please keep the common_on_n 1'b0 to set these blocks
900
+	 * remain powered.
901
+	 */
902
+	if (rport->port_id == USB2PHY_PORT_OTG &&
903
+	    of_device_is_compatible(rphy->dev->of_node, "rockchip,rk3588-usb2phy")) {
904
+		ret = rockchip_usb2phy_reset(rphy);
905
+		if (ret)
906
+			goto unlock;
907
+	}
776908 
777909 	/* waiting for the utmi_clk to become stable */
778910 	usleep_range(1500, 2000);
....@@ -830,7 +962,7 @@
830962 	if (rport->port_id == USB2PHY_PORT_HOST)
831963 		cancel_delayed_work_sync(&rport->sm_work);
832964 	else if (rport->port_id == USB2PHY_PORT_OTG &&
833
-		 rport->bvalid_irq > 0)
965
+		 rport->otg_sm_work.work.func)
834966 		flush_delayed_work(&rport->otg_sm_work);
835967 
836968 	return 0;
....@@ -859,7 +991,8 @@
859991 	return ret;
860992 }
861993 
862
-static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode)
994
+static int rockchip_usb2phy_set_mode(struct phy *phy,
995
+				     enum phy_mode mode, int submode)
863996 {
864997 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
865998 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
....@@ -871,16 +1004,31 @@
8711004 
8721005 	switch (mode) {
8731006 	case PHY_MODE_USB_OTG:
1007
+		if (rphy->edev_self && submode) {
1008
+			if (submode == USB_ROLE_HOST) {
1009
+				extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1010
+				extcon_set_state(rphy->edev, EXTCON_USB, false);
1011
+			} else if (submode == USB_ROLE_DEVICE) {
1012
+				extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1013
+				extcon_set_state(rphy->edev, EXTCON_USB, true);
1014
+			}
1015
+
1016
+			return ret;
1017
+		}
1018
+
8741019 		/*
8751020 		 * In case of using vbus to detect connect state by u2phy,
8761021 		 * enable vbus detect on otg mode.
877
-		 *
878
-		 * fallthrough
8791022 		 */
1023
+		fallthrough;
8801024 	case PHY_MODE_USB_DEVICE:
8811025 		/* Disable VBUS supply */
8821026 		rockchip_set_vbus_power(rport, false);
8831027 		extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, false);
1028
+		/* For vbus always on, set EXTCON_USB to true. */
1029
+		if (rport->vbus_always_on)
1030
+			extcon_set_state(rphy->edev, EXTCON_USB, true);
1031
+		rport->perip_connected = true;
8841032 		vbus_det_en = true;
8851033 		break;
8861034 	case PHY_MODE_USB_HOST:
....@@ -893,7 +1041,11 @@
8931041 		}
8941042 
8951043 		extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, true);
896
-		/* fallthrough */
1044
+		/* For vbus always on, deinit EXTCON_USB to false. */
1045
+		if (rport->vbus_always_on)
1046
+			extcon_set_state(rphy->edev, EXTCON_USB, false);
1047
+		rport->perip_connected = false;
1048
+		fallthrough;
8971049 	case PHY_MODE_INVALID:
8981050 		vbus_det_en = false;
8991051 		break;
....@@ -953,8 +1105,6 @@
9531105 		return sprintf(buf, "otg\n");
9541106 	case USB_DR_MODE_UNKNOWN:
9551107 		return sprintf(buf, "UNKNOWN\n");
956
-	default:
957
-		break;
9581108 	}
9591109 
9601110 	return -EINVAL;
....@@ -1011,17 +1161,17 @@
10111161 
10121162 	switch (rport->mode) {
10131163 	case USB_DR_MODE_HOST:
1014
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST);
1164
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
10151165 		property_enable(base, &rport->port_cfg->iddig_output, false);
10161166 		property_enable(base, &rport->port_cfg->iddig_en, true);
10171167 		break;
10181168 	case USB_DR_MODE_PERIPHERAL:
1019
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE);
1169
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
10201170 		property_enable(base, &rport->port_cfg->iddig_output, true);
10211171 		property_enable(base, &rport->port_cfg->iddig_en, true);
10221172 		break;
10231173 	case USB_DR_MODE_OTG:
1024
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG);
1174
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
10251175 		property_enable(base, &rport->port_cfg->iddig_output, false);
10261176 		property_enable(base, &rport->port_cfg->iddig_en, false);
10271177 		break;
....@@ -1060,7 +1210,10 @@
10601210 
10611211 	mutex_lock(&rport->mutex);
10621212 
1063
-	if (rport->utmi_avalid)
1213
+	if (rport->port_cfg->bvalid_grf_con.enable && rport->typec_vbus_det)
1214
+		rport->vbus_attached =
1215
+			property_enabled(rphy->grf, &rport->port_cfg->bvalid_grf_con);
1216
+	else if (rport->utmi_avalid)
10641217 		rport->vbus_attached =
10651218 			property_enabled(rphy->grf, &rport->port_cfg->utmi_avalid);
10661219 	else
....@@ -1082,10 +1235,10 @@
10821235 				rockchip_usb2phy_power_off(rport->phy);
10831236 			mutex_lock(&rport->mutex);
10841237 		}
1085
-		/* fall through */
1238
+		fallthrough;
10861239 	case OTG_STATE_B_IDLE:
10871240 		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0 ||
1088
-		    extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) > 0 ) {
1241
+		    extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) > 0) {
10891242 			dev_dbg(&rport->phy->dev, "usb otg host connect\n");
10901243 			rport->state = OTG_STATE_A_HOST;
10911244 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
....@@ -1139,6 +1292,7 @@
11391292 		} else {
11401293 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
11411294 			rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1295
+			rport->perip_connected = false;
11421296 			mutex_unlock(&rport->mutex);
11431297 			if (!rport->dis_u2_susphy)
11441298 				rockchip_usb2phy_power_off(rport->phy);
....@@ -1370,25 +1524,27 @@
13701524 			rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
13711525 		else
13721526 			rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
1373
-		/* fall through */
1527
+		fallthrough;
13741528 	case USB_CHG_STATE_SECONDARY_DONE:
13751529 		rphy->chg_state = USB_CHG_STATE_DETECTED;
1376
-		/* fall through */
1530
+		fallthrough;
13771531 	case USB_CHG_STATE_DETECTED:
1532
+		if (rphy->phy_cfg->chg_det.chg_mode.offset !=
1533
+		    rport->port_cfg->phy_sus.offset)
1534
+			property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, false);
1535
+
13781536 		/* Restore the PHY suspend configuration */
13791537 		phy_sus_reg = &rport->port_cfg->phy_sus;
13801538 		mask = GENMASK(phy_sus_reg->bitend, phy_sus_reg->bitstart);
13811539 		ret = regmap_write(base, phy_sus_reg->offset,
1382
-				   ((rphy->phy_sus_cfg <<
1383
-				     phy_sus_reg->bitstart) |
1384
-				    (mask << BIT_WRITEABLE_SHIFT)));
1540
+				   (rphy->phy_sus_cfg | (mask << BIT_WRITEABLE_SHIFT)));
13851541 		if (ret)
13861542 			dev_err(&rport->phy->dev,
13871543 				"Fail to set phy_sus reg offset 0x%x, ret %d\n",
13881544 				phy_sus_reg->offset, ret);
13891545 		mutex_unlock(&rport->mutex);
13901546 		rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1391
-		dev_info(&rport->phy->dev, "charger = %s\n",
1547
+		dev_dbg(&rport->phy->dev, "charger = %s\n",
13921548 			 chg_to_string(rphy->chg_type));
13931549 		return;
13941550 	default:
....@@ -1422,14 +1578,13 @@
14221578 	struct rockchip_usb2phy_port *rport =
14231579 		container_of(work, struct rockchip_usb2phy_port, sm_work.work);
14241580 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1425
-	unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
1426
-			  rport->port_cfg->utmi_hstdet.bitstart + 1;
1427
-	unsigned int ul, uhd, state;
1581
+	unsigned int sh, ul, uhd, state;
14281582 	unsigned int ul_mask, uhd_mask;
14291583 	int ret;
14301584 
14311585 	if (!rport->port_cfg->utmi_ls.offset ||
1432
-	    !rport->port_cfg->utmi_hstdet.offset) {
1586
+	    (!rport->port_cfg->utmi_hstdet.offset &&
1587
+	     !rport->port_cfg->disfall_en.offset)) {
14331588 		dev_dbg(&rport->phy->dev, "some property may not be specified\n");
14341589 		return;
14351590 	}
....@@ -1440,18 +1595,26 @@
14401595 	if (ret < 0)
14411596 		goto next_schedule;
14421597 
1443
-	ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
1444
-	if (ret < 0)
1445
-		goto next_schedule;
1446
-
1447
-	uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
1448
-			   rport->port_cfg->utmi_hstdet.bitstart);
14491598 	ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
14501599 			  rport->port_cfg->utmi_ls.bitstart);
14511600 
1452
-	/* stitch on utmi_ls and utmi_hstdet as phy state */
1453
-	state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
1454
-		(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
1601
+	if (rport->port_cfg->utmi_hstdet.offset) {
1602
+		ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
1603
+		if (ret < 0)
1604
+			goto next_schedule;
1605
+
1606
+		uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
1607
+				   rport->port_cfg->utmi_hstdet.bitstart);
1608
+
1609
+		sh = rport->port_cfg->utmi_hstdet.bitend -
1610
+		     rport->port_cfg->utmi_hstdet.bitstart + 1;
1611
+		/* stitch on utmi_ls and utmi_hstdet as phy state */
1612
+		state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
1613
+			(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
1614
+	} else {
1615
+		state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 |
1616
+			rport->host_disconnect;
1617
+	}
14551618 
14561619 	switch (state) {
14571620 	case PHY_STATE_HS_ONLINE:
....@@ -1472,7 +1635,7 @@
14721635 			dev_dbg(&rport->phy->dev, "FS/LS online\n");
14731636 			break;
14741637 		}
1475
-		/* fall through */
1638
+		fallthrough;
14761639 	case PHY_STATE_CONNECT:
14771640 		if (rport->suspended) {
14781641 			dev_dbg(&rport->phy->dev, "Connected\n");
....@@ -1516,7 +1679,7 @@
15161679 		mutex_unlock(&rport->mutex);
15171680 		return;
15181681 	default:
1519
-		dev_dbg(&rport->phy->dev, "unknown phy state\n");
1682
+		dev_dbg(&rport->phy->dev, "unknown phy state %d\n", state);
15201683 		break;
15211684 	}
15221685 
....@@ -1530,7 +1693,8 @@
15301693 	struct rockchip_usb2phy_port *rport = data;
15311694 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
15321695 
1533
-	if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
1696
+	if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st) ||
1697
+	    !property_enabled(rphy->grf, &rport->port_cfg->ls_det_en))
15341698 		return IRQ_NONE;
15351699 
15361700 	dev_dbg(&rport->phy->dev, "linestate interrupt\n");
....@@ -1539,6 +1703,14 @@
15391703 
15401704 	/* disable linestate detect irq and clear its status */
15411705 	rockchip_usb2phy_enable_line_irq(rphy, rport, false);
1706
+
1707
+	/*
1708
+	 * For host port, it may miss disc irq when device is connected,
1709
+	 * in this case, we can clear host_disconnect state depend on
1710
+	 * the linestate irq.
1711
+	 */
1712
+	if (rport->port_id == USB2PHY_PORT_HOST && rport->port_cfg->disfall_en.offset)
1713
+		rport->host_disconnect = false;
15421714 
15431715 	mutex_unlock(&rport->mutex);
15441716 
....@@ -1571,8 +1743,10 @@
15711743 	if (rport->bypass_uart_en)
15721744 		rockchip_usb_bypass_uart(rport, false);
15731745 
1574
-	cancel_delayed_work_sync(&rport->otg_sm_work);
1575
-	rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1746
+	if (rport->otg_sm_work.work.func) {
1747
+		cancel_delayed_work_sync(&rport->otg_sm_work);
1748
+		rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1749
+	}
15761750 
15771751 	return IRQ_HANDLED;
15781752 }
....@@ -1593,7 +1767,13 @@
15931767 	if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st)) {
15941768 		property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr,
15951769 				true);
1596
-		cable_vbus_state = true;
1770
+		/*
1771
+		 * if id fall det, switch to host if ID Detector pin is floating
1772
+		 * or iddig status is low.
1773
+		 */
1774
+		if (!rport->port_cfg->utmi_iddig.enable ||
1775
+		    !property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig))
1776
+			cable_vbus_state = true;
15971777 	} else if (property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) {
15981778 		property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr,
15991779 				true);
....@@ -1607,6 +1787,33 @@
16071787 	extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
16081788 
16091789 	rockchip_set_vbus_power(rport, cable_vbus_state);
1790
+
1791
+	mutex_unlock(&rport->mutex);
1792
+
1793
+	return IRQ_HANDLED;
1794
+}
1795
+
1796
+static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data)
1797
+{
1798
+	struct rockchip_usb2phy_port *rport = data;
1799
+	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1800
+
1801
+	if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
1802
+	    !property_enabled(rphy->grf, &rport->port_cfg->disrise_st))
1803
+		return IRQ_NONE;
1804
+
1805
+	mutex_lock(&rport->mutex);
1806
+
1807
+	/* clear disconnect fall or rise detect irq pending status */
1808
+	if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
1809
+		property_enable(rphy->grf, &rport->port_cfg->disfall_clr,
1810
+				true);
1811
+		rport->host_disconnect = false;
1812
+	} else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
1813
+		property_enable(rphy->grf, &rport->port_cfg->disrise_clr,
1814
+				true);
1815
+		rport->host_disconnect = true;
1816
+	}
16101817 
16111818 	mutex_unlock(&rport->mutex);
16121819 
....@@ -1637,8 +1844,16 @@
16371844 		if (!rport->phy)
16381845 			continue;
16391846 
1847
+		/*
1848
+		 * Handle disc irq before linestate irq to set the disc
1849
+		 * state for sm work scheduled in the linestate irq handler.
1850
+		 */
1851
+		if (rport->port_id == USB2PHY_PORT_HOST &&
1852
+		    rport->port_cfg->disfall_en.offset)
1853
+			ret |= rockchip_usb2phy_host_disc_irq(irq, rport);
1854
+
16401855 		/* Handle linestate irq for both otg port and host port */
1641
-		ret = rockchip_usb2phy_linestate_irq(irq, rport);
1856
+		ret |= rockchip_usb2phy_linestate_irq(irq, rport);
16421857 
16431858 		/*
16441859 		 * Handle bvalid irq and id irq for otg port which
....@@ -1777,6 +1992,61 @@
17771992 	return ret;
17781993 }
17791994 
1995
+static void rockchip_usb2phy_usb_bvalid_enable(struct rockchip_usb2phy_port *rport,
1996
+					       u8 enable)
1997
+{
1998
+	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1999
+	const struct rockchip_usb2phy_port_cfg *cfg = rport->port_cfg;
2000
+
2001
+	if (cfg->bvalid_phy_con.enable)
2002
+		property_enable(rphy->grf, &cfg->bvalid_phy_con, enable);
2003
+
2004
+	if (cfg->bvalid_grf_con.enable)
2005
+		property_enable(rphy->grf, &cfg->bvalid_grf_con, enable);
2006
+}
2007
+
2008
+static int rockchip_usb2phy_orien_sw_set(struct typec_switch *sw,
2009
+					 enum typec_orientation orien)
2010
+{
2011
+	struct rockchip_usb2phy_port *rport = typec_switch_get_drvdata(sw);
2012
+
2013
+	dev_dbg(&rport->phy->dev, "type-c orientation: %d\n", orien);
2014
+
2015
+	mutex_lock(&rport->mutex);
2016
+	rockchip_usb2phy_usb_bvalid_enable(rport, orien != TYPEC_ORIENTATION_NONE);
2017
+	mutex_unlock(&rport->mutex);
2018
+
2019
+	return 0;
2020
+}
2021
+
2022
+static int
2023
+rockchip_usb2phy_setup_orien_switch(struct rockchip_usb2phy *rphy,
2024
+				    struct rockchip_usb2phy_port *rport)
2025
+{
2026
+	struct typec_switch_desc sw_desc = { };
2027
+	struct device *dev = rphy->dev;
2028
+
2029
+	sw_desc.drvdata = rport;
2030
+	sw_desc.fwnode = dev_fwnode(dev);
2031
+	sw_desc.set = rockchip_usb2phy_orien_sw_set;
2032
+
2033
+	rport->sw = typec_switch_register(dev, &sw_desc);
2034
+	if (IS_ERR(rport->sw)) {
2035
+		dev_err(dev, "Error register typec orientation switch: %ld\n",
2036
+			PTR_ERR(rport->sw));
2037
+		return PTR_ERR(rport->sw);
2038
+	}
2039
+
2040
+	return 0;
2041
+}
2042
+
2043
+static void rockchip_usb2phy_orien_switch_unregister(void *data)
2044
+{
2045
+	struct rockchip_usb2phy_port *rport = data;
2046
+
2047
+	typec_switch_unregister(rport->sw);
2048
+}
2049
+
17802050 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
17812051 					   struct rockchip_usb2phy_port *rport,
17822052 					   struct device_node *child_np)
....@@ -1861,6 +2131,23 @@
18612131 	rport->low_power_en =
18622132 		of_property_read_bool(child_np, "rockchip,low-power-mode");
18632133 
2134
+	/* For type-c with vbus_det always pull up */
2135
+	rport->typec_vbus_det =
2136
+		of_property_read_bool(child_np, "rockchip,typec-vbus-det");
2137
+
2138
+	rport->sel_pipe_phystatus =
2139
+		of_property_read_bool(child_np, "rockchip,sel-pipe-phystatus");
2140
+
2141
+	if (rport->sel_pipe_phystatus) {
2142
+		rphy->usbctrl_grf =
2143
+			syscon_regmap_lookup_by_phandle(rphy->dev->of_node,
2144
+							"rockchip,usbctrl-grf");
2145
+		if (IS_ERR(rphy->usbctrl_grf)) {
2146
+			dev_err(rphy->dev, "Failed to map usbctrl-grf\n");
2147
+			return PTR_ERR(rphy->usbctrl_grf);
2148
+		}
2149
+	}
2150
+
18642151 	/* Get Vbus regulators */
18652152 	rport->vbus = devm_regulator_get_optional(&rport->phy->dev, "vbus");
18662153 	if (IS_ERR(rport->vbus)) {
....@@ -1868,7 +2155,8 @@
18682155 		if (ret == -EPROBE_DEFER)
18692156 			return ret;
18702157 
1871
-		dev_warn(&rport->phy->dev, "No vbus specified for otg port\n");
2158
+		if (rport->mode == USB_DR_MODE_OTG)
2159
+			dev_warn(&rport->phy->dev, "No vbus specified for otg port\n");
18722160 		rport->vbus = NULL;
18732161 	}
18742162 
....@@ -1891,13 +2179,42 @@
18912179 		return ret;
18922180 	}
18932181 
2182
+	if (IS_REACHABLE(CONFIG_TYPEC) &&
2183
+	    device_property_present(rphy->dev, "orientation-switch")) {
2184
+		ret = rockchip_usb2phy_setup_orien_switch(rphy, rport);
2185
+		if (ret)
2186
+			return ret;
2187
+
2188
+		ret = devm_add_action_or_reset(rphy->dev,
2189
+					       rockchip_usb2phy_orien_switch_unregister,
2190
+					       rport);
2191
+		if (ret)
2192
+			return ret;
2193
+	}
2194
+
2195
+	/*
2196
+	 * Set the utmi bvalid come from the usb phy or grf.
2197
+	 * For most of Rockchip SoCs, them have VBUSDET pin
2198
+	 * for the usb phy to detect the USB VBUS and set
2199
+	 * the bvalid signal, so select the bvalid from the
2200
+	 * usb phy by default. And for those SoCs which don't
2201
+	 * have VBUSDET pin (e.g. RV1103), it needs to select
2202
+	 * the bvaid from the grf and set bvalid to be valid
2203
+	 * (high) by default.
2204
+	 */
2205
+	if (rport->port_cfg->bvalid_grf_sel.enable != 0) {
2206
+		if (of_machine_is_compatible("rockchip,rv1103"))
2207
+			property_enable(base, &rport->port_cfg->bvalid_grf_sel, true);
2208
+		else
2209
+			property_enable(base, &rport->port_cfg->bvalid_grf_sel, false);
2210
+	}
2211
+
2212
+	if (rport->vbus_always_on)
2213
+		extcon_set_state(rphy->edev, EXTCON_USB, true);
2214
+
18942215 	if (rport->vbus_always_on || rport->mode == USB_DR_MODE_HOST ||
18952216 	    rport->mode == USB_DR_MODE_UNKNOWN)
18962217 		goto out;
1897
-
1898
-	/* Select bvalid of usb phy as bvalid of usb controller */
1899
-	if (rport->port_cfg->bvalid_set.enable != 0)
1900
-		property_enable(base, &rport->port_cfg->bvalid_set, false);
19012218 
19022219 	wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
19032220 	ret = devm_add_action_or_reset(rphy->dev, rockchip_otg_wake_lock_destroy,
....@@ -2012,24 +2329,29 @@
20122329 
20132330 	/* find out a proper config which can be matched with dt. */
20142331 	index = 0;
2015
-	while (phy_cfgs[index].reg) {
2332
+	do {
20162333 		if (phy_cfgs[index].reg == reg) {
20172334 			rphy->phy_cfg = &phy_cfgs[index];
20182335 			break;
20192336 		}
20202337 
20212338 		++index;
2022
-	}
2339
+	} while (phy_cfgs[index].reg);
20232340 
20242341 	if (!rphy->phy_cfg) {
2025
-		dev_err(dev, "no phy-config can be matched with %s node\n",
2026
-			np->name);
2342
+		dev_err(dev, "no phy-config can be matched with %pOFn node\n",
2343
+			np);
20272344 		return -EINVAL;
20282345 	}
20292346 
20302347 	pm_runtime_set_active(dev);
20312348 	pm_runtime_enable(dev);
20322349 	pm_runtime_get_sync(dev);
2350
+
2351
+
2352
+	rphy->phy_reset = devm_reset_control_get_optional(dev, "phy");
2353
+	if (IS_ERR(rphy->phy_reset))
2354
+		return PTR_ERR(rphy->phy_reset);
20332355 
20342356 	ret = devm_clk_bulk_get_all(dev, &rphy->clks);
20352357 	if (ret == -EPROBE_DEFER)
....@@ -2057,8 +2379,8 @@
20572379 		struct phy *phy;
20582380 
20592381 		/* This driver aims to support both otg-port and host-port */
2060
-		if (of_node_cmp(child_np->name, "host-port") &&
2061
-		    of_node_cmp(child_np->name, "otg-port"))
2382
+		if (!of_node_name_eq(child_np, "host-port") &&
2383
+		    !of_node_name_eq(child_np, "otg-port"))
20622384 			goto next_child;
20632385 
20642386 		phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
....@@ -2072,7 +2394,7 @@
20722394 		phy_set_drvdata(rport->phy, rport);
20732395 
20742396 		/* initialize otg/host port separately */
2075
-		if (!of_node_cmp(child_np->name, "host-port")) {
2397
+		if (of_node_name_eq(child_np, "host-port")) {
20762398 			ret = rockchip_usb2phy_host_port_init(rphy, rport,
20772399 							      child_np);
20782400 			if (ret)
....@@ -2136,7 +2458,6 @@
21362458 	pm_runtime_put_sync(dev);
21372459 	pm_runtime_disable(dev);
21382460 	clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
2139
-
21402461 	return ret;
21412462 }
21422463 
....@@ -2203,20 +2524,55 @@
22032524 {
22042525 	int ret;
22052526 
2206
-	/* Open pre-emphasize in non-chirp state for otg port */
2207
-	ret = regmap_write(rphy->grf, 0x0, 0x00070004);
2208
-	if (ret)
2209
-		return ret;
2527
+	if (soc_is_rk3308bs()) {
2528
+		/* Turn off differential receiver in suspend mode */
2529
+		ret = regmap_update_bits(rphy->grf, 0x30, BIT(2), 0);
2530
+		if (ret)
2531
+			return ret;
22102532 
2211
-	/* Open pre-emphasize in non-chirp state for host port */
2212
-	ret = regmap_write(rphy->grf, 0x30, 0x00070004);
2213
-	if (ret)
2214
-		return ret;
2533
+		/* Enable otg port pre-emphasis during non-chirp phase */
2534
+		ret = regmap_update_bits(rphy->grf, 0, GENMASK(2, 0), BIT(2));
2535
+		if (ret)
2536
+			return ret;
22152537 
2216
-	/* Turn off differential receiver in suspend mode */
2217
-	ret = regmap_write(rphy->grf, 0x18, 0x00040000);
2218
-	if (ret)
2219
-		return ret;
2538
+		/* Set otg port squelch trigger point configure to 100mv */
2539
+		ret = regmap_update_bits(rphy->grf, 0x004, GENMASK(7, 5), 0x40);
2540
+		if (ret)
2541
+			return ret;
2542
+
2543
+		ret = regmap_update_bits(rphy->grf, 0x008, BIT(0), 0x1);
2544
+		if (ret)
2545
+			return ret;
2546
+
2547
+		/* Enable host port pre-emphasis during non-chirp phase */
2548
+		ret = regmap_update_bits(rphy->grf, 0x400, GENMASK(2, 0), BIT(2));
2549
+		if (ret)
2550
+			return ret;
2551
+
2552
+		/* Set host port squelch trigger point configure to 100mv */
2553
+		ret = regmap_update_bits(rphy->grf, 0x404, GENMASK(7, 5), 0x40);
2554
+		if (ret)
2555
+			return ret;
2556
+
2557
+		ret = regmap_update_bits(rphy->grf, 0x408, BIT(0), 0x1);
2558
+		if (ret)
2559
+			return ret;
2560
+	} else {
2561
+		/* Open pre-emphasize in non-chirp state for otg port */
2562
+		ret = regmap_write(rphy->grf, 0x0, 0x00070004);
2563
+		if (ret)
2564
+			return ret;
2565
+
2566
+		/* Open pre-emphasize in non-chirp state for host port */
2567
+		ret = regmap_write(rphy->grf, 0x30, 0x00070004);
2568
+		if (ret)
2569
+			return ret;
2570
+
2571
+		/* Turn off differential receiver in suspend mode */
2572
+		ret = regmap_write(rphy->grf, 0x18, 0x00040000);
2573
+		if (ret)
2574
+			return ret;
2575
+	}
22202576 
22212577 	return 0;
22222578 }
....@@ -2379,34 +2735,22 @@
23792735 
23802736 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
23812737 {
2382
-	u32 reg;
23832738 	int ret = 0;
23842739 
23852740 	/* Turn off otg port differential receiver in suspend mode */
2386
-	reg = readl(rphy->phy_base + 0x30);
2387
-	writel(reg & ~BIT(2), rphy->phy_base + 0x30);
2741
+	phy_clear_bits(rphy->phy_base + 0x30, BIT(2));
23882742 
23892743 	/* Turn off host port differential receiver in suspend mode */
2390
-	reg = readl(rphy->phy_base + 0x0430);
2391
-	writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
2744
+	phy_clear_bits(rphy->phy_base + 0x430, BIT(2));
23922745 
23932746 	/* Set otg port HS eye height to 400mv(default is 450mv) */
2394
-	reg = readl(rphy->phy_base + 0x30);
2395
-	reg &= ~GENMASK(6, 4);
2396
-	reg |= (0x00 << 4);
2397
-	writel(reg, rphy->phy_base + 0x30);
2747
+	phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x00 << 4));
23982748 
23992749 	/* Set host port HS eye height to 400mv(default is 450mv) */
2400
-	reg = readl(rphy->phy_base + 0x430);
2401
-	reg &= ~GENMASK(6, 4);
2402
-	reg |= (0x00 << 4);
2403
-	writel(reg, rphy->phy_base + 0x430);
2750
+	phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x00 << 4));
24042751 
24052752 	/* Choose the Tx fs/ls data as linestate from TX driver for otg port */
2406
-	reg = readl(rphy->phy_base + 0x94);
2407
-	reg &= ~GENMASK(6, 3);
2408
-	reg |= (0x03 << 3);
2409
-	writel(reg, rphy->phy_base + 0x94);
2753
+	phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3));
24102754 
24112755 	/* Enable otg and host ports phy irq to pmu wakeup source */
24122756 	ret |= regmap_write(rphy->grf, 0x80004, 0x00030003);
....@@ -2414,33 +2758,50 @@
24142758 	return ret;
24152759 }
24162760 
2417
-static int rk3568_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2761
+static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
24182762 {
2419
-	u32 reg;
24202763 	int ret = 0;
24212764 
2422
-	reg = readl(rphy->phy_base + 0x30);
2423
-	/* turn off differential reciver in suspend mode */
2424
-	writel(reg & ~BIT(2), rphy->phy_base + 0x30);
2765
+	/* Turn off differential receiver by default to save power */
2766
+	phy_clear_bits(rphy->phy_base + 0x0030, BIT(2));
2767
+	phy_clear_bits(rphy->phy_base + 0x0430, BIT(2));
24252768 
2426
-	reg = readl(rphy->phy_base);
2769
+	/* Enable pre-emphasis during non-chirp phase */
2770
+	phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04);
2771
+	phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04);
2772
+
2773
+	/* Set HS eye height to 425mv(default is 400mv) */
2774
+	phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4));
2775
+	phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4));
2776
+
2777
+	/* Set the bvalid filter time to 10ms based on the u2phy grf pclk 100MHz */
2778
+	ret |= regmap_write(rphy->grf, 0x0138, FILTER_COUNTER);
2779
+
2780
+	/* Set the id filter time to 10ms based on the u2phy grf pclk 100MHz */
2781
+	ret |= regmap_write(rphy->grf, 0x013c, FILTER_COUNTER);
2782
+
2783
+	/* Enable host port wakeup irq */
2784
+	ret |= regmap_write(rphy->grf, 0x010c, 0x80008000);
2785
+
2786
+	return ret;
2787
+}
2788
+
2789
+static int rk3568_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2790
+{
2791
+	int ret = 0;
2792
+
2793
+	/* Turn off differential receiver by default to save power */
2794
+	phy_clear_bits(rphy->phy_base + 0x30, BIT(2));
2795
+
24272796 	/* Enable otg port pre-emphasis during non-chirp phase */
2428
-	reg &= ~(0x07 << 0);
2429
-	reg |= (0x04 << 0);
2430
-	writel(reg, rphy->phy_base);
2797
+	phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04);
24312798 
2432
-	reg = readl(rphy->phy_base + 0x0400);
24332799 	/* Enable host port pre-emphasis during non-chirp phase */
2434
-	reg &= ~(0x07 << 0);
2435
-	reg |= (0x04 << 0);
2436
-	writel(reg, rphy->phy_base + 0x0400);
2800
+	phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04);
24372801 
24382802 	if (rphy->phy_cfg->reg == 0xfe8a0000) {
24392803 		/* Set otg port HS eye height to 437.5mv(default is 400mv) */
2440
-		reg = readl(rphy->phy_base + 0x30);
2441
-		reg &= ~(0x07 << 4);
2442
-		reg |= (0x06 << 4);
2443
-		writel(reg, rphy->phy_base + 0x30);
2804
+		phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x06 << 4));
24442805 
24452806 		/*
24462807 		 * Set the bvalid filter time to 10ms
....@@ -2461,23 +2822,158 @@
24612822 	return ret;
24622823 }
24632824 
2825
+static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2826
+{
2827
+	/* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */
2828
+	phy_update_bits(rphy->phy_base + 0x30, GENMASK(2, 0), 0x07);
2829
+
2830
+	if (rockchip_get_cpu_version()) {
2831
+		/* Set Tx HS pre_emphasize strength to 3'b001 */
2832
+		phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x01 << 3));
2833
+	} else {
2834
+		/* Set Tx HS pre_emphasize strength to 3'b011 */
2835
+		phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x03 << 3));
2836
+	}
2837
+
2838
+	/* Set RX Squelch trigger point configure to 4'b0000(112.5 mV) */
2839
+	phy_update_bits(rphy->phy_base + 0x64, GENMASK(6, 3), (0x00 << 3));
2840
+
2841
+	/* Turn off differential receiver by default to save power */
2842
+	phy_clear_bits(rphy->phy_base + 0x100, BIT(6));
2843
+
2844
+	/* Set 45ohm HS ODT value to 5'b10111 to increase driver strength */
2845
+	phy_update_bits(rphy->phy_base + 0x11c, GENMASK(4, 0), 0x17);
2846
+
2847
+	/* Set Tx HS eye height tuning to 3'b011(462 mV)*/
2848
+	phy_update_bits(rphy->phy_base + 0x124, GENMASK(4, 2), (0x03 << 2));
2849
+
2850
+	/* Bypass Squelch detector calibration */
2851
+	phy_update_bits(rphy->phy_base + 0x1a4, GENMASK(7, 4), (0x01 << 4));
2852
+	phy_update_bits(rphy->phy_base + 0x1b4, GENMASK(7, 4), (0x01 << 4));
2853
+
2854
+	/* Set HS disconnect detect mode to single ended detect mode */
2855
+	phy_set_bits(rphy->phy_base + 0x70, BIT(2));
2856
+
2857
+	return 0;
2858
+}
2859
+
24642860 static int rockchip_usb2phy_vbus_det_control(struct rockchip_usb2phy *rphy,
24652861 					     const struct usb2phy_reg *vbus_det_en,
24662862 					     bool en)
24672863 {
2468
-	u32 reg;
2469
-
24702864 	if (en) {
2471
-		reg = readl(rphy->phy_base + vbus_det_en->offset);
24722865 		/* Enable vbus voltage level detection function */
2473
-		writel(reg & ~BIT(7), rphy->phy_base + vbus_det_en->offset);
2866
+		phy_clear_bits(rphy->phy_base + vbus_det_en->offset, BIT(7));
24742867 	} else {
2475
-		reg = readl(rphy->phy_base + vbus_det_en->offset);
24762868 		/* Disable vbus voltage level detection function */
2477
-		writel(reg | BIT(7), rphy->phy_base + vbus_det_en->offset);
2869
+		phy_set_bits(rphy->phy_base + vbus_det_en->offset, BIT(7));
24782870 	}
24792871 
24802872 	return 0;
2873
+}
2874
+
2875
+static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2876
+{
2877
+	unsigned int reg;
2878
+	int ret = 0;
2879
+
2880
+	/* Read the SIDDQ control register */
2881
+	ret = regmap_read(rphy->grf, 0x0008, &reg);
2882
+	if (ret)
2883
+		return ret;
2884
+
2885
+	if (reg & BIT(13)) {
2886
+		/* Deassert SIDDQ to power on analog block */
2887
+		ret = regmap_write(rphy->grf, 0x0008,
2888
+				   GENMASK(29, 29) | 0x0000);
2889
+		if (ret)
2890
+			return ret;
2891
+
2892
+		/* Do reset after exit IDDQ mode */
2893
+		ret = rockchip_usb2phy_reset(rphy);
2894
+		if (ret)
2895
+			return ret;
2896
+	}
2897
+
2898
+	if (rphy->phy_cfg->reg == 0x0000) {
2899
+		/*
2900
+		 * Set USB2 PHY0 suspend configuration for USB3_0
2901
+		 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2902
+		 * 2. Set utmi_xcvrselect to 2'b01 (FS transceiver)
2903
+		 * 3. Set utmi_opmode to 2'b01 (no-driving)
2904
+		 */
2905
+		ret |= regmap_write(rphy->grf, 0x000c,
2906
+				    GENMASK(20, 16) | 0x0015);
2907
+
2908
+		/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2909
+		ret |= regmap_write(rphy->grf, 0x0004,
2910
+				   GENMASK(27, 24) | 0x0900);
2911
+
2912
+		/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2913
+		ret |= regmap_write(rphy->grf, 0x0008,
2914
+				   GENMASK(20, 19) | 0x0010);
2915
+
2916
+		/* Pullup iddig pin for USB3_0 OTG mode */
2917
+		ret |= regmap_write(rphy->grf, 0x0010,
2918
+				    GENMASK(17, 16) | 0x0003);
2919
+	} else if (rphy->phy_cfg->reg == 0x4000) {
2920
+		/*
2921
+		 * Set USB2 PHY1 suspend configuration for USB3_1
2922
+		 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2923
+		 * 2. Set utmi_xcvrselect to 2'b01(FS transceiver)
2924
+		 * 3. Set utmi_opmode to 2'b01 (no-driving)
2925
+		 */
2926
+		ret |= regmap_write(rphy->grf, 0x000c,
2927
+				    GENMASK(20, 16) | 0x0015);
2928
+
2929
+		/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2930
+		ret |= regmap_write(rphy->grf, 0x0004,
2931
+				   GENMASK(27, 24) | 0x0900);
2932
+
2933
+		/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2934
+		ret |= regmap_write(rphy->grf, 0x0008,
2935
+				   GENMASK(20, 19) | 0x0010);
2936
+
2937
+		/* Pullup iddig pin for USB3_1 OTG mode */
2938
+		ret |= regmap_write(rphy->grf, 0x0010,
2939
+				    GENMASK(17, 16) | 0x0003);
2940
+	} else if (rphy->phy_cfg->reg == 0x8000) {
2941
+		/*
2942
+		 * Set USB2 PHY2 suspend configuration for USB2_0
2943
+		 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2944
+		 * 2. Set utmi_xcvrselect to 2'b01(FS transceiver)
2945
+		 * 3. Set utmi_opmode to 2'b00 (normal)
2946
+		 */
2947
+		ret |= regmap_write(rphy->grf, 0x000c,
2948
+				    GENMASK(20, 16) | 0x0014);
2949
+
2950
+		/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2951
+		ret |= regmap_write(rphy->grf, 0x0004,
2952
+				   GENMASK(27, 24) | 0x0900);
2953
+
2954
+		/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2955
+		ret |= regmap_write(rphy->grf, 0x0008,
2956
+				   GENMASK(20, 19) | 0x0010);
2957
+	} else if (rphy->phy_cfg->reg == 0xc000) {
2958
+		/*
2959
+		 * Set USB2 PHY3 suspend configuration for USB2_1
2960
+		 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2961
+		 * 2. Set utmi_xcvrselect to 2'b01(FS transceiver)
2962
+		 * 3. Set utmi_opmode to 2'b00 (normal)
2963
+		 */
2964
+		ret |= regmap_write(rphy->grf, 0x000c,
2965
+				    GENMASK(20, 16) | 0x0014);
2966
+
2967
+		/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2968
+		ret |= regmap_write(rphy->grf, 0x0004,
2969
+				   GENMASK(27, 24) | 0x0900);
2970
+
2971
+		/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2972
+		ret |= regmap_write(rphy->grf, 0x0008,
2973
+				   GENMASK(20, 19) | 0x0010);
2974
+	}
2975
+
2976
+	return ret;
24812977 }
24822978 
24832979 #ifdef CONFIG_PM_SLEEP
....@@ -2571,6 +3067,13 @@
25713067 	if (device_may_wakeup(rphy->dev))
25723068 		wakeup_enable = true;
25733069 
3070
+	/*
3071
+	 * PHY lost power in suspend, it needs to reset
3072
+	 * PHY to recovery clock to usb controller.
3073
+	 */
3074
+	if (!wakeup_enable)
3075
+		rockchip_usb2phy_reset(rphy);
3076
+
25743077 	if (phy_cfg->phy_tuning)
25753078 		ret = phy_cfg->phy_tuning(rphy);
25763079 
....@@ -2622,6 +3125,26 @@
26223125 				if (ret)
26233126 					return ret;
26243127 			}
3128
+		}
3129
+
3130
+		/* Enable bvalid detect irq */
3131
+		if (rport->port_id == USB2PHY_PORT_OTG &&
3132
+		    (rport->mode == USB_DR_MODE_PERIPHERAL ||
3133
+		     rport->mode == USB_DR_MODE_OTG) &&
3134
+		    (rport->bvalid_irq > 0 || rport->otg_mux_irq > 0 || rphy->irq > 0) &&
3135
+		    !rport->vbus_always_on) {
3136
+			ret = rockchip_usb2phy_enable_vbus_irq(rphy, rport,
3137
+							       true);
3138
+			if (ret) {
3139
+				dev_err(rphy->dev,
3140
+					"failed to enable bvalid irq\n");
3141
+				return ret;
3142
+			}
3143
+
3144
+			if (property_enabled(rphy->grf, &rport->port_cfg->utmi_bvalid))
3145
+				schedule_delayed_work(&rport->otg_sm_work,
3146
+						      OTG_SCHEDULE_DELAY);
3147
+
26253148 		}
26263149 
26273150 		if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable &&
....@@ -2909,7 +3432,6 @@
29093432 				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
29103433 				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
29113434 				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
2912
-				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
29133435 				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
29143436 				.vbus_det_en	= { 0x001c, 15, 15, 1, 0 },
29153437 			},
....@@ -2987,7 +3509,7 @@
29873509 				.vbus_det_en    = { 0x079c, 15, 15, 1, 0 },
29883510 			},
29893511 			[USB2PHY_PORT_HOST] = {
2990
-				.phy_sus	= { 0x0728, 8, 0, 0, 0x1d1 },
3512
+				.phy_sus	= { 0x0728, 15, 0, 0, 0x1d1 },
29913513 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
29923514 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
29933515 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
....@@ -3128,7 +3650,6 @@
31283650 				.bvalid_det_en	= { 0x60074, 2, 2, 0, 1 },
31293651 				.bvalid_det_st	= { 0x60078, 2, 2, 0, 1 },
31303652 				.bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
3131
-				.bvalid_set	= { 0x6004c, 15, 14, 0, 3 },
31323653 				.iddig_output	= { 0x6004c, 10, 10, 0, 1 },
31333654 				.iddig_en	= { 0x6004c, 9, 9, 0, 1 },
31343655 				.idfall_det_en	= { 0x60074, 5, 5, 0, 1 },
....@@ -3172,6 +3693,65 @@
31723693 	}
31733694 };
31743695 
3696
+static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
3697
+	{
3698
+		.reg = 0xff740000,
3699
+		.num_ports	= 2,
3700
+		.phy_tuning	= rk3562_usb2phy_tuning,
3701
+		.vbus_detect	= rockchip_usb2phy_vbus_det_control,
3702
+		.clkout_ctl	= { 0x0108, 4, 4, 1, 0 },
3703
+		.ls_filter_con	= { 0x0130, 19, 0, 0x30100, 0x00020 },
3704
+		.port_cfgs	= {
3705
+			[USB2PHY_PORT_OTG] = {
3706
+				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
3707
+				.bvalid_det_en	= { 0x0110, 2, 2, 0, 1 },
3708
+				.bvalid_det_st	= { 0x0114, 2, 2, 0, 1 },
3709
+				.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
3710
+				.bvalid_grf_sel	= { 0x0108, 15, 14, 0, 3 },
3711
+				.bypass_dm_en	= { 0x0108, 2, 2, 0, 1},
3712
+				.bypass_sel	= { 0x0108, 3, 3, 0, 1},
3713
+				.iddig_output	= { 0x0100, 10, 10, 0, 1 },
3714
+				.iddig_en	= { 0x0100, 9, 9, 0, 1 },
3715
+				.idfall_det_en	= { 0x0110, 5, 5, 0, 1 },
3716
+				.idfall_det_st	= { 0x0114, 5, 5, 0, 1 },
3717
+				.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
3718
+				.idrise_det_en	= { 0x0110, 4, 4, 0, 1 },
3719
+				.idrise_det_st	= { 0x0114, 4, 4, 0, 1 },
3720
+				.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
3721
+				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
3722
+				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
3723
+				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
3724
+				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
3725
+				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
3726
+				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
3727
+				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
3728
+				.vbus_det_en	= { 0x003c, 7, 7, 0, 1 },
3729
+			},
3730
+			[USB2PHY_PORT_HOST] = {
3731
+				.phy_sus	= { 0x0104, 8, 0, 0x1d2, 0x1d1 },
3732
+				.ls_det_en	= { 0x0110, 1, 1, 0, 1 },
3733
+				.ls_det_st	= { 0x0114, 1, 1, 0, 1 },
3734
+				.ls_det_clr	= { 0x0118, 1, 1, 0, 1 },
3735
+				.utmi_ls	= { 0x0120, 17, 16, 0, 1 },
3736
+				.utmi_hstdet	= { 0x0120, 19, 19, 0, 1 }
3737
+			}
3738
+		},
3739
+		.chg_det = {
3740
+			.chg_mode	= { 0x0100, 8, 0, 0, 0x1d7 },
3741
+			.cp_det		= { 0x0120, 24, 24, 0, 1 },
3742
+			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
3743
+			.dp_det		= { 0x0120, 25, 25, 0, 1 },
3744
+			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
3745
+			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
3746
+			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
3747
+			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
3748
+			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
3749
+			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
3750
+		},
3751
+	},
3752
+	{ /* sentinel */ }
3753
+};
3754
+
31753755 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
31763756 	{
31773757 		.reg = 0xfe8a0000,
....@@ -3186,7 +3766,7 @@
31863766 				.bvalid_det_en	= { 0x0080, 2, 2, 0, 1 },
31873767 				.bvalid_det_st	= { 0x0084, 2, 2, 0, 1 },
31883768 				.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
3189
-				.bvalid_set	= { 0x0008, 15, 14, 0, 3 },
3769
+				.bvalid_grf_sel	= { 0x0008, 15, 14, 0, 3 },
31903770 				.bypass_dm_en	= { 0x0008, 2, 2, 0, 1},
31913771 				.bypass_sel	= { 0x0008, 3, 3, 0, 1},
31923772 				.iddig_output	= { 0x0000, 10, 10, 0, 1 },
....@@ -3257,6 +3837,208 @@
32573837 	{ /* sentinel */ }
32583838 };
32593839 
3840
+static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
3841
+	{
3842
+		.reg = 0x0000,
3843
+		.num_ports	= 1,
3844
+		.phy_tuning	= rk3588_usb2phy_tuning,
3845
+		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
3846
+		.ls_filter_con	= { 0x0040, 19, 0, 0x30100, 0x00020 },
3847
+		.port_cfgs	= {
3848
+			[USB2PHY_PORT_OTG] = {
3849
+				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
3850
+				.pipe_phystatus	= { 0x001c, 3, 2, 0, 2 },
3851
+				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
3852
+				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
3853
+				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
3854
+				.bvalid_grf_sel	= { 0x0010, 3, 3, 0, 1 },
3855
+				.bvalid_grf_con	= { 0x0010, 3, 2, 2, 3 },
3856
+				.bvalid_phy_con	= { 0x0008, 1, 0, 2, 3 },
3857
+				.bypass_dm_en	= { 0x000c, 5, 5, 0, 1 },
3858
+				.bypass_sel	= { 0x000c, 6, 6, 0, 1 },
3859
+				.iddig_output	= { 0x0010, 0, 0, 0, 1 },
3860
+				.iddig_en	= { 0x0010, 1, 1, 0, 1 },
3861
+				.idfall_det_en	= { 0x0080, 4, 4, 0, 1 },
3862
+				.idfall_det_st	= { 0x0084, 4, 4, 0, 1 },
3863
+				.idfall_det_clr = { 0x0088, 4, 4, 0, 1 },
3864
+				.idrise_det_en	= { 0x0080, 3, 3, 0, 1 },
3865
+				.idrise_det_st	= { 0x0084, 3, 3, 0, 1 },
3866
+				.idrise_det_clr = { 0x0088, 3, 3, 0, 1 },
3867
+				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
3868
+				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
3869
+				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
3870
+				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
3871
+				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
3872
+				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
3873
+				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
3874
+				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
3875
+				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
3876
+				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
3877
+				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
3878
+				.utmi_iddig	= { 0x00c0, 5, 5, 0, 1 },
3879
+				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
3880
+			}
3881
+		},
3882
+		.chg_det = {
3883
+			.chg_mode	= { 0x0008, 2, 2, 0, 1 },
3884
+			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
3885
+			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
3886
+			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
3887
+			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
3888
+			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
3889
+			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
3890
+			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
3891
+			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
3892
+			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
3893
+		},
3894
+	},
3895
+	{
3896
+		.reg = 0x4000,
3897
+		.num_ports	= 1,
3898
+		.phy_tuning	= rk3588_usb2phy_tuning,
3899
+		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
3900
+		.ls_filter_con	= { 0x0040, 19, 0, 0x30100, 0x00020 },
3901
+		.port_cfgs	= {
3902
+			[USB2PHY_PORT_OTG] = {
3903
+				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
3904
+				.pipe_phystatus	= { 0x0034, 3, 2, 0, 2 },
3905
+				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
3906
+				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
3907
+				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
3908
+				.bvalid_grf_sel	= { 0x0010, 3, 3, 0, 1 },
3909
+				.bvalid_grf_con	= { 0x0010, 3, 2, 2, 3 },
3910
+				.bvalid_phy_con = { 0x0008, 1, 0, 2, 3 },
3911
+				.bypass_dm_en	= { 0x000c, 5, 5, 0, 1 },
3912
+				.bypass_sel	= { 0x000c, 6, 6, 0, 1 },
3913
+				.iddig_output	= { 0x0010, 0, 0, 0, 1 },
3914
+				.iddig_en	= { 0x0010, 1, 1, 0, 1 },
3915
+				.idfall_det_en	= { 0x0080, 4, 4, 0, 1 },
3916
+				.idfall_det_st	= { 0x0084, 4, 4, 0, 1 },
3917
+				.idfall_det_clr = { 0x0088, 4, 4, 0, 1 },
3918
+				.idrise_det_en	= { 0x0080, 3, 3, 0, 1 },
3919
+				.idrise_det_st	= { 0x0084, 3, 3, 0, 1 },
3920
+				.idrise_det_clr = { 0x0088, 3, 3, 0, 1 },
3921
+				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
3922
+				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
3923
+				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
3924
+				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
3925
+				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
3926
+				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
3927
+				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
3928
+				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
3929
+				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
3930
+				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
3931
+				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
3932
+				.utmi_iddig	= { 0x00c0, 5, 5, 0, 1 },
3933
+				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
3934
+			}
3935
+		},
3936
+		.chg_det = {
3937
+			.chg_mode	= { 0x0008, 2, 2, 0, 1 },
3938
+			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
3939
+			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
3940
+			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
3941
+			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
3942
+			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
3943
+			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
3944
+			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
3945
+			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
3946
+			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
3947
+		},
3948
+	},
3949
+	{
3950
+		.reg = 0x8000,
3951
+		.num_ports	= 1,
3952
+		.phy_tuning	= rk3588_usb2phy_tuning,
3953
+		.clkout_ctl	= { 0x0000, 0, 0, 0, 0 },
3954
+		.ls_filter_con	= { 0x0040, 19, 0, 0x30100, 0x00020 },
3955
+		.port_cfgs	= {
3956
+			[USB2PHY_PORT_HOST] = {
3957
+				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
3958
+				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
3959
+				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
3960
+				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
3961
+				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
3962
+				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
3963
+				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
3964
+				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
3965
+				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
3966
+				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
3967
+				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
3968
+			}
3969
+		},
3970
+	},
3971
+	{
3972
+		.reg = 0xc000,
3973
+		.num_ports	= 1,
3974
+		.phy_tuning	= rk3588_usb2phy_tuning,
3975
+		.clkout_ctl	= { 0x0000, 0, 0, 0, 0 },
3976
+		.ls_filter_con	= { 0x0040, 19, 0, 0x30100, 0x00020 },
3977
+		.port_cfgs	= {
3978
+			[USB2PHY_PORT_HOST] = {
3979
+				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
3980
+				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
3981
+				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
3982
+				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
3983
+				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
3984
+				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
3985
+				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
3986
+				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
3987
+				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
3988
+				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
3989
+				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
3990
+			}
3991
+		},
3992
+	},
3993
+	{ /* sentinel */ }
3994
+};
3995
+
3996
+static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
3997
+	{
3998
+		.reg = 0xff3e0000,
3999
+		.num_ports	= 1,
4000
+		.phy_tuning	= rv1106_usb2phy_tuning,
4001
+		.clkout_ctl	= { 0x0058, 4, 4, 1, 0 },
4002
+		.port_cfgs	= {
4003
+			[USB2PHY_PORT_OTG] = {
4004
+				.phy_sus	= { 0x0050, 8, 0, 0, 0x1d1 },
4005
+				.bvalid_det_en	= { 0x0100, 2, 2, 0, 1 },
4006
+				.bvalid_det_st	= { 0x0104, 2, 2, 0, 1 },
4007
+				.bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
4008
+				.bvalid_grf_sel	= { 0x0058, 15, 14, 0, 3 },
4009
+				.iddig_output	= { 0x0050, 10, 10, 0, 1 },
4010
+				.iddig_en	= { 0x0050, 9, 9, 0, 1 },
4011
+				.idfall_det_en	= { 0x0100, 5, 5, 0, 1 },
4012
+				.idfall_det_st	= { 0x0104, 5, 5, 0, 1 },
4013
+				.idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
4014
+				.idrise_det_en	= { 0x0100, 4, 4, 0, 1 },
4015
+				.idrise_det_st	= { 0x0104, 4, 4, 0, 1 },
4016
+				.idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
4017
+				.ls_det_en	= { 0x0100, 0, 0, 0, 1 },
4018
+				.ls_det_st	= { 0x0104, 0, 0, 0, 1 },
4019
+				.ls_det_clr	= { 0x0108, 0, 0, 0, 1 },
4020
+				.utmi_avalid	= { 0x0060, 10, 10, 0, 1 },
4021
+				.utmi_bvalid	= { 0x0060, 9, 9, 0, 1 },
4022
+				.utmi_iddig	= { 0x0060, 6, 6, 0, 1 },
4023
+				.utmi_ls	= { 0x0060, 5, 4, 0, 1 },
4024
+			},
4025
+		},
4026
+		.chg_det = {
4027
+			.chg_mode	= { 0x0050, 8, 0, 0, 0x1d7 },
4028
+			.cp_det		= { 0x0060, 13, 13, 0, 1 },
4029
+			.dcp_det	= { 0x0060, 12, 12, 0, 1 },
4030
+			.dp_det		= { 0x0060, 14, 14, 0, 1 },
4031
+			.idm_sink_en	= { 0x0058, 8, 8, 0, 1 },
4032
+			.idp_sink_en	= { 0x0058, 7, 7, 0, 1 },
4033
+			.idp_src_en	= { 0x0058, 9, 9, 0, 1 },
4034
+			.rdm_pdwn_en	= { 0x0058, 10, 10, 0, 1 },
4035
+			.vdm_src_en	= { 0x0058, 12, 12, 0, 1 },
4036
+			.vdp_src_en	= { 0x0058, 11, 11, 0, 1 },
4037
+		},
4038
+	},
4039
+	{ /* sentinel */ }
4040
+};
4041
+
32604042 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
32614043 	{
32624044 		.reg = 0x100,
....@@ -3300,17 +4082,51 @@
33004082 };
33014083 
33024084 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
4085
+#ifdef CONFIG_CPU_PX30
4086
+	{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
4087
+#endif
4088
+#ifdef CONFIG_CPU_RK1808
33034089 	{ .compatible = "rockchip,rk1808-usb2phy", .data = &rk1808_phy_cfgs },
4090
+#endif
4091
+#ifdef CONFIG_CPU_RK312X
33044092 	{ .compatible = "rockchip,rk3128-usb2phy", .data = &rk312x_phy_cfgs },
4093
+#endif
4094
+#ifdef CONFIG_CPU_RK322X
33054095 	{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
4096
+#endif
4097
+#ifdef CONFIG_CPU_RK3308
33064098 	{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
4099
+#endif
4100
+#ifdef CONFIG_CPU_RK3328
33074101 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
4102
+#endif
4103
+#ifdef CONFIG_CPU_RK3366
33084104 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
4105
+#endif
4106
+#ifdef CONFIG_CPU_RK3368
33094107 	{ .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },
4108
+#endif
4109
+#ifdef CONFIG_CPU_RK3399
33104110 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
4111
+#endif
4112
+#ifdef CONFIG_CPU_RK3528
33114113 	{ .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
4114
+#endif
4115
+#ifdef CONFIG_CPU_RK3562
4116
+	{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
4117
+#endif
4118
+#ifdef CONFIG_CPU_RK3568
33124119 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
4120
+#endif
4121
+#ifdef CONFIG_CPU_RK3588
4122
+	{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
4123
+#endif
4124
+#ifdef CONFIG_CPU_RV1106
4125
+	{ .compatible = "rockchip,rv1106-usb2phy", .data = &rv1106_phy_cfgs },
4126
+#endif
4127
+#ifdef CONFIG_CPU_RV1108
33134128 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
4129
+#endif
33144130 	{}
33154131 };
33164132 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);