forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/pci/quirks.c
....@@ -20,7 +20,6 @@
2020 #include <linux/delay.h>
2121 #include <linux/acpi.h>
2222 #include <linux/dmi.h>
23
-#include <linux/pci-aspm.h>
2423 #include <linux/ioport.h>
2524 #include <linux/sched.h>
2625 #include <linux/ktime.h>
....@@ -37,7 +36,7 @@
3736 				 void (*fn)(struct pci_dev *dev))
3837 {
3938 	if (initcall_debug)
40
-		pci_info(dev, "calling  %pF @ %i\n", fn, task_pid_nr(current));
39
+		pci_info(dev, "calling  %pS @ %i\n", fn, task_pid_nr(current));
4140 
4241 	return ktime_get();
4342 }
....@@ -52,7 +51,7 @@
5251 	delta = ktime_sub(rettime, calltime);
5352 	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
5453 	if (initcall_debug || duration > 10000)
55
-		pci_info(dev, "%pF took %lld usecs\n", fn, duration);
54
+		pci_info(dev, "%pS took %lld usecs\n", fn, duration);
5655 }
5756 
5857 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
....@@ -160,8 +159,7 @@
160159 	u8 tmp;
161160 
162161 	if (pci_cache_line_size)
163
-		printk(KERN_DEBUG "PCI: CLS %u bytes\n",
164
-		       pci_cache_line_size << 2);
162
+		pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
165163 
166164 	pci_apply_fixup_final_quirks = true;
167165 	for_each_pci_dev(dev) {
....@@ -178,16 +176,16 @@
178176 			if (!tmp || cls == tmp)
179177 				continue;
180178 
181
-			printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
182
-			       cls << 2, tmp << 2,
183
-			       pci_dfl_cache_line_size << 2);
179
+			pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
180
+			         cls << 2, tmp << 2,
181
+				 pci_dfl_cache_line_size << 2);
184182 			pci_cache_line_size = pci_dfl_cache_line_size;
185183 		}
186184 	}
187185 
188186 	if (!pci_cache_line_size) {
189
-		printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
190
-		       cls << 2, pci_dfl_cache_line_size << 2);
187
+		pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
188
+			pci_dfl_cache_line_size << 2);
191189 		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
192190 	}
193191 
....@@ -477,7 +475,7 @@
477475 {
478476 	int i;
479477 
480
-	for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
478
+	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
481479 		struct resource *r = &dev->resource[i];
482480 
483481 		if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
....@@ -618,6 +616,31 @@
618616 }
619617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
620618 		quirk_amd_nl_class);
619
+
620
+/*
621
+ * Synopsys USB 3.x host HAPS platform has a class code of
622
+ * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it.  However, these
623
+ * devices should use dwc3-haps driver.  Change these devices' class code to
624
+ * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
625
+ * them.
626
+ */
627
+static void quirk_synopsys_haps(struct pci_dev *pdev)
628
+{
629
+	u32 class = pdev->class;
630
+
631
+	switch (pdev->device) {
632
+	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
633
+	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
634
+	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
635
+		pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
636
+		pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
637
+			 class, pdev->class);
638
+		break;
639
+	}
640
+}
641
+DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
642
+			       PCI_CLASS_SERIAL_USB_XHCI, 0,
643
+			       quirk_synopsys_haps);
621644 
622645 /*
623646  * Let's make the southbridge information explicit instead of having to
....@@ -1549,7 +1572,7 @@
15491572 
15501573 	pci_read_config_dword(dev, 0xF0, &rcba);
15511574 	/* use bits 31:14, 16 kB aligned */
1552
-	asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1575
+	asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
15531576 	if (asus_rcba_base == NULL)
15541577 		return;
15551578 }
....@@ -1708,7 +1731,7 @@
17081731 	case PCI_DEVICE_ID_JMICRON_JMB366:
17091732 		/* Redirect IDE second PATA port to the right spot */
17101733 		conf5 |= (1 << 24);
1711
-		/* Fall through */
1734
+		fallthrough;
17121735 	case PCI_DEVICE_ID_JMICRON_JMB361:
17131736 	case PCI_DEVICE_ID_JMICRON_JMB363:
17141737 	case PCI_DEVICE_ID_JMICRON_JMB369:
....@@ -1787,11 +1810,23 @@
17871810 	 * The next five BARs all seem to be rubbish, so just clean
17881811 	 * them out.
17891812 	 */
1790
-	for (i = 1; i < 6; i++)
1813
+	for (i = 1; i < PCI_STD_NUM_BARS; i++)
17911814 		memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
17921815 }
17931816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_EESSC,	quirk_alder_ioapic);
17941817 #endif
1818
+
1819
+static void quirk_no_msi(struct pci_dev *dev)
1820
+{
1821
+	pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1822
+	dev->no_msi = 1;
1823
+}
1824
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1825
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1826
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1827
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1828
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1829
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
17951830 
17961831 static void quirk_pcie_mch(struct pci_dev *pdev)
17971832 {
....@@ -1824,7 +1859,7 @@
18241859  */
18251860 static void quirk_intel_pcie_pm(struct pci_dev *dev)
18261861 {
1827
-	pci_pm_d3_delay = 120;
1862
+	pci_pm_d3hot_delay = 120;
18281863 	dev->no_d1d2 = 1;
18291864 }
18301865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e2, quirk_intel_pcie_pm);
....@@ -1851,12 +1886,12 @@
18511886 
18521887 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
18531888 {
1854
-	if (dev->d3_delay >= delay)
1889
+	if (dev->d3hot_delay >= delay)
18551890 		return;
18561891 
1857
-	dev->d3_delay = delay;
1892
+	dev->d3hot_delay = delay;
18581893 	pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1859
-		 dev->d3_delay);
1894
+		 dev->d3hot_delay);
18601895 }
18611896 
18621897 static void quirk_radeon_pm(struct pci_dev *dev)
....@@ -2203,7 +2238,7 @@
22032238 		if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
22042239 				dev->subsystem_device == 0x0299)
22052240 			return;
2206
-		/* else: fall through */
2241
+		fallthrough;
22072242 	case PCI_DEVICE_ID_NETMOS_9735:
22082243 	case PCI_DEVICE_ID_NETMOS_9745:
22092244 	case PCI_DEVICE_ID_NETMOS_9845:
....@@ -2321,6 +2356,13 @@
23212356  * disable both L0s and L1 for now to be safe.
23222357  */
23232358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2359
+
2360
+/*
2361
+ * Micron 2100AI NVMe doesn't work reliably when ASPM is enabled. Disable
2362
+ * ASPM support for it now.
2363
+ */
2364
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICRON, PCI_DEVICE_ID_MICRON_2100AI,
2365
+			quirk_disable_aspm_l0s_l1);
23242366 
23252367 /*
23262368  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
....@@ -2645,6 +2687,59 @@
26452687 			nvenet_msi_disable);
26462688 
26472689 /*
2690
+ * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2691
+ * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2692
+ * generate MSI interrupts for PME and AER events instead only INTx interrupts
2693
+ * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2694
+ * for other events, since PCIe specificiation doesn't support using a mix of
2695
+ * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2696
+ * service drivers registering their respective ISRs for MSIs.
2697
+ */
2698
+static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2699
+{
2700
+	dev->no_msi = 1;
2701
+}
2702
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2703
+			      PCI_CLASS_BRIDGE_PCI, 8,
2704
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2705
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2706
+			      PCI_CLASS_BRIDGE_PCI, 8,
2707
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2708
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2709
+			      PCI_CLASS_BRIDGE_PCI, 8,
2710
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2711
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2712
+			      PCI_CLASS_BRIDGE_PCI, 8,
2713
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2714
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2715
+			      PCI_CLASS_BRIDGE_PCI, 8,
2716
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2717
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2718
+			      PCI_CLASS_BRIDGE_PCI, 8,
2719
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2720
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2721
+			      PCI_CLASS_BRIDGE_PCI, 8,
2722
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2723
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2724
+			      PCI_CLASS_BRIDGE_PCI, 8,
2725
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2726
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2727
+			      PCI_CLASS_BRIDGE_PCI, 8,
2728
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2729
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2730
+			      PCI_CLASS_BRIDGE_PCI, 8,
2731
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2732
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2733
+			      PCI_CLASS_BRIDGE_PCI, 8,
2734
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2735
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2736
+			      PCI_CLASS_BRIDGE_PCI, 8,
2737
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2738
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2739
+			      PCI_CLASS_BRIDGE_PCI, 8,
2740
+			      pci_quirk_nvidia_tegra_disable_rp_msi);
2741
+
2742
+/*
26482743  * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
26492744  * config register.  This register controls the routing of legacy
26502745  * interrupts from devices that route through the MCP55.  If this register
....@@ -2664,7 +2759,7 @@
26642759 	pci_read_config_dword(dev, 0x74, &cfg);
26652760 
26662761 	if (cfg & ((1 << 2) | (1 << 15))) {
2667
-		printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
2762
+		pr_info("Rewriting IRQ routing register on MCP55\n");
26682763 		cfg &= ~((1 << 2) | (1 << 15));
26692764 		pci_write_config_dword(dev, 0x74, cfg);
26702765 	}
....@@ -2977,6 +3072,24 @@
29773072 			quirk_msi_intx_disable_qca_bug);
29783073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
29793074 			quirk_msi_intx_disable_qca_bug);
3075
+
3076
+/*
3077
+ * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3078
+ * should be disabled on platforms where the device (mistakenly) advertises it.
3079
+ *
3080
+ * Notice that this quirk also disables MSI (which may work, but hasn't been
3081
+ * tested), since currently there is no standard way to disable only MSI-X.
3082
+ *
3083
+ * The 0031 device id is reused for other non Root Port device types,
3084
+ * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3085
+ */
3086
+static void quirk_al_msi_disable(struct pci_dev *dev)
3087
+{
3088
+	dev->no_msi = 1;
3089
+	pci_warn(dev, "Disabling MSI/MSI-X\n");
3090
+}
3091
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3092
+			      PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
29803093 #endif /* CONFIG_PCI_MSI */
29813094 
29823095 /*
....@@ -3296,36 +3409,36 @@
32963409  * PCI devices which are on Intel chips can skip the 10ms delay
32973410  * before entering D3 mode.
32983411  */
3299
-static void quirk_remove_d3_delay(struct pci_dev *dev)
3412
+static void quirk_remove_d3hot_delay(struct pci_dev *dev)
33003413 {
3301
-	dev->d3_delay = 0;
3414
+	dev->d3hot_delay = 0;
33023415 }
3303
-/* C600 Series devices do not need 10ms d3_delay */
3304
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3305
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3306
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3307
-/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3308
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3309
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3310
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3311
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3312
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3313
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3314
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3315
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3316
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3317
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3318
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3319
-/* Intel Cherrytrail devices do not need 10ms d3_delay */
3320
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3321
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3322
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3323
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3324
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3325
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3326
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3327
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3328
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3416
+/* C600 Series devices do not need 10ms d3hot_delay */
3417
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3418
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3419
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3420
+/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3421
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3422
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3423
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3424
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3425
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3426
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3427
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3428
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3429
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3430
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3431
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3432
+/* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3433
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3434
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3435
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3436
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3437
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3438
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3439
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3440
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3441
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
33293442 
33303443 /*
33313444  * Some devices may pass our check in pci_intx_mask_supported() if
....@@ -3483,7 +3596,7 @@
34833596  * The device will throw a Link Down error on AER-capable systems and
34843597  * regardless of AER, config space of the device is never accessible again
34853598  * and typically causes the system to hang or reset when access is attempted.
3486
- * http://www.spinics.net/lists/linux-pci/msg34797.html
3599
+ * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
34873600  */
34883601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
34893602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
....@@ -3615,63 +3728,6 @@
36153728 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
36163729 			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
36173730 			       quirk_apple_poweroff_thunderbolt);
3618
-
3619
-/*
3620
- * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3621
- *
3622
- * During suspend the Thunderbolt controller is reset and all PCI
3623
- * tunnels are lost. The NHI driver will try to reestablish all tunnels
3624
- * during resume. We have to manually wait for the NHI since there is
3625
- * no parent child relationship between the NHI and the tunneled
3626
- * bridges.
3627
- */
3628
-static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3629
-{
3630
-	struct pci_dev *sibling = NULL;
3631
-	struct pci_dev *nhi = NULL;
3632
-
3633
-	if (!x86_apple_machine)
3634
-		return;
3635
-	if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3636
-		return;
3637
-
3638
-	/*
3639
-	 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3640
-	 * host controller and not on a Thunderbolt endpoint.
3641
-	 */
3642
-	sibling = pci_get_slot(dev->bus, 0x0);
3643
-	if (sibling == dev)
3644
-		goto out; /* we are the downstream bridge to the NHI */
3645
-	if (!sibling || !sibling->subordinate)
3646
-		goto out;
3647
-	nhi = pci_get_slot(sibling->subordinate, 0x0);
3648
-	if (!nhi)
3649
-		goto out;
3650
-	if (nhi->vendor != PCI_VENDOR_ID_INTEL
3651
-		    || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3652
-			nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3653
-			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3654
-			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3655
-		    || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3656
-		goto out;
3657
-	pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3658
-	device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3659
-out:
3660
-	pci_dev_put(nhi);
3661
-	pci_dev_put(sibling);
3662
-}
3663
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3664
-			       PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3665
-			       quirk_apple_wait_for_thunderbolt);
3666
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3667
-			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3668
-			       quirk_apple_wait_for_thunderbolt);
3669
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3670
-			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3671
-			       quirk_apple_wait_for_thunderbolt);
3672
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3673
-			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3674
-			       quirk_apple_wait_for_thunderbolt);
36753731 #endif
36763732 
36773733 /*
....@@ -4013,7 +4069,7 @@
40134069 static void quirk_dma_func0_alias(struct pci_dev *dev)
40144070 {
40154071 	if (PCI_FUNC(dev->devfn) != 0)
4016
-		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
4072
+		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
40174073 }
40184074 
40194075 /*
....@@ -4027,7 +4083,7 @@
40274083 static void quirk_dma_func1_alias(struct pci_dev *dev)
40284084 {
40294085 	if (PCI_FUNC(dev->devfn) != 1)
4030
-		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
4086
+		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
40314087 }
40324088 
40334089 /*
....@@ -4118,9 +4174,8 @@
41184174 
41194175 	id = pci_match_id(fixed_dma_alias_tbl, dev);
41204176 	if (id)
4121
-		pci_add_dma_alias(dev, id->driver_data);
4177
+		pci_add_dma_alias(dev, id->driver_data, 1);
41224178 }
4123
-
41244179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
41254180 
41264181 /*
....@@ -4160,9 +4215,9 @@
41604215  */
41614216 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
41624217 {
4163
-	pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4164
-	pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4165
-	pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4218
+	pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4219
+	pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4220
+	pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
41664221 }
41674222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
41684223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
....@@ -4186,13 +4241,8 @@
41864241 	const unsigned int num_pci_slots = 0x20;
41874242 	unsigned int slot;
41884243 
4189
-	for (slot = 0; slot < num_pci_slots; slot++) {
4190
-		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0));
4191
-		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x1));
4192
-		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x2));
4193
-		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x3));
4194
-		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x4));
4195
-	}
4244
+	for (slot = 0; slot < num_pci_slots; slot++)
4245
+		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
41964246 }
41974247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
41984248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
....@@ -4351,7 +4401,7 @@
43514401  */
43524402 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
43534403 {
4354
-	struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4404
+	struct pci_dev *root_port = pcie_find_root_port(pdev);
43554405 
43564406 	if (!root_port) {
43574407 		pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
....@@ -4410,9 +4460,9 @@
44104460  * redirect (CR) since all transactions are redirected to the upstream
44114461  * root complex.
44124462  *
4413
- * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4414
- * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4415
- * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4463
+ * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4464
+ * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4465
+ * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
44164466  *
44174467  * 1002:4385 SBx00 SMBus Controller
44184468  * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
....@@ -4500,6 +4550,29 @@
45004550 }
45014551 
45024552 /*
4553
+ * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4554
+ * But the implementation could block peer-to-peer transactions between them
4555
+ * and provide ACS-like functionality.
4556
+ */
4557
+static int  pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4558
+{
4559
+	if (!pci_is_pcie(dev) ||
4560
+	    ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4561
+	     (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4562
+		return -ENOTTY;
4563
+
4564
+	switch (dev->device) {
4565
+	case 0x0710 ... 0x071e:
4566
+	case 0x0721:
4567
+	case 0x0723 ... 0x0732:
4568
+		return pci_acs_ctrl_enabled(acs_flags,
4569
+			PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4570
+	}
4571
+
4572
+	return false;
4573
+}
4574
+
4575
+/*
45034576  * Many Intel PCH Root Ports do provide ACS-like features to disable peer
45044577  * transactions and validate bus numbers in requests, but do not provide an
45054578  * actual PCIe ACS capability.  This is the list of device IDs known to fall
....@@ -4577,6 +4650,36 @@
45774650 }
45784651 
45794652 /*
4653
+ * Each of these NXP Root Ports is in a Root Complex with a unique segment
4654
+ * number and does provide isolation features to disable peer transactions
4655
+ * and validate bus numbers in requests, but does not provide an ACS
4656
+ * capability.
4657
+ */
4658
+static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4659
+{
4660
+	return pci_acs_ctrl_enabled(acs_flags,
4661
+		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4662
+}
4663
+
4664
+static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4665
+{
4666
+	if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4667
+		return -ENOTTY;
4668
+
4669
+	/*
4670
+	 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4671
+	 * but do include ACS-like functionality. The hardware doesn't support
4672
+	 * peer-to-peer transactions via the root port and each has a unique
4673
+	 * segment number.
4674
+	 *
4675
+	 * Additionally, the root ports cannot send traffic to each other.
4676
+	 */
4677
+	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4678
+
4679
+	return acs_flags ? 0 : 1;
4680
+}
4681
+
4682
+/*
45804683  * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
45814684  * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
45824685  * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
....@@ -4613,11 +4716,11 @@
46134716  *
46144717  * 0x9d10-0x9d1b PCI Express Root port #{1-12}
46154718  *
4616
- * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4617
- * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4618
- * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4619
- * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4620
- * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4719
+ * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4720
+ * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4721
+ * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4722
+ * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4723
+ * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
46214724  * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
46224725  * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
46234726  */
....@@ -4646,7 +4749,7 @@
46464749 	if (!pci_quirk_intel_spt_pch_acs_match(dev))
46474750 		return -ENOTTY;
46484751 
4649
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4752
+	pos = dev->acs_cap;
46504753 	if (!pos)
46514754 		return -ENOTTY;
46524755 
....@@ -4775,6 +4878,8 @@
47754878 	/* QCOM QDF2xxx root ports */
47764879 	{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
47774880 	{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4881
+	/* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4882
+	{ PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
47784883 	/* Intel PCH root ports */
47794884 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
47804885 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
....@@ -4799,7 +4904,51 @@
47994904 	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
48004905 	/* Broadcom multi-function device */
48014906 	{ PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4907
+	{ PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4908
+	{ PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4909
+	{ PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
48024910 	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4911
+	/* Amazon Annapurna Labs */
4912
+	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4913
+	/* Zhaoxin multi-function devices */
4914
+	{ PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4915
+	{ PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4916
+	{ PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4917
+	/* NXP root ports, xx=16, 12, or 08 cores */
4918
+	/* LX2xx0A : without security features + CAN-FD */
4919
+	{ PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4920
+	{ PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4921
+	{ PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4922
+	/* LX2xx0C : security features + CAN-FD */
4923
+	{ PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4924
+	{ PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4925
+	{ PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4926
+	/* LX2xx0E : security features + CAN */
4927
+	{ PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4928
+	{ PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4929
+	{ PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4930
+	/* LX2xx0N : without security features + CAN */
4931
+	{ PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4932
+	{ PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4933
+	{ PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4934
+	/* LX2xx2A : without security features + CAN-FD */
4935
+	{ PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4936
+	{ PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4937
+	{ PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4938
+	/* LX2xx2C : security features + CAN-FD */
4939
+	{ PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4940
+	{ PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
4941
+	{ PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
4942
+	/* LX2xx2E : security features + CAN */
4943
+	{ PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
4944
+	{ PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
4945
+	{ PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
4946
+	/* LX2xx2N : without security features + CAN */
4947
+	{ PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
4948
+	{ PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
4949
+	{ PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
4950
+	/* Zhaoxin Root/Downstream Ports */
4951
+	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
48034952 	{ 0 }
48044953 };
48054954 
....@@ -4873,7 +5022,7 @@
48735022 	if (!(rcba & INTEL_LPC_RCBA_ENABLE))
48745023 		return -EINVAL;
48755024 
4876
-	rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
5025
+	rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
48775026 				   PAGE_ALIGN(INTEL_UPDCR_REG));
48785027 	if (!rcba_mem)
48795028 		return -ENOMEM;
....@@ -4923,6 +5072,13 @@
49235072 	}
49245073 }
49255074 
5075
+/*
5076
+ * Currently this quirk does the equivalent of
5077
+ * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5078
+ *
5079
+ * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5080
+ * if dev->external_facing || dev->untrusted
5081
+ */
49265082 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
49275083 {
49285084 	if (!pci_quirk_intel_pch_acs_match(dev))
....@@ -4950,7 +5106,7 @@
49505106 	if (!pci_quirk_intel_spt_pch_acs_match(dev))
49515107 		return -ENOTTY;
49525108 
4953
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
5109
+	pos = dev->acs_cap;
49545110 	if (!pos)
49555111 		return -ENOTTY;
49565112 
....@@ -4961,6 +5117,9 @@
49615117 	ctrl |= (cap & PCI_ACS_RR);
49625118 	ctrl |= (cap & PCI_ACS_CR);
49635119 	ctrl |= (cap & PCI_ACS_UF);
5120
+
5121
+	if (dev->external_facing || dev->untrusted)
5122
+		ctrl |= (cap & PCI_ACS_TB);
49645123 
49655124 	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
49665125 
....@@ -4977,7 +5136,7 @@
49775136 	if (!pci_quirk_intel_spt_pch_acs_match(dev))
49785137 		return -ENOTTY;
49795138 
4980
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
5139
+	pos = dev->acs_cap;
49815140 	if (!pos)
49825141 		return -ENOTTY;
49835142 
....@@ -5354,7 +5513,7 @@
53545513 	bool found;
53555514 	struct pci_dev *bridge = bus->self;
53565515 
5357
-	pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5516
+	pos = bridge->acs_cap;
53585517 
53595518 	/* Disable ACS SV before initial config reads */
53605519 	if (pos) {
....@@ -5389,7 +5548,6 @@
53895548 	void __iomem *mmio;
53905549 	struct ntb_info_regs __iomem *mmio_ntb;
53915550 	struct ntb_ctrl_regs __iomem *mmio_ctrl;
5392
-	struct sys_info_regs __iomem *mmio_sys_info;
53935551 	u64 partition_map;
53945552 	u8 partition;
53955553 	int pp;
....@@ -5410,7 +5568,6 @@
54105568 
54115569 	mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
54125570 	mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5413
-	mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
54145571 
54155572 	partition = ioread8(&mmio_ntb->partition_id);
54165573 
....@@ -5452,7 +5609,7 @@
54525609 			pci_dbg(pdev,
54535610 				"Aliasing Partition %d Proxy ID %02x.%d\n",
54545611 				pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5455
-			pci_add_dma_alias(pdev, devfn);
5612
+			pci_add_dma_alias(pdev, devfn, 1);
54565613 		}
54575614 	}
54585615 
....@@ -5493,6 +5650,39 @@
54935650 SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
54945651 SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
54955652 SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */
5653
+SWITCHTEC_QUIRK(0x4000);  /* PFX 100XG4 */
5654
+SWITCHTEC_QUIRK(0x4084);  /* PFX 84XG4  */
5655
+SWITCHTEC_QUIRK(0x4068);  /* PFX 68XG4  */
5656
+SWITCHTEC_QUIRK(0x4052);  /* PFX 52XG4  */
5657
+SWITCHTEC_QUIRK(0x4036);  /* PFX 36XG4  */
5658
+SWITCHTEC_QUIRK(0x4028);  /* PFX 28XG4  */
5659
+SWITCHTEC_QUIRK(0x4100);  /* PSX 100XG4 */
5660
+SWITCHTEC_QUIRK(0x4184);  /* PSX 84XG4  */
5661
+SWITCHTEC_QUIRK(0x4168);  /* PSX 68XG4  */
5662
+SWITCHTEC_QUIRK(0x4152);  /* PSX 52XG4  */
5663
+SWITCHTEC_QUIRK(0x4136);  /* PSX 36XG4  */
5664
+SWITCHTEC_QUIRK(0x4128);  /* PSX 28XG4  */
5665
+SWITCHTEC_QUIRK(0x4200);  /* PAX 100XG4 */
5666
+SWITCHTEC_QUIRK(0x4284);  /* PAX 84XG4  */
5667
+SWITCHTEC_QUIRK(0x4268);  /* PAX 68XG4  */
5668
+SWITCHTEC_QUIRK(0x4252);  /* PAX 52XG4  */
5669
+SWITCHTEC_QUIRK(0x4236);  /* PAX 36XG4  */
5670
+SWITCHTEC_QUIRK(0x4228);  /* PAX 28XG4  */
5671
+
5672
+/*
5673
+ * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5674
+ * These IDs are used to forward responses to the originator on the other
5675
+ * side of the NTB.  Alias all possible IDs to the NTB to permit access when
5676
+ * the IOMMU is turned on.
5677
+ */
5678
+static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5679
+{
5680
+	pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5681
+	/* PLX NTB may use all 256 devfns */
5682
+	pci_add_dma_alias(pdev, 0, 256);
5683
+}
5684
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5685
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
54965686 
54975687 /*
54985688  * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
....@@ -5564,17 +5754,26 @@
55645754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
55655755 
55665756 /*
5567
- * Device [12d8:0x400e] and [12d8:0x400f]
5757
+ * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5758
+ *
55685759  * These devices advertise PME# support in all power states but don't
55695760  * reliably assert it.
5761
+ *
5762
+ * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5763
+ * says "The MSI Function is not implemented on this device" in chapters
5764
+ * 7.3.27, 7.3.29-7.3.31.
55705765  */
5571
-static void pci_fixup_no_pme(struct pci_dev *dev)
5766
+static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
55725767 {
5768
+#ifdef CONFIG_PCI_MSI
5769
+	pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5770
+	dev->no_msi = 1;
5771
+#endif
55735772 	pci_info(dev, "PME# is unreliable, disabling it\n");
55745773 	dev->pme_support = 0;
55755774 }
5576
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme);
5577
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme);
5775
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5776
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
55785777 
55795778 static void apex_pci_fixup_class(struct pci_dev *pdev)
55805779 {