forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/pci/controller/dwc/pcie-dw-rockchip.c
....@@ -14,6 +14,7 @@
1414 #include <linux/gpio.h>
1515 #include <linux/init.h>
1616 #include <linux/interrupt.h>
17
+#include <linux/iopoll.h>
1718 #include <linux/irq.h>
1819 #include <linux/irqchip/chained_irq.h>
1920 #include <linux/irqdomain.h>
....@@ -29,6 +30,7 @@
2930 #include <linux/of_pci.h>
3031 #include <linux/pci.h>
3132 #include <linux/phy/phy.h>
33
+#include <linux/phy/pcie.h>
3234 #include <linux/platform_device.h>
3335 #include <linux/poll.h>
3436 #include <linux/regmap.h>
....@@ -50,15 +52,11 @@
5052 	RK_PCIE_RC_TYPE,
5153 };
5254 
53
-struct reset_bulk_data	{
54
-	const char *id;
55
-	struct reset_control *rst;
56
-};
57
-
5855 #define RK_PCIE_DBG			0
5956 
6057 #define PCIE_DMA_OFFSET			0x380000
6158 
59
+#define PCIE_DMA_CTRL_OFF		0x8
6260 #define PCIE_DMA_WR_ENB			0xc
6361 #define PCIE_DMA_WR_CTRL_LO		0x200
6462 #define PCIE_DMA_WR_CTRL_HI		0x204
....@@ -102,6 +100,8 @@
102100 
103101 #define PCIE_CAP_LINK_CONTROL2_LINK_STATUS	0xa0
104102 
103
+#define PCIE_CLIENT_INTR_STATUS_MSG_RX	0x04
104
+#define PME_TO_ACK			(BIT(9) | BIT(25))
105105 #define PCIE_CLIENT_INTR_STATUS_LEGACY	0x08
106106 #define PCIE_CLIENT_INTR_STATUS_MISC	0x10
107107 #define PCIE_CLIENT_INTR_MASK_LEGACY	0x1c
....@@ -109,12 +109,21 @@
109109 #define MASK_LEGACY_INT(x)		(0x00110011 << x)
110110 #define UNMASK_LEGACY_INT(x)		(0x00110000 << x)
111111 #define PCIE_CLIENT_INTR_MASK		0x24
112
+#define PCIE_CLIENT_POWER		0x2c
113
+#define READY_ENTER_L23			BIT(3)
114
+#define PCIE_CLIENT_MSG_GEN		0x34
115
+#define PME_TURN_OFF			(BIT(4) | BIT(20))
112116 #define PCIE_CLIENT_GENERAL_DEBUG	0x104
113117 #define PCIE_CLIENT_HOT_RESET_CTRL	0x180
118
+#define PCIE_LTSSM_APP_DLY1_EN		BIT(0)
119
+#define PCIE_LTSSM_APP_DLY2_EN		BIT(1)
120
+#define PCIE_LTSSM_APP_DLY1_DONE	BIT(2)
121
+#define PCIE_LTSSM_APP_DLY2_DONE	BIT(3)
114122 #define PCIE_LTSSM_ENABLE_ENHANCE	BIT(4)
115123 #define PCIE_CLIENT_LTSSM_STATUS	0x300
116124 #define SMLH_LINKUP			BIT(16)
117125 #define RDLH_LINKUP			BIT(17)
126
+#define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154
118127 #define PCIE_CLIENT_DBG_FIFO_MODE_CON	0x310
119128 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
120129 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
....@@ -122,20 +131,31 @@
122131 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
123132 #define PCIE_CLIENT_DBG_FIFO_STATUS	0x350
124133 #define PCIE_CLIENT_DBG_TRANSITION_DATA	0xffff0000
125
-#define PCIE_CLIENT_DBF_EN		0xffff0003
134
+#define PCIE_CLIENT_DBF_EN		0xffff0007
126135 
127136 #define PCIE_PHY_LINKUP			BIT(0)
128137 #define PCIE_DATA_LINKUP		BIT(1)
129138 
130
-#define PCIE_RESBAR_CTRL_REG0_REG	0x2a8
139
+#define PCIE_TYPE0_HDR_DBI2_OFFSET	0x100000
131140 #define PCIE_SB_BAR0_MASK_REG		0x100010
132141 
133142 #define PCIE_PL_ORDER_RULE_CTRL_OFF	0x8B4
143
+#define RK_PCIE_L2_TMOUT_US		5000
144
+#define RK_PCIE_HOTRESET_TMOUT_US	10000
145
+
146
+enum rk_pcie_ltssm_code {
147
+	S_L0 = 0x11,
148
+	S_L0S = 0x12,
149
+	S_L1_IDLE = 0x14,
150
+	S_L2_IDLE = 0x15,
151
+	S_MAX = 0x1f,
152
+};
134153 
135154 struct rk_pcie {
136155 	struct dw_pcie			*pci;
137156 	enum rk_pcie_device_mode	mode;
138157 	enum phy_mode			phy_mode;
158
+	int				phy_sub_mode;
139159 	unsigned char			bar_to_atu[6];
140160 	phys_addr_t			*outbound_addr;
141161 	unsigned long			*ib_window_map;
....@@ -146,9 +166,10 @@
146166 	void __iomem			*apb_base;
147167 	struct phy			*phy;
148168 	struct clk_bulk_data		*clks;
169
+	struct reset_control		*rsts;
149170 	unsigned int			clk_cnt;
150
-	struct reset_bulk_data		*rsts;
151171 	struct gpio_desc		*rst_gpio;
172
+	u32				perst_inactive_ms;
152173 	struct gpio_desc		*prsnt_gpio;
153174 	phys_addr_t			mem_start;
154175 	size_t				mem_size;
....@@ -157,15 +178,22 @@
157178 	struct regmap			*pmu_grf;
158179 	struct dma_trx_obj		*dma_obj;
159180 	bool				in_suspend;
160
-	bool                            skip_scan_in_resume;
181
+	bool				skip_scan_in_resume;
161182 	bool				is_rk1808;
162183 	bool				is_signal_test;
163184 	bool				bifurcation;
185
+	bool				supports_clkreq;
164186 	struct regulator		*vpcie3v3;
165187 	struct irq_domain		*irq_domain;
166188 	raw_spinlock_t			intx_lock;
189
+	u16				aspm;
190
+	u32				l1ss_ctl1;
167191 	struct dentry			*debugfs;
168192 	u32				msi_vector_num;
193
+	struct workqueue_struct		*hot_rst_wq;
194
+	struct work_struct		hot_rst_work;
195
+	u32				comp_prst[2];
196
+	u32				intx;
169197 };
170198 
171199 struct rk_pcie_of_data {
....@@ -174,7 +202,6 @@
174202 };
175203 
176204 #define to_rk_pcie(x)	dev_get_drvdata((x)->dev)
177
-static const struct dev_pm_ops rockchip_dw_pcie_pm_ops;
178205 
179206 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
180207 {
....@@ -259,12 +286,154 @@
259286 	return 0;
260287 }
261288 
289
+static void rk_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
290
+{
291
+	int ret;
292
+
293
+	if (pci->ops->write_dbi) {
294
+		pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);
295
+		return;
296
+	}
297
+
298
+	ret = dw_pcie_write(pci->atu_base + reg, 4, val);
299
+	if (ret)
300
+		dev_err(pci->dev, "Write ATU address failed\n");
301
+}
302
+
303
+static void rk_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
304
+				     u32 val)
305
+{
306
+	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
307
+
308
+	rk_pcie_writel_atu(pci, offset + reg, val);
309
+}
310
+
311
+static u32 rk_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
312
+{
313
+	int ret;
314
+	u32 val;
315
+
316
+	if (pci->ops->read_dbi)
317
+		return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);
318
+
319
+	ret = dw_pcie_read(pci->atu_base + reg, 4, &val);
320
+	if (ret)
321
+		dev_err(pci->dev, "Read ATU address failed\n");
322
+
323
+	return val;
324
+}
325
+
326
+static u32 rk_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
327
+{
328
+	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
329
+
330
+	return rk_pcie_readl_atu(pci, offset + reg);
331
+}
332
+
333
+static int rk_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
334
+					   int index, int bar, u64 cpu_addr,
335
+					   enum dw_pcie_as_type as_type)
336
+{
337
+	int type;
338
+	u32 retries, val;
339
+
340
+	rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
341
+				 lower_32_bits(cpu_addr));
342
+	rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
343
+				 upper_32_bits(cpu_addr));
344
+
345
+	switch (as_type) {
346
+	case DW_PCIE_AS_MEM:
347
+		type = PCIE_ATU_TYPE_MEM;
348
+		break;
349
+	case DW_PCIE_AS_IO:
350
+		type = PCIE_ATU_TYPE_IO;
351
+		break;
352
+	default:
353
+		return -EINVAL;
354
+	}
355
+
356
+	rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
357
+				 PCIE_ATU_FUNC_NUM(func_no));
358
+	rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
359
+				 PCIE_ATU_FUNC_NUM_MATCH_EN |
360
+				 PCIE_ATU_ENABLE |
361
+				 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
362
+
363
+	/*
364
+	 * Make sure ATU enable takes effect before any subsequent config
365
+	 * and I/O accesses.
366
+	 */
367
+	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
368
+		val = rk_pcie_readl_ib_unroll(pci, index,
369
+					      PCIE_ATU_UNR_REGION_CTRL2);
370
+		if (val & PCIE_ATU_ENABLE)
371
+			return 0;
372
+
373
+		mdelay(LINK_WAIT_IATU);
374
+	}
375
+	dev_err(pci->dev, "Inbound iATU is not being enabled\n");
376
+
377
+	return -EBUSY;
378
+}
379
+
380
+
381
+static int rk_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
382
+				    int bar, u64 cpu_addr,
383
+				    enum dw_pcie_as_type as_type)
384
+{
385
+	int type;
386
+	u32 retries, val;
387
+
388
+	if (pci->iatu_unroll_enabled)
389
+		return rk_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
390
+						       cpu_addr, as_type);
391
+
392
+	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
393
+			   index);
394
+	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
395
+	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
396
+
397
+	switch (as_type) {
398
+	case DW_PCIE_AS_MEM:
399
+		type = PCIE_ATU_TYPE_MEM;
400
+		break;
401
+	case DW_PCIE_AS_IO:
402
+		type = PCIE_ATU_TYPE_IO;
403
+		break;
404
+	default:
405
+		return -EINVAL;
406
+	}
407
+
408
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
409
+			   PCIE_ATU_FUNC_NUM(func_no));
410
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
411
+			   PCIE_ATU_FUNC_NUM_MATCH_EN |
412
+			   PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
413
+
414
+	/*
415
+	 * Make sure ATU enable takes effect before any subsequent config
416
+	 * and I/O accesses.
417
+	 */
418
+	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
419
+		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
420
+		if (val & PCIE_ATU_ENABLE)
421
+			return 0;
422
+
423
+		mdelay(LINK_WAIT_IATU);
424
+	}
425
+	dev_err(pci->dev, "Inbound iATU is not being enabled\n");
426
+
427
+	return -EBUSY;
428
+}
429
+
262430 static int rk_pcie_ep_inbound_atu(struct rk_pcie *rk_pcie,
263431 				enum pci_barno bar, dma_addr_t cpu_addr,
264432 				enum dw_pcie_as_type as_type)
265433 {
266434 	int ret;
267435 	u32 free_win;
436
+	u8 func_no = 0x0;
268437 
269438 	if (rk_pcie->in_suspend) {
270439 		free_win = rk_pcie->bar_to_atu[bar];
....@@ -277,8 +446,8 @@
277446 		}
278447 	}
279448 
280
-	ret = dw_pcie_prog_inbound_atu(rk_pcie->pci, free_win, bar, cpu_addr,
281
-				       as_type);
449
+	ret = rk_pcie_prog_inbound_atu(rk_pcie->pci, func_no, free_win, bar,
450
+				       cpu_addr, as_type);
282451 	if (ret < 0) {
283452 		dev_err(rk_pcie->pci->dev, "Failed to program IB window\n");
284453 		return ret;
....@@ -291,6 +460,105 @@
291460 	set_bit(free_win, rk_pcie->ib_window_map);
292461 
293462 	return 0;
463
+}
464
+
465
+static void rk_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
466
+				     u32 val)
467
+{
468
+	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
469
+
470
+	rk_pcie_writel_atu(pci, offset + reg, val);
471
+}
472
+
473
+static u32 rk_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
474
+{
475
+	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
476
+
477
+	return rk_pcie_readl_atu(pci, offset + reg);
478
+}
479
+
480
+static void rk_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
481
+					     int index, int type,
482
+					     u64 cpu_addr, u64 pci_addr,
483
+					     u32 size)
484
+{
485
+	u32 retries, val;
486
+	u64 limit_addr = cpu_addr + size - 1;
487
+
488
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
489
+				 lower_32_bits(cpu_addr));
490
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
491
+				 upper_32_bits(cpu_addr));
492
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
493
+				 lower_32_bits(limit_addr));
494
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
495
+				 upper_32_bits(limit_addr));
496
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
497
+				 lower_32_bits(pci_addr));
498
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
499
+				 upper_32_bits(pci_addr));
500
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
501
+				 type | PCIE_ATU_FUNC_NUM(func_no));
502
+	rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
503
+				 PCIE_ATU_ENABLE);
504
+
505
+	/*
506
+	 * Make sure ATU enable takes effect before any subsequent config
507
+	 * and I/O accesses.
508
+	 */
509
+	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
510
+		val = rk_pcie_readl_ob_unroll(pci, index,
511
+					      PCIE_ATU_UNR_REGION_CTRL2);
512
+		if (val & PCIE_ATU_ENABLE)
513
+			return;
514
+
515
+		mdelay(LINK_WAIT_IATU);
516
+	}
517
+	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
518
+}
519
+
520
+static void rk_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
521
+				int type, u64 cpu_addr, u64 pci_addr, u32 size)
522
+{
523
+	u32 retries, val;
524
+
525
+	if (pci->ops->cpu_addr_fixup)
526
+		cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
527
+
528
+	if (pci->iatu_unroll_enabled) {
529
+		rk_pcie_prog_outbound_atu_unroll(pci, 0x0, index, type,
530
+						 cpu_addr, pci_addr, size);
531
+		return;
532
+	}
533
+
534
+	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
535
+			   PCIE_ATU_REGION_OUTBOUND | index);
536
+	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
537
+			   lower_32_bits(cpu_addr));
538
+	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
539
+			   upper_32_bits(cpu_addr));
540
+	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
541
+			   lower_32_bits(cpu_addr + size - 1));
542
+	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
543
+			   lower_32_bits(pci_addr));
544
+	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
545
+			   upper_32_bits(pci_addr));
546
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
547
+			   PCIE_ATU_FUNC_NUM(0x0));
548
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
549
+
550
+	/*
551
+	 * Make sure ATU enable takes effect before any subsequent config
552
+	 * and I/O accesses.
553
+	 */
554
+	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
555
+		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
556
+		if (val & PCIE_ATU_ENABLE)
557
+			return;
558
+
559
+		mdelay(LINK_WAIT_IATU);
560
+	}
561
+	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
294562 }
295563 
296564 static int rk_pcie_ep_outbound_atu(struct rk_pcie *rk_pcie,
....@@ -311,7 +579,7 @@
311579 		}
312580 	}
313581 
314
-	dw_pcie_prog_outbound_atu(rk_pcie->pci, free_win, PCIE_ATU_TYPE_MEM,
582
+	rk_pcie_prog_outbound_atu(rk_pcie->pci, free_win, PCIE_ATU_TYPE_MEM,
315583 				  phys_addr, pci_addr, size);
316584 
317585 	if (rk_pcie->in_suspend)
....@@ -368,6 +636,28 @@
368636 	return 0;
369637 }
370638 
639
+#if defined(CONFIG_PCIEASPM)
640
+static void disable_aspm_l1ss(struct rk_pcie *rk_pcie)
641
+{
642
+	u32 val, cfg_link_cap_l1sub;
643
+
644
+	val = dw_pcie_find_ext_capability(rk_pcie->pci, PCI_EXT_CAP_ID_L1SS);
645
+	if (!val) {
646
+		dev_err(rk_pcie->pci->dev, "can't find l1ss cap\n");
647
+
648
+		return;
649
+	}
650
+
651
+	cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
652
+
653
+	val = dw_pcie_readl_dbi(rk_pcie->pci, cfg_link_cap_l1sub);
654
+	val &= ~(PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2 | PCI_L1SS_CAP_L1_PM_SS);
655
+	dw_pcie_writel_dbi(rk_pcie->pci, cfg_link_cap_l1sub, val);
656
+}
657
+#else
658
+static inline void disable_aspm_l1ss(struct rk_pcie *rk_pcie) { return; }
659
+#endif
660
+
371661 static inline void rk_pcie_set_mode(struct rk_pcie *rk_pcie)
372662 {
373663 	switch (rk_pcie->mode) {
....@@ -375,6 +665,14 @@
375665 		rk_pcie_writel_apb(rk_pcie, 0x0, 0xf00000);
376666 		break;
377667 	case RK_PCIE_RC_TYPE:
668
+		if (rk_pcie->supports_clkreq) {
669
+			/* Application is ready to have reference clock removed */
670
+			rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_POWER, 0x00010001);
671
+		} else {
672
+			/* Pull down CLKREQ# to assert the connecting CLOCK_GEN OE */
673
+			rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_POWER, 0x30011000);
674
+			disable_aspm_l1ss(rk_pcie);
675
+		}
378676 		rk_pcie_writel_apb(rk_pcie, 0x0, 0xf00040);
379677 		/*
380678 		 * Disable order rule for CPL can't pass halted P queue.
....@@ -411,8 +709,7 @@
411709 
412710 	if (rk_pcie->is_rk1808) {
413711 		val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG);
414
-		if ((val & (PCIE_PHY_LINKUP | PCIE_DATA_LINKUP)) == 0x3 &&
415
-		    ((val & GENMASK(15, 10)) >> 10) == 0x11)
712
+		if ((val & (PCIE_PHY_LINKUP | PCIE_DATA_LINKUP)) == 0x3)
416713 			return 1;
417714 	} else {
418715 		val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS);
....@@ -425,7 +722,8 @@
425722 
426723 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
427724 {
428
-#if RK_PCIE_DBG
725
+	if (!IS_ENABLED(CONFIG_DEBUG_FS))
726
+		return;
429727 	if (rk_pcie->is_rk1808 == true)
430728 		return;
431729 
....@@ -439,7 +737,6 @@
439737 			   PCIE_CLIENT_DBG_TRANSITION_DATA);
440738 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON,
441739 			   PCIE_CLIENT_DBF_EN);
442
-#endif
443740 }
444741 
445742 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
....@@ -472,6 +769,9 @@
472769 		return 0;
473770 	}
474771 
772
+	/* Rest the device */
773
+	gpiod_set_value_cansleep(rk_pcie->rst_gpio, 0);
774
+
475775 	rk_pcie_disable_ltssm(rk_pcie);
476776 	rk_pcie_link_status_clear(rk_pcie);
477777 	rk_pcie_enable_debug(rk_pcie);
....@@ -502,18 +802,19 @@
502802 	 * PERST and T_PVPERL (Power stable to PERST# inactive) should be a
503803 	 * minimum of 100ms.  See table 2-4 in section 2.6.2 AC, the PCI Express
504804 	 * Card Electromechanical Specification 3.0. So 100ms in total is the min
505
-	 * requuirement here. We add a 1s for sake of hoping everthings work fine.
805
+	 * requuirement here. We add a 200ms by default for sake of hoping everthings
806
+	 * work fine. If it doesn't, please add more in DT node by add rockchip,perst-inactive-ms.
506807 	 */
507
-	msleep(1000);
808
+	msleep(rk_pcie->perst_inactive_ms);
508809 	gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
509810 
510811 	/*
511812 	 * Add this 1ms delay because we observe link is always up stably after it and
512813 	 * could help us save 20ms for scanning devices.
513814 	 */
514
-	 usleep_range(1000, 1100);
815
+	usleep_range(1000, 1100);
515816 
516
-	for (retries = 0; retries < 10; retries++) {
817
+	for (retries = 0; retries < 100; retries++) {
517818 		if (dw_pcie_link_up(pci)) {
518819 			/*
519820 			 * We may be here in case of L0 in Gen1. But if EP is capable
....@@ -522,17 +823,20 @@
522823 			 * that LTSSM max timeout is 24ms per period, we can wait a bit
523824 			 * more for Gen switch.
524825 			 */
525
-			msleep(100);
526
-			dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
527
-				 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
528
-			rk_pcie_debug_dump(rk_pcie);
529
-			return 0;
826
+			msleep(50);
827
+			/* In case link drop after linkup, double check it */
828
+			if (dw_pcie_link_up(pci)) {
829
+				dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
830
+					 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
831
+				rk_pcie_debug_dump(rk_pcie);
832
+				return 0;
833
+			}
530834 		}
531835 
532836 		dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n",
533837 				     rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
534838 		rk_pcie_debug_dump(rk_pcie);
535
-		msleep(1000);
839
+		msleep(20);
536840 	}
537841 
538842 	dev_err(pci->dev, "PCIe Link Fail\n");
....@@ -540,12 +844,23 @@
540844 	return rk_pcie->is_signal_test == true ? 0 : -EINVAL;
541845 }
542846 
847
+static bool rk_pcie_udma_enabled(struct rk_pcie *rk_pcie)
848
+{
849
+	return dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET +
850
+				 PCIE_DMA_CTRL_OFF);
851
+}
852
+
543853 static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie)
544854 {
855
+	if (!rk_pcie_udma_enabled(rk_pcie))
856
+		return 0;
857
+
545858 	rk_pcie->dma_obj = rk_pcie_dma_obj_probe(rk_pcie->pci->dev);
546859 	if (IS_ERR(rk_pcie->dma_obj)) {
547860 		dev_err(rk_pcie->pci->dev, "failed to prepare dma object\n");
548861 		return -EINVAL;
862
+	} else if (rk_pcie->dma_obj) {
863
+		goto out;
549864 	}
550865 
551866 	rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true);
....@@ -553,7 +868,7 @@
553868 		dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
554869 		return -EINVAL;
555870 	}
556
-
871
+out:
557872 	/* Enable client write and read interrupt */
558873 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xc000000);
559874 
....@@ -566,6 +881,76 @@
566881 	return 0;
567882 }
568883 
884
+static int rk_pci_find_resbar_capability(struct rk_pcie *rk_pcie)
885
+{
886
+	u32 header;
887
+	int ttl;
888
+	int start = 0;
889
+	int pos = PCI_CFG_SPACE_SIZE;
890
+	int cap = PCI_EXT_CAP_ID_REBAR;
891
+
892
+	/* minimum 8 bytes per capability */
893
+	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
894
+
895
+	header = dw_pcie_readl_dbi(rk_pcie->pci, pos);
896
+
897
+	/*
898
+	 * If we have no capabilities, this is indicated by cap ID,
899
+	 * cap version and next pointer all being 0.
900
+	 */
901
+	if (header == 0)
902
+		return 0;
903
+
904
+	while (ttl-- > 0) {
905
+		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
906
+			return pos;
907
+
908
+		pos = PCI_EXT_CAP_NEXT(header);
909
+		if (pos < PCI_CFG_SPACE_SIZE)
910
+			break;
911
+
912
+		header = dw_pcie_readl_dbi(rk_pcie->pci, pos);
913
+		if (!header)
914
+			break;
915
+	}
916
+
917
+	return 0;
918
+}
919
+
920
+#ifdef MODULE
921
+void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
922
+{
923
+	int ret;
924
+
925
+	if (pci->ops && pci->ops->write_dbi2) {
926
+		pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
927
+		return;
928
+	}
929
+
930
+	ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
931
+	if (ret)
932
+		dev_err(pci->dev, "write DBI address failed\n");
933
+}
934
+#endif
935
+
936
+static int rk_pcie_ep_set_bar_flag(struct rk_pcie *rk_pcie, enum pci_barno barno, int flags)
937
+{
938
+	enum pci_barno bar = barno;
939
+	u32 reg;
940
+
941
+	reg = PCI_BASE_ADDRESS_0 + (4 * bar);
942
+
943
+	/* Disabled the upper 32bits BAR to make a 64bits bar pair */
944
+	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
945
+		dw_pcie_writel_dbi2(rk_pcie->pci, reg + 4, 0);
946
+
947
+	dw_pcie_writel_dbi(rk_pcie->pci, reg, flags);
948
+	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
949
+		dw_pcie_writel_dbi(rk_pcie->pci, reg + 4, 0);
950
+
951
+	return 0;
952
+}
953
+
569954 static void rk_pcie_ep_setup(struct rk_pcie *rk_pcie)
570955 {
571956 	int ret;
....@@ -573,6 +958,8 @@
573958 	u32 lanes;
574959 	struct device *dev = rk_pcie->pci->dev;
575960 	struct device_node *np = dev->of_node;
961
+	int resbar_base;
962
+	int bar;
576963 
577964 	/* Enable client write and read interrupt */
578965 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xc000000);
....@@ -636,17 +1023,36 @@
6361023 	/* Enable bus master and memory space */
6371024 	dw_pcie_writel_dbi(rk_pcie->pci, PCIE_TYPE0_STATUS_COMMAND_REG, 0x6);
6381025 
639
-	/* Resize BAR0 to 4GB */
640
-	/* bit13-8 set to 6 means 64MB */
641
-	dw_pcie_writel_dbi(rk_pcie->pci, PCIE_RESBAR_CTRL_REG0_REG, 0x600);
1026
+	resbar_base = rk_pci_find_resbar_capability(rk_pcie);
1027
+	if (!resbar_base) {
1028
+		dev_warn(dev, "failed to find resbar_base\n");
1029
+	} else {
1030
+		/* Resize BAR0 to support 512GB, BAR1 to support 8M, BAR2~5 to support 64M */
1031
+		dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x4, 0xfffff0);
1032
+		dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x8, 0x13c0);
1033
+		dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0xc, 0xfffff0);
1034
+		dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x10, 0x3c0);
1035
+		for (bar = 2; bar < 6; bar++) {
1036
+			dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
1037
+			dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
1038
+		}
6421039 
643
-	/* Set shadow BAR0 according 64MB */
644
-	val = rk_pcie->mem_size - 1;
645
-	dw_pcie_writel_dbi(rk_pcie->pci, PCIE_SB_BAR0_MASK_REG, val);
1040
+		/* Set flags */
1041
+		rk_pcie_ep_set_bar_flag(rk_pcie, BAR_0, PCI_BASE_ADDRESS_MEM_TYPE_32);
1042
+		rk_pcie_ep_set_bar_flag(rk_pcie, BAR_1, PCI_BASE_ADDRESS_MEM_TYPE_32);
1043
+		rk_pcie_ep_set_bar_flag(rk_pcie, BAR_2, PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
1044
+		rk_pcie_ep_set_bar_flag(rk_pcie, BAR_4, PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
1045
+	}
6461046 
647
-	/* Set reserved memory address to BAR0 */
648
-	dw_pcie_writel_dbi(rk_pcie->pci, PCIE_TYPE0_BAR0_REG,
649
-			   rk_pcie->mem_start);
1047
+	/* Device id and class id needed for request bar address */
1048
+	dw_pcie_writew_dbi(rk_pcie->pci, PCI_DEVICE_ID, 0x356a);
1049
+	dw_pcie_writew_dbi(rk_pcie->pci, PCI_CLASS_DEVICE, 0x0580);
1050
+
1051
+	/* Set shadow BAR0 */
1052
+	if (rk_pcie->is_rk1808) {
1053
+		val = rk_pcie->mem_size - 1;
1054
+		dw_pcie_writel_dbi(rk_pcie->pci, PCIE_SB_BAR0_MASK_REG, val);
1055
+	}
6501056 }
6511057 
6521058 static int rk_pcie_ep_win_parse(struct rk_pcie *rk_pcie)
....@@ -722,6 +1128,10 @@
7221128 
7231129 	dw_pcie_setup_rc(pp);
7241130 
1131
+	/* Disable BAR0 BAR1 */
1132
+	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0);
1133
+	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0);
1134
+
7251135 	ret = rk_pcie_establish_link(pci);
7261136 
7271137 	if (pp->msi_irq > 0)
....@@ -754,9 +1164,6 @@
7541164 	}
7551165 
7561166 	pp->ops = &rk_pcie_host_ops;
757
-
758
-	if (device_property_read_bool(dev, "msi-map"))
759
-		pp->msi_ext = 1;
7601167 
7611168 	ret = dw_pcie_host_init(pp);
7621169 	if (ret) {
....@@ -796,6 +1203,8 @@
7961203 		return ret;
7971204 	}
7981205 
1206
+	rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
1207
+	rk_pcie->pci->atu_base = rk_pcie->pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
7991208 	rk_pcie->pci->iatu_unroll_enabled = rk_pcie_iatu_unroll_enabled(rk_pcie->pci);
8001209 
8011210 	ret = rk_pcie_ep_atu_init(rk_pcie);
....@@ -812,52 +1221,24 @@
8121221 		return ret;
8131222 	}
8141223 
815
-	return 0;
816
-}
1224
+	if (!rk_pcie_udma_enabled(rk_pcie))
1225
+		return 0;
8171226 
818
-static void rk_pcie_clk_deinit(struct rk_pcie *rk_pcie)
819
-{
820
-	clk_bulk_disable(rk_pcie->clk_cnt, rk_pcie->clks);
821
-	clk_bulk_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
1227
+	return 0;
8221228 }
8231229 
8241230 static int rk_pcie_clk_init(struct rk_pcie *rk_pcie)
8251231 {
8261232 	struct device *dev = rk_pcie->pci->dev;
827
-	struct property *prop;
828
-	const char *name;
829
-	int i = 0, ret, count;
1233
+	int ret;
8301234 
831
-	count = of_property_count_strings(dev->of_node, "clock-names");
832
-	if (count < 1)
1235
+	rk_pcie->clk_cnt = devm_clk_bulk_get_all(dev, &rk_pcie->clks);
1236
+	if (rk_pcie->clk_cnt < 1)
8331237 		return -ENODEV;
8341238 
835
-	rk_pcie->clks = devm_kcalloc(dev, count,
836
-				     sizeof(struct clk_bulk_data),
837
-				     GFP_KERNEL);
838
-	if (!rk_pcie->clks)
839
-		return -ENOMEM;
840
-
841
-	rk_pcie->clk_cnt = count;
842
-
843
-	of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
844
-		rk_pcie->clks[i].id = name;
845
-		if (!rk_pcie->clks[i].id)
846
-			return -ENOMEM;
847
-		i++;
848
-	}
849
-
850
-	ret = devm_clk_bulk_get(dev, count, rk_pcie->clks);
851
-	if (ret)
852
-		return ret;
853
-
854
-	ret = clk_bulk_prepare(count, rk_pcie->clks);
855
-	if (ret)
856
-		return ret;
857
-
858
-	ret = clk_bulk_enable(count, rk_pcie->clks);
1239
+	ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks);
8591240 	if (ret) {
860
-		clk_bulk_unprepare(count, rk_pcie->clks);
1241
+		dev_err(dev, "failed to prepare enable pcie bulk clks: %d\n", ret);
8611242 		return ret;
8621243 	}
8631244 
....@@ -908,6 +1289,10 @@
9081289 		return PTR_ERR(rk_pcie->rst_gpio);
9091290 	}
9101291 
1292
+	if (device_property_read_u32(&pdev->dev, "rockchip,perst-inactive-ms",
1293
+				     &rk_pcie->perst_inactive_ms))
1294
+		rk_pcie->perst_inactive_ms = 200;
1295
+
9111296 	rk_pcie->prsnt_gpio = devm_gpiod_get_optional(&pdev->dev, "prsnt", GPIOD_IN);
9121297 	if (IS_ERR_OR_NULL(rk_pcie->prsnt_gpio))
9131298 		dev_info(&pdev->dev, "invalid prsnt-gpios property in node\n");
....@@ -920,7 +1305,7 @@
9201305 	int ret;
9211306 	struct device *dev = rk_pcie->pci->dev;
9221307 
923
-	rk_pcie->phy = devm_phy_get(dev, "pcie-phy");
1308
+	rk_pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
9241309 	if (IS_ERR(rk_pcie->phy)) {
9251310 		if (PTR_ERR(rk_pcie->phy) != -EPROBE_DEFER)
9261311 			dev_info(dev, "missing phy\n");
....@@ -929,23 +1314,27 @@
9291314 
9301315 	switch (rk_pcie->mode) {
9311316 	case RK_PCIE_RC_TYPE:
932
-		rk_pcie->phy_mode = PHY_MODE_PCIE_RC;
1317
+		rk_pcie->phy_mode = PHY_MODE_PCIE; /* make no sense */
1318
+		rk_pcie->phy_sub_mode = PHY_MODE_PCIE_RC;
9331319 		break;
9341320 	case RK_PCIE_EP_TYPE:
935
-		rk_pcie->phy_mode = PHY_MODE_PCIE_EP;
1321
+		rk_pcie->phy_mode = PHY_MODE_PCIE;
1322
+		rk_pcie->phy_sub_mode = PHY_MODE_PCIE_EP;
9361323 		break;
9371324 	}
9381325 
939
-	ret = phy_set_mode(rk_pcie->phy, rk_pcie->phy_mode);
1326
+	ret = phy_set_mode_ext(rk_pcie->phy, rk_pcie->phy_mode,
1327
+			       rk_pcie->phy_sub_mode);
9401328 	if (ret) {
9411329 		dev_err(dev, "fail to set phy to  mode %s, err %d\n",
942
-			(rk_pcie->phy_mode == PHY_MODE_PCIE_RC) ? "RC" : "EP",
1330
+			(rk_pcie->phy_sub_mode == PHY_MODE_PCIE_RC) ? "RC" : "EP",
9431331 			ret);
9441332 		return ret;
9451333 	}
9461334 
9471335 	if (rk_pcie->bifurcation)
948
-		ret = phy_set_mode(rk_pcie->phy, PHY_MODE_PCIE_BIFURCATION);
1336
+		phy_set_mode_ext(rk_pcie->phy, rk_pcie->phy_mode,
1337
+				 PHY_MODE_PCIE_BIFURCATION);
9491338 
9501339 	ret = phy_init(rk_pcie->phy);
9511340 	if (ret < 0) {
....@@ -954,53 +1343,6 @@
9541343 	}
9551344 
9561345 	phy_power_on(rk_pcie->phy);
957
-
958
-	return 0;
959
-}
960
-
961
-static int rk_pcie_reset_control_release(struct rk_pcie *rk_pcie)
962
-{
963
-	struct device *dev = rk_pcie->pci->dev;
964
-	struct property *prop;
965
-	const char *name;
966
-	int ret, count, i = 0;
967
-
968
-	count = of_property_count_strings(dev->of_node, "reset-names");
969
-	if (count < 1)
970
-		return -ENODEV;
971
-
972
-	rk_pcie->rsts = devm_kcalloc(dev, count,
973
-				     sizeof(struct reset_bulk_data),
974
-				     GFP_KERNEL);
975
-	if (!rk_pcie->rsts)
976
-		return -ENOMEM;
977
-
978
-	of_property_for_each_string(dev->of_node, "reset-names",
979
-				    prop, name) {
980
-		rk_pcie->rsts[i].id = name;
981
-		if (!rk_pcie->rsts[i].id)
982
-			return -ENOMEM;
983
-		i++;
984
-	}
985
-
986
-	for (i = 0; i < count; i++) {
987
-		rk_pcie->rsts[i].rst = devm_reset_control_get_exclusive(dev,
988
-						rk_pcie->rsts[i].id);
989
-		if (IS_ERR_OR_NULL(rk_pcie->rsts[i].rst)) {
990
-			dev_err(dev, "failed to get %s\n",
991
-				rk_pcie->clks[i].id);
992
-			return -PTR_ERR(rk_pcie->rsts[i].rst);
993
-		}
994
-	}
995
-
996
-	for (i = 0; i < count; i++) {
997
-		ret = reset_control_deassert(rk_pcie->rsts[i].rst);
998
-		if (ret) {
999
-			dev_err(dev, "failed to release %s\n",
1000
-				rk_pcie->rsts[i].id);
1001
-			return ret;
1002
-		}
1003
-	}
10041346 
10051347 	return 0;
10061348 }
....@@ -1105,13 +1447,37 @@
11051447 	table->start.chnl = table->chn;
11061448 }
11071449 
1450
+static void rk_pcie_hot_rst_work(struct work_struct *work)
1451
+{
1452
+	struct rk_pcie *rk_pcie = container_of(work, struct rk_pcie, hot_rst_work);
1453
+	u32 val, status;
1454
+	int ret;
1455
+
1456
+	/* Setup command register */
1457
+	val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND);
1458
+	val &= 0xffff0000;
1459
+	val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
1460
+		PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1461
+	dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val);
1462
+
1463
+	if (rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN) {
1464
+		ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_LTSSM_STATUS,
1465
+			 status, ((status & 0x3F) == 0), 100, RK_PCIE_HOTRESET_TMOUT_US);
1466
+		if (ret)
1467
+			dev_err(rk_pcie->pci->dev, "wait for detect quiet failed!\n");
1468
+
1469
+		rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL,
1470
+			(PCIE_LTSSM_APP_DLY2_DONE) | ((PCIE_LTSSM_APP_DLY2_DONE) << 16));
1471
+	}
1472
+}
1473
+
11081474 static irqreturn_t rk_pcie_sys_irq_handler(int irq, void *arg)
11091475 {
11101476 	struct rk_pcie *rk_pcie = arg;
11111477 	u32 chn;
11121478 	union int_status status;
11131479 	union int_clear clears;
1114
-	u32 reg, val;
1480
+	u32 reg;
11151481 
11161482 	status.asdword = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET +
11171483 					   PCIE_DMA_WR_INT_STATUS);
....@@ -1152,14 +1518,8 @@
11521518 	}
11531519 
11541520 	reg = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MISC);
1155
-	if (reg & BIT(2)) {
1156
-		/* Setup command register */
1157
-		val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND);
1158
-		val &= 0xffff0000;
1159
-		val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
1160
-		       PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1161
-		dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val);
1162
-	}
1521
+	if (reg & BIT(2))
1522
+		queue_work(rk_pcie->hot_rst_wq, &rk_pcie->hot_rst_work);
11631523 
11641524 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MISC, reg);
11651525 
....@@ -1215,11 +1575,23 @@
12151575 		.data = &rk3528_pcie_rc_of_data,
12161576 	},
12171577 	{
1578
+		.compatible = "rockchip,rk3562-pcie",
1579
+		.data = &rk3528_pcie_rc_of_data,
1580
+	},
1581
+	{
12181582 		.compatible = "rockchip,rk3568-pcie",
12191583 		.data = &rk_pcie_rc_of_data,
12201584 	},
12211585 	{
12221586 		.compatible = "rockchip,rk3568-pcie-ep",
1587
+		.data = &rk_pcie_ep_of_data,
1588
+	},
1589
+	{
1590
+		.compatible = "rockchip,rk3588-pcie",
1591
+		.data = &rk_pcie_rc_of_data,
1592
+	},
1593
+	{
1594
+		.compatible = "rockchip,rk3588-pcie-ep",
12231595 		.data = &rk_pcie_ep_of_data,
12241596 	},
12251597 	{},
....@@ -1271,7 +1643,8 @@
12711643 
12721644 	/* LTSSM EN ctrl mode */
12731645 	val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL);
1274
-	val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
1646
+	val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN)
1647
+		| ((PCIE_LTSSM_APP_DLY2_EN | PCIE_LTSSM_ENABLE_ENHANCE) << 16);
12751648 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL, val);
12761649 }
12771650 
....@@ -1309,7 +1682,7 @@
13091682 static int rk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
13101683 			    irq_hw_number_t hwirq)
13111684 {
1312
-	irq_set_chip_and_handler(irq, &rk_pcie_legacy_irq_chip, handle_simple_irq);
1685
+	irq_set_chip_and_handler(irq, &rk_pcie_legacy_irq_chip, handle_level_irq);
13131686 	irq_set_chip_data(irq, domain->host_data);
13141687 
13151688 	return 0;
....@@ -1398,41 +1771,6 @@
13981771 	return ret;
13991772 }
14001773 
1401
-static int rk_pci_find_capability(struct rk_pcie *rk_pcie, int cap)
1402
-{
1403
-	u32 header;
1404
-	int ttl;
1405
-	int start = 0;
1406
-	int pos = PCI_CFG_SPACE_SIZE;
1407
-
1408
-	/* minimum 8 bytes per capability */
1409
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1410
-
1411
-	header = dw_pcie_readl_dbi(rk_pcie->pci, pos);
1412
-
1413
-	/*
1414
-	 * If we have no capabilities, this is indicated by cap ID,
1415
-	 * cap version and next pointer all being 0.
1416
-	 */
1417
-	if (header == 0)
1418
-		return 0;
1419
-
1420
-	while (ttl-- > 0) {
1421
-		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
1422
-			return pos;
1423
-
1424
-		pos = PCI_EXT_CAP_NEXT(header);
1425
-		if (pos < PCI_CFG_SPACE_SIZE)
1426
-			break;
1427
-
1428
-		header = dw_pcie_readl_dbi(rk_pcie->pci, pos);
1429
-		if (!header)
1430
-			break;
1431
-	}
1432
-
1433
-	return 0;
1434
-}
1435
-
14361774 #define RAS_DES_EVENT(ss, v) \
14371775 do { \
14381776 	dw_pcie_writel_dbi(pcie->pci, cap_base + 8, v); \
....@@ -1443,8 +1781,27 @@
14431781 {
14441782 	struct rk_pcie *pcie = s->private;
14451783 	int cap_base;
1784
+	u32 val = rk_pcie_readl_apb(pcie, PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN);
1785
+	char *pm;
14461786 
1447
-	cap_base = rk_pci_find_capability(pcie, PCI_EXT_CAP_ID_VNDR);
1787
+	if (val & BIT(6))
1788
+		pm = "In training";
1789
+	else if (val & BIT(5))
1790
+		pm = "L1.2";
1791
+	else if (val & BIT(4))
1792
+		pm = "L1.1";
1793
+	else if (val & BIT(3))
1794
+		pm = "L1";
1795
+	else if (val & BIT(2))
1796
+		pm = "L0";
1797
+	else if (val & 0x3)
1798
+		pm = (val == 0x3) ? "L0s" : (val & BIT(1) ? "RX L0s" : "TX L0s");
1799
+	else
1800
+		pm = "Invalid";
1801
+
1802
+	seq_printf(s, "Common event signal status: 0x%s\n", pm);
1803
+
1804
+	cap_base = dw_pcie_find_ext_capability(pcie->pci, PCI_EXT_CAP_ID_VNDR);
14481805 	if (!cap_base) {
14491806 		dev_err(pcie->pci->dev, "Not able to find RASDES CAP!\n");
14501807 		return 0;
....@@ -1480,7 +1837,6 @@
14801837 
14811838 	return 0;
14821839 }
1483
-
14841840 static int rockchip_pcie_rasdes_open(struct inode *inode, struct file *file)
14851841 {
14861842 	return single_open(file, rockchip_pcie_rasdes_show,
....@@ -1499,7 +1855,7 @@
14991855 	if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
15001856 		return -EFAULT;
15011857 
1502
-	cap_base = rk_pci_find_capability(pcie, PCI_EXT_CAP_ID_VNDR);
1858
+	cap_base = dw_pcie_find_ext_capability(pcie->pci, PCI_EXT_CAP_ID_VNDR);
15031859 	if (!cap_base) {
15041860 		dev_err(pcie->pci->dev, "Not able to find RASDES CAP!\n");
15051861 		return 0;
....@@ -1584,7 +1940,6 @@
15841940 	const struct rk_pcie_of_data *data;
15851941 	enum rk_pcie_device_mode mode;
15861942 	struct device_node *np = pdev->dev.of_node;
1587
-	struct platform_driver *drv = to_platform_driver(dev->driver);
15881943 	u32 val = 0;
15891944 	int irq;
15901945 
....@@ -1638,6 +1993,8 @@
16381993 		}
16391994 	}
16401995 
1996
+	rk_pcie->supports_clkreq = device_property_read_bool(dev, "supports-clkreq");
1997
+
16411998 retry_regulator:
16421999 	/* DON'T MOVE ME: must be enable before phy init */
16432000 	rk_pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
....@@ -1667,11 +2024,14 @@
16672024 		goto disable_vpcie3v3;
16682025 	}
16692026 
1670
-	ret = rk_pcie_reset_control_release(rk_pcie);
1671
-	if (ret) {
1672
-		dev_err(dev, "reset control init failed\n");
2027
+	rk_pcie->rsts = devm_reset_control_array_get_exclusive(dev);
2028
+	if (IS_ERR(rk_pcie->rsts)) {
2029
+		ret = PTR_ERR(rk_pcie->rsts);
2030
+		dev_err(dev, "failed to get reset lines\n");
16732031 		goto disable_phy;
16742032 	}
2033
+
2034
+	reset_control_deassert(rk_pcie->rsts);
16752035 
16762036 	ret = rk_pcie_request_sys_irq(rk_pcie, pdev);
16772037 	if (ret) {
....@@ -1723,17 +2083,39 @@
17232083 		rk_pcie->is_signal_test = true;
17242084 	}
17252085 
1726
-	/* Force into compliance mode */
1727
-	if (device_property_read_bool(dev, "rockchip,compliance-mode")) {
1728
-		val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
1729
-		val |= BIT(4);
1730
-		dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
2086
+	/*
2087
+	 * Force into compliance mode
2088
+	 * comp_prst is a two dimensional array of which the first element
2089
+	 * stands for speed mode, and the second one is preset value encoding:
2090
+	 * [0] 0->SMA tool control the signal switch, 1/2/3 is for manual Gen setting
2091
+	 * [1] transmitter setting for manual Gen setting, valid only if [0] isn't zero.
2092
+	 */
2093
+	if (!device_property_read_u32_array(dev, "rockchip,compliance-mode",
2094
+					    rk_pcie->comp_prst, 2)) {
2095
+		BUG_ON(rk_pcie->comp_prst[0] > 3 || rk_pcie->comp_prst[1] > 10);
2096
+		if (!rk_pcie->comp_prst[0]) {
2097
+			dev_info(dev, "Auto compliance mode for SMA tool.\n");
2098
+		} else {
2099
+			dev_info(dev, "compliance mode for soldered board Gen%d, P%d.\n",
2100
+				 rk_pcie->comp_prst[0], rk_pcie->comp_prst[1]);
2101
+			val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
2102
+			val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12);
2103
+			dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
2104
+		}
17312105 		rk_pcie->is_signal_test = true;
17322106 	}
17332107 
17342108 	/* Skip waiting for training to pass in system PM routine */
17352109 	if (device_property_read_bool(dev, "rockchip,skip-scan-in-resume"))
17362110 		rk_pcie->skip_scan_in_resume = true;
2111
+
2112
+	rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq");
2113
+	if (!rk_pcie->hot_rst_wq) {
2114
+		dev_err(dev, "failed to create hot_rst workqueue\n");
2115
+		ret = -ENOMEM;
2116
+		goto remove_irq_domain;
2117
+	}
2118
+	INIT_WORK(&rk_pcie->hot_rst_work, rk_pcie_hot_rst_work);
17372119 
17382120 	switch (rk_pcie->mode) {
17392121 	case RK_PCIE_RC_TYPE:
....@@ -1748,12 +2130,12 @@
17482130 		return 0;
17492131 
17502132 	if (ret)
1751
-		goto remove_irq_domain;
2133
+		goto remove_rst_wq;
17522134 
17532135 	ret = rk_pcie_init_dma_trx(rk_pcie);
17542136 	if (ret) {
17552137 		dev_err(dev, "failed to add dma extension\n");
1756
-		return ret;
2138
+		goto remove_rst_wq;
17572139 	}
17582140 
17592141 	if (rk_pcie->dma_obj) {
....@@ -1765,13 +2147,15 @@
17652147 		/* hold link reset grant after link-up */
17662148 		ret = rk_pcie_reset_grant_ctrl(rk_pcie, false);
17672149 		if (ret)
1768
-			goto remove_irq_domain;
2150
+			goto remove_rst_wq;
17692151 	}
17702152 
17712153 	dw_pcie_dbi_ro_wr_dis(pci);
17722154 
17732155 	device_init_wakeup(dev, true);
1774
-	drv->driver.pm = &rockchip_dw_pcie_pm_ops;
2156
+
2157
+	/* Enable async system PM for multiports SoC */
2158
+	device_enable_async_suspend(dev);
17752159 
17762160 	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
17772161 		ret = rockchip_pcie_debugfs_init(rk_pcie);
....@@ -1779,7 +2163,7 @@
17792163 			dev_err(dev, "failed to setup debugfs: %d\n", ret);
17802164 
17812165 		/* Enable RASDES Error event by default */
1782
-		val = rk_pci_find_capability(rk_pcie, PCI_EXT_CAP_ID_VNDR);
2166
+		val = dw_pcie_find_ext_capability(rk_pcie->pci, PCI_EXT_CAP_ID_VNDR);
17832167 		if (!val) {
17842168 			dev_err(dev, "Not able to find RASDES CAP!\n");
17852169 			return 0;
....@@ -1791,6 +2175,8 @@
17912175 
17922176 	return 0;
17932177 
2178
+remove_rst_wq:
2179
+	destroy_workqueue(rk_pcie->hot_rst_wq);
17942180 remove_irq_domain:
17952181 	if (rk_pcie->irq_domain)
17962182 		irq_domain_remove(rk_pcie->irq_domain);
....@@ -1798,10 +2184,9 @@
17982184 	phy_power_off(rk_pcie->phy);
17992185 	phy_exit(rk_pcie->phy);
18002186 deinit_clk:
1801
-	rk_pcie_clk_deinit(rk_pcie);
2187
+	clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
18022188 disable_vpcie3v3:
18032189 	rk_pcie_disable_power(rk_pcie);
1804
-
18052190 release_driver:
18062191 	if (IS_ENABLED(CONFIG_PCIE_RK_THREADED_INIT))
18072192 		device_release_driver(dev);
....@@ -1826,12 +2211,147 @@
18262211 	return rk_pcie_really_probe(pdev);
18272212 }
18282213 
2214
+#ifdef CONFIG_PCIEASPM
2215
+static void rk_pcie_downstream_dev_to_d0(struct rk_pcie *rk_pcie, bool enable)
2216
+{
2217
+	struct pcie_port *pp = &rk_pcie->pci->pp;
2218
+	struct pci_bus *child, *root_bus = NULL;
2219
+	struct pci_dev *pdev, *bridge;
2220
+	u32 val;
2221
+
2222
+	list_for_each_entry(child, &pp->bridge->bus->children, node) {
2223
+		/* Bring downstream devices to D3 if they are not already in */
2224
+		if (child->parent == pp->bridge->bus) {
2225
+			root_bus = child;
2226
+			bridge = root_bus->self;
2227
+			break;
2228
+		}
2229
+	}
2230
+
2231
+	if (!root_bus) {
2232
+		dev_err(rk_pcie->pci->dev, "Failed to find downstream devices\n");
2233
+		return;
2234
+	}
2235
+
2236
+	/* Save and restore root bus ASPM */
2237
+	if (enable) {
2238
+		if (rk_pcie->l1ss_ctl1)
2239
+			dw_pcie_writel_dbi(rk_pcie->pci, bridge->l1ss + PCI_L1SS_CTL1, rk_pcie->l1ss_ctl1);
2240
+
2241
+		/* rk_pcie->aspm woule be saved in advance when enable is false */
2242
+		dw_pcie_writel_dbi(rk_pcie->pci, bridge->pcie_cap + PCI_EXP_LNKCTL, rk_pcie->aspm);
2243
+	} else {
2244
+		val = dw_pcie_readl_dbi(rk_pcie->pci, bridge->l1ss + PCI_L1SS_CTL1);
2245
+		if (val & PCI_L1SS_CTL1_L1SS_MASK)
2246
+			rk_pcie->l1ss_ctl1 = val;
2247
+		else
2248
+			rk_pcie->l1ss_ctl1 = 0;
2249
+
2250
+		val = dw_pcie_readl_dbi(rk_pcie->pci, bridge->pcie_cap + PCI_EXP_LNKCTL);
2251
+		rk_pcie->aspm = val & PCI_EXP_LNKCTL_ASPMC;
2252
+		val &= ~(PCI_EXP_LNKCAP_ASPM_L1 | PCI_EXP_LNKCAP_ASPM_L0S);
2253
+		dw_pcie_writel_dbi(rk_pcie->pci, bridge->pcie_cap + PCI_EXP_LNKCTL, val);
2254
+	}
2255
+
2256
+	list_for_each_entry(pdev, &root_bus->devices, bus_list) {
2257
+		if (PCI_SLOT(pdev->devfn) == 0) {
2258
+			if (pci_set_power_state(pdev, PCI_D0))
2259
+				dev_err(rk_pcie->pci->dev,
2260
+					"Failed to transition %s to D3hot state\n",
2261
+					dev_name(&pdev->dev));
2262
+			if (enable) {
2263
+				if (rk_pcie->l1ss_ctl1) {
2264
+					pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, &val);
2265
+					val &= ~PCI_L1SS_CTL1_L1SS_MASK;
2266
+					val |= (rk_pcie->l1ss_ctl1 & PCI_L1SS_CTL1_L1SS_MASK);
2267
+					pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, val);
2268
+				}
2269
+
2270
+				pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
2271
+								   PCI_EXP_LNKCTL_ASPMC, rk_pcie->aspm);
2272
+			} else {
2273
+				pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2274
+			}
2275
+		}
2276
+	}
2277
+}
2278
+#endif
2279
+
18292280 static int __maybe_unused rockchip_dw_pcie_suspend(struct device *dev)
18302281 {
18312282 	struct rk_pcie *rk_pcie = dev_get_drvdata(dev);
1832
-	int ret;
2283
+	int ret = 0, power;
2284
+	struct dw_pcie *pci = rk_pcie->pci;
2285
+	u32 status;
2286
+
2287
+	/*
2288
+	 * This is as per PCI Express Base r5.0 r1.0 May 22-2019,
2289
+	 * 5.2 Link State Power Management (Page #440).
2290
+	 *
2291
+	 * L2/L3 Ready entry negotiations happen while in the L0 state.
2292
+	 * L2/L3 Ready are entered only after the negotiation completes.
2293
+	 *
2294
+	 * The following example sequence illustrates the multi-step Link state
2295
+	 * transition process leading up to entering a system sleep state:
2296
+	 * 1. System software directs all Functions of a Downstream component to D3Hot.
2297
+	 * 2. The Downstream component then initiates the transition of the Link to L1
2298
+	 *    as required.
2299
+	 * 3. System software then causes the Root Complex to broadcast the PME_Turn_Off
2300
+	 *    Message in preparation for removing the main power source.
2301
+	 * 4. This Message causes the subject Link to transition back to L0 in order to
2302
+	 *    send it and to enable the Downstream component to respond with PME_TO_Ack.
2303
+	 * 5. After sending the PME_TO_Ack, the Downstream component initiates the L2/L3
2304
+	 *    Ready transition protocol.
2305
+	 */
2306
+
2307
+	/* 1. All sub-devices are in D3hot by PCIe stack */
2308
+	dw_pcie_dbi_ro_wr_dis(rk_pcie->pci);
18332309 
18342310 	rk_pcie_link_status_clear(rk_pcie);
2311
+
2312
+	/*
2313
+	 * Wlan devices will be shutdown from function driver now, so doing L2 here
2314
+	 * must fail. Skip L2 routine.
2315
+	 */
2316
+	if (rk_pcie->skip_scan_in_resume) {
2317
+		rfkill_get_wifi_power_state(&power);
2318
+		if (!power)
2319
+			goto no_l2;
2320
+	}
2321
+
2322
+	/* 2. Broadcast PME_Turn_Off Message */
2323
+	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_MSG_GEN, PME_TURN_OFF);
2324
+	ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_MSG_GEN,
2325
+				 status, !(status & BIT(4)), 20, RK_PCIE_L2_TMOUT_US);
2326
+	if (ret) {
2327
+		dev_err(dev, "Failed to send PME_Turn_Off\n");
2328
+		goto no_l2;
2329
+	}
2330
+
2331
+	/* 3. Wait for PME_TO_Ack */
2332
+	ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX,
2333
+				 status, status & BIT(9), 20, RK_PCIE_L2_TMOUT_US);
2334
+	if (ret) {
2335
+		dev_err(dev, "Failed to receive PME_TO_Ack\n");
2336
+		goto no_l2;
2337
+	}
2338
+
2339
+	/* 4. Clear PME_TO_Ack and Wait for ready to enter L23 message */
2340
+	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MSG_RX, PME_TO_ACK);
2341
+	ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_POWER,
2342
+				 status, status & READY_ENTER_L23, 20, RK_PCIE_L2_TMOUT_US);
2343
+	if (ret) {
2344
+		dev_err(dev, "Failed to ready to enter L23\n");
2345
+		goto no_l2;
2346
+	}
2347
+
2348
+	/* 5. Check we are in L2 */
2349
+	ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_LTSSM_STATUS,
2350
+				 status, ((status & S_MAX) == S_L2_IDLE), 20, RK_PCIE_L2_TMOUT_US);
2351
+	if (ret)
2352
+		dev_err(pci->dev, "Link isn't in L2 idle!\n");
2353
+
2354
+no_l2:
18352355 	rk_pcie_disable_ltssm(rk_pcie);
18362356 
18372357 	/* make sure assert phy success */
....@@ -1840,7 +2360,9 @@
18402360 	phy_power_off(rk_pcie->phy);
18412361 	phy_exit(rk_pcie->phy);
18422362 
1843
-	clk_bulk_disable(rk_pcie->clk_cnt, rk_pcie->clks);
2363
+	rk_pcie->intx = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY);
2364
+
2365
+	clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
18442366 
18452367 	rk_pcie->in_suspend = true;
18462368 
....@@ -1856,20 +2378,25 @@
18562378 	bool std_rc = rk_pcie->mode == RK_PCIE_RC_TYPE && !rk_pcie->dma_obj;
18572379 	int ret;
18582380 
2381
+	reset_control_assert(rk_pcie->rsts);
2382
+	udelay(10);
2383
+	reset_control_deassert(rk_pcie->rsts);
2384
+
18592385 	ret = rk_pcie_enable_power(rk_pcie);
18602386 	if (ret)
18612387 		return ret;
18622388 
1863
-	ret = clk_bulk_enable(rk_pcie->clk_cnt, rk_pcie->clks);
2389
+	ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks);
18642390 	if (ret) {
1865
-		clk_bulk_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
2391
+		dev_err(dev, "failed to prepare enable pcie bulk clks: %d\n", ret);
18662392 		return ret;
18672393 	}
18682394 
1869
-	ret = phy_set_mode(rk_pcie->phy, rk_pcie->phy_mode);
2395
+	ret = phy_set_mode_ext(rk_pcie->phy, rk_pcie->phy_mode,
2396
+			       rk_pcie->phy_sub_mode);
18702397 	if (ret) {
18712398 		dev_err(dev, "fail to set phy to mode %s, err %d\n",
1872
-			(rk_pcie->phy_mode == PHY_MODE_PCIE_RC) ? "RC" : "EP",
2399
+			(rk_pcie->phy_sub_mode == PHY_MODE_PCIE_RC) ? "RC" : "EP",
18732400 			ret);
18742401 		return ret;
18752402 	}
....@@ -1898,6 +2425,9 @@
18982425 
18992426 	if (std_rc)
19002427 		dw_pcie_setup_rc(&rk_pcie->pci->pp);
2428
+
2429
+	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY,
2430
+			   rk_pcie->intx | 0xffff0000);
19012431 
19022432 	ret = rk_pcie_establish_link(rk_pcie->pci);
19032433 	if (ret) {
....@@ -1937,7 +2467,33 @@
19372467 	return ret;
19382468 }
19392469 
2470
+#ifdef CONFIG_PCIEASPM
2471
+static int rockchip_dw_pcie_prepare(struct device *dev)
2472
+{
2473
+	struct rk_pcie *rk_pcie = dev_get_drvdata(dev);
2474
+
2475
+	dw_pcie_dbi_ro_wr_en(rk_pcie->pci);
2476
+	rk_pcie_downstream_dev_to_d0(rk_pcie, false);
2477
+	dw_pcie_dbi_ro_wr_dis(rk_pcie->pci);
2478
+
2479
+	return 0;
2480
+}
2481
+
2482
+static void rockchip_dw_pcie_complete(struct device *dev)
2483
+{
2484
+	struct rk_pcie *rk_pcie = dev_get_drvdata(dev);
2485
+
2486
+	dw_pcie_dbi_ro_wr_en(rk_pcie->pci);
2487
+	rk_pcie_downstream_dev_to_d0(rk_pcie, true);
2488
+	dw_pcie_dbi_ro_wr_dis(rk_pcie->pci);
2489
+}
2490
+#endif
2491
+
19402492 static const struct dev_pm_ops rockchip_dw_pcie_pm_ops = {
2493
+#ifdef CONFIG_PCIEASPM
2494
+	.prepare = rockchip_dw_pcie_prepare,
2495
+	.complete = rockchip_dw_pcie_complete,
2496
+#endif
19412497 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_dw_pcie_suspend,
19422498 				      rockchip_dw_pcie_resume)
19432499 };
....@@ -1947,10 +2503,12 @@
19472503 		.name	= "rk-pcie",
19482504 		.of_match_table = rk_pcie_of_match,
19492505 		.suppress_bind_attrs = true,
2506
+		.pm = &rockchip_dw_pcie_pm_ops,
19502507 	},
2508
+	.probe = rk_pcie_probe,
19512509 };
19522510 
1953
-module_platform_driver_probe(rk_plat_pcie_driver, rk_pcie_probe);
2511
+module_platform_driver(rk_plat_pcie_driver);
19542512 
19552513 MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com>");
19562514 MODULE_DESCRIPTION("RockChip PCIe Controller driver");