mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/net/phy/icplus.c
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..
@@ -1,13 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0+
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 /*
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  * Driver for ICPlus PHYs
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  *
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  * Copyright (c) 2007 Freescale Semiconductor, Inc.
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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- *
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  */
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 #include <linux/kernel.h>
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 #include <linux/string.h>
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@@ -25,6 +20,7 @@
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 #include <linux/mii.h>
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 #include <linux/ethtool.h>
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 #include <linux/phy.h>
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+#include <linux/property.h>
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24
 
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 #include <asm/io.h>
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 #include <asm/irq.h>
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@@ -36,14 +32,34 @@
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32
 
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 /* IP101A/G - IP1001 */
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 #define IP10XX_SPEC_CTRL_STATUS		16	/* Spec. Control Register */
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-#define IP1001_RXPHASE_SEL		(1<<0)	/* Add delay on RX_CLK */
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-#define IP1001_TXPHASE_SEL		(1<<1)	/* Add delay on TX_CLK */
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+#define IP1001_RXPHASE_SEL		BIT(0)	/* Add delay on RX_CLK */
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+#define IP1001_TXPHASE_SEL		BIT(1)	/* Add delay on TX_CLK */
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 #define IP1001_SPEC_CTRL_STATUS_2	20	/* IP1001 Spec. Control Reg 2 */
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 #define IP1001_APS_ON			11	/* IP1001 APS Mode  bit */
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-#define IP101A_G_APS_ON			2	/* IP101A/G APS Mode bit */
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+#define IP101A_G_APS_ON			BIT(1)	/* IP101A/G APS Mode bit */
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 #define IP101A_G_IRQ_CONF_STATUS	0x11	/* Conf Info IRQ & Status Reg */
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-#define	IP101A_G_IRQ_PIN_USED		(1<<15) /* INTR pin used */
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-#define	IP101A_G_IRQ_DEFAULT		IP101A_G_IRQ_PIN_USED
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+#define	IP101A_G_IRQ_PIN_USED		BIT(15) /* INTR pin used */
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+#define IP101A_G_IRQ_ALL_MASK		BIT(11) /* IRQ's inactive */
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+#define IP101A_G_IRQ_SPEED_CHANGE	BIT(2)
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+#define IP101A_G_IRQ_DUPLEX_CHANGE	BIT(1)
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+#define IP101A_G_IRQ_LINK_CHANGE	BIT(0)
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+
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+#define IP101G_DIGITAL_IO_SPEC_CTRL			0x1d
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+#define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32		BIT(2)
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+
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+/* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
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+ * (pin number 21). The hardware default is RXER (receive error) mode. But it
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+ * can be configured to interrupt mode manually.
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+ */
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+enum ip101gr_sel_intr32 {
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+	IP101GR_SEL_INTR32_KEEP,
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+	IP101GR_SEL_INTR32_INTR,
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+	IP101GR_SEL_INTR32_RXER,
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+};
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+
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+struct ip101a_g_phy_priv {
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+	enum ip101gr_sel_intr32 sel_intr32;
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+};
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63
 
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 static int ip175c_config_init(struct phy_device *phydev)
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 {
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@@ -162,26 +178,6 @@
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 	return 0;
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 }
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180
 
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-static int ip101a_g_config_init(struct phy_device *phydev)
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-{
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-	int c;
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-
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-	c = ip1xx_reset(phydev);
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-	if (c < 0)
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-		return c;
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-
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-	/* INTR pin used: speed/link/duplex will cause an interrupt */
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-	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
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-	if (c < 0)
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-		return c;
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-
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-	/* Enable Auto Power Saving mode */
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-	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
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-	c |= IP101A_G_APS_ON;
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-
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-	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
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-}
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-
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 static int ip175c_read_status(struct phy_device *phydev)
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 {
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 	if (phydev->mdio.addr == 4) /* WAN port */
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@@ -201,6 +197,106 @@
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 	return 0;
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 }
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+static int ip101a_g_probe(struct phy_device *phydev)
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+{
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+	struct device *dev = &phydev->mdio.dev;
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+	struct ip101a_g_phy_priv *priv;
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+
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+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+	if (!priv)
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+		return -ENOMEM;
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+
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+	/* Both functions (RX error and interrupt status) are sharing the same
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+	 * pin on the 32-pin IP101GR, so this is an exclusive choice.
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+	 */
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+	if (device_property_read_bool(dev, "icplus,select-rx-error") &&
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+	    device_property_read_bool(dev, "icplus,select-interrupt")) {
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+		dev_err(dev,
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+			"RXER and INTR mode cannot be selected together\n");
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+		return -EINVAL;
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+	}
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+
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+	if (device_property_read_bool(dev, "icplus,select-rx-error"))
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+		priv->sel_intr32 = IP101GR_SEL_INTR32_RXER;
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+	else if (device_property_read_bool(dev, "icplus,select-interrupt"))
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+		priv->sel_intr32 = IP101GR_SEL_INTR32_INTR;
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+	else
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+		priv->sel_intr32 = IP101GR_SEL_INTR32_KEEP;
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+
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+	phydev->priv = priv;
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+
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+	return 0;
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+}
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+
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+static int ip101a_g_config_init(struct phy_device *phydev)
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+{
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+	struct ip101a_g_phy_priv *priv = phydev->priv;
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+	int err, c;
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+
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+	c = ip1xx_reset(phydev);
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+	if (c < 0)
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+		return c;
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+
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+	/* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
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+	switch (priv->sel_intr32) {
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+	case IP101GR_SEL_INTR32_RXER:
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+		err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
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+				 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0);
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+		if (err < 0)
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+			return err;
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+		break;
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+
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+	case IP101GR_SEL_INTR32_INTR:
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+		err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
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+				 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32,
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+				 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32);
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+		if (err < 0)
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+			return err;
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+		break;
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+
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+	default:
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+		/* Don't touch IP101G_DIGITAL_IO_SPEC_CTRL because it's not
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+		 * documented on IP101A and it's not clear whether this would
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+		 * cause problems.
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+		 * For the 32-pin IP101GR we simply keep the SEL_INTR32
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+		 * configuration as set by the bootloader when not configured
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+		 * to one of the special functions.
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+		 */
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+		break;
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+	}
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+
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+	/* Enable Auto Power Saving mode */
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+	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
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+	c |= IP101A_G_APS_ON;
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+
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+	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
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+}
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+
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+static int ip101a_g_config_intr(struct phy_device *phydev)
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+{
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+	u16 val;
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+
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+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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+		/* INTR pin used: Speed/link/duplex will cause an interrupt */
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+		val = IP101A_G_IRQ_PIN_USED;
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+	else
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+		val = IP101A_G_IRQ_ALL_MASK;
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+
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+	return phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val);
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+}
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+
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+static int ip101a_g_did_interrupt(struct phy_device *phydev)
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+{
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+	int val = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
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+
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+	if (val < 0)
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+		return 0;
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+
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+	return val & (IP101A_G_IRQ_SPEED_CHANGE |
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+		      IP101A_G_IRQ_DUPLEX_CHANGE |
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+		      IP101A_G_IRQ_LINK_CHANGE);
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+}
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+
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 static int ip101a_g_ack_interrupt(struct phy_device *phydev)
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 {
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 	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
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@@ -215,7 +311,7 @@
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 	.phy_id		= 0x02430d80,
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 	.name		= "ICPlus IP175C",
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 	.phy_id_mask	= 0x0ffffff0,
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-	.features	= PHY_BASIC_FEATURES,
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+	/* PHY_BASIC_FEATURES */
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 	.config_init	= &ip175c_config_init,
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 	.config_aneg	= &ip175c_config_aneg,
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 	.read_status	= &ip175c_read_status,
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@@ -225,7 +321,7 @@
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 	.phy_id		= 0x02430d90,
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 	.name		= "ICPlus IP1001",
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 	.phy_id_mask	= 0x0ffffff0,
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-	.features	= PHY_GBIT_FEATURES,
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+	/* PHY_GBIT_FEATURES */
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 	.config_init	= &ip1001_config_init,
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 	.suspend	= genphy_suspend,
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 	.resume		= genphy_resume,
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@@ -233,8 +329,10 @@
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 	.phy_id		= 0x02430c54,
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 	.name		= "ICPlus IP101A/G",
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 	.phy_id_mask	= 0x0ffffff0,
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-	.features	= PHY_BASIC_FEATURES,
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-	.flags		= PHY_HAS_INTERRUPT,
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+	/* PHY_BASIC_FEATURES */
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+	.probe		= ip101a_g_probe,
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+	.config_intr	= ip101a_g_config_intr,
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+	.did_interrupt	= ip101a_g_did_interrupt,
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 	.ack_interrupt	= ip101a_g_ack_interrupt,
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 	.config_init	= &ip101a_g_config_init,
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 	.suspend	= genphy_suspend,