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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/net/phy/bcm-cygnus.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Copyright (C) 2015 Broadcom Corporation
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation version 2.
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- *
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- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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- * kind, whether express or implied; without even the implied warranty
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- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
124  */
135 
146 /* Broadcom Cygnus SoC internal transceivers support. */
....@@ -17,6 +9,10 @@
179 #include <linux/module.h>
1810 #include <linux/netdevice.h>
1911 #include <linux/phy.h>
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+
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+struct bcm_omega_phy_priv {
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+	u64	*stats;
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+};
2016 
2117 /* Broadcom Cygnus Phy specific registers */
2218 #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0  0x91E5 /* VDAL Control register */
....@@ -129,21 +125,162 @@
129125 	return genphy_config_aneg(phydev);
130126 }
131127 
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+static int bcm_omega_config_init(struct phy_device *phydev)
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+{
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+	u8 count, rev;
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+	int ret = 0;
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+
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+	rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
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+
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+	pr_info_once("%s: %s PHY revision: 0x%02x\n",
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+		     phydev_name(phydev), phydev->drv->name, rev);
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+
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+	/* Dummy read to a register to workaround an issue upon reset where the
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+	 * internal inverter may not allow the first MDIO transaction to pass
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+	 * the MDIO management controller and make us return 0xffff for such
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+	 * reads.
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+	 */
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+	phy_read(phydev, MII_BMSR);
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+
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+	switch (rev) {
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+	case 0x00:
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+		ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
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+		break;
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+	default:
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+		break;
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+	}
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+
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+	if (ret)
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+		return ret;
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+
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+	ret = bcm_phy_downshift_get(phydev, &count);
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+	if (ret)
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+		return ret;
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+
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+	/* Only enable EEE if Wirespeed/downshift is disabled */
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+	ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
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+	if (ret)
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+		return ret;
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+
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+	return bcm_phy_enable_apd(phydev, true);
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+}
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+
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+static int bcm_omega_resume(struct phy_device *phydev)
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+{
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+	int ret;
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+
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+	/* Re-apply workarounds coming out suspend/resume */
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+	ret = bcm_omega_config_init(phydev);
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+	if (ret)
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+		return ret;
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+
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+	/* 28nm Gigabit PHYs come out of reset without any half-duplex
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+	 * or "hub" compliant advertised mode, fix that. This does not
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+	 * cause any problems with the PHY library since genphy_config_aneg()
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+	 * gracefully handles auto-negotiated and forced modes.
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+	 */
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+	return genphy_config_aneg(phydev);
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+}
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+
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+static int bcm_omega_get_tunable(struct phy_device *phydev,
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+				 struct ethtool_tunable *tuna, void *data)
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+{
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+	switch (tuna->id) {
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+	case ETHTOOL_PHY_DOWNSHIFT:
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+		return bcm_phy_downshift_get(phydev, (u8 *)data);
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+	default:
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+		return -EOPNOTSUPP;
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+	}
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+}
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+
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+static int bcm_omega_set_tunable(struct phy_device *phydev,
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+				 struct ethtool_tunable *tuna,
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+				 const void *data)
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+{
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+	u8 count = *(u8 *)data;
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+	int ret;
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+
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+	switch (tuna->id) {
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+	case ETHTOOL_PHY_DOWNSHIFT:
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+		ret = bcm_phy_downshift_set(phydev, count);
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+		break;
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+	default:
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+		return -EOPNOTSUPP;
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+	}
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+
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+	if (ret)
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+		return ret;
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+
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+	/* Disable EEE advertisement since this prevents the PHY
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+	 * from successfully linking up, trigger auto-negotiation restart
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+	 * to let the MAC decide what to do.
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+	 */
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+	ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
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+	if (ret)
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+		return ret;
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+
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+	return genphy_restart_aneg(phydev);
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+}
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+
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+static void bcm_omega_get_phy_stats(struct phy_device *phydev,
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+				    struct ethtool_stats *stats, u64 *data)
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+{
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+	struct bcm_omega_phy_priv *priv = phydev->priv;
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+
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+	bcm_phy_get_stats(phydev, priv->stats, stats, data);
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+}
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+
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+static int bcm_omega_probe(struct phy_device *phydev)
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+{
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+	struct bcm_omega_phy_priv *priv;
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+
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+	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
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+	if (!priv)
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+		return -ENOMEM;
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+
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+	phydev->priv = priv;
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+
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+	priv->stats = devm_kcalloc(&phydev->mdio.dev,
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+				   bcm_phy_get_sset_count(phydev), sizeof(u64),
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+				   GFP_KERNEL);
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+	if (!priv->stats)
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+		return -ENOMEM;
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+
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+	return 0;
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+}
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+
132252 static struct phy_driver bcm_cygnus_phy_driver[] = {
133253 {
134254 	.phy_id        = PHY_ID_BCM_CYGNUS,
135255 	.phy_id_mask   = 0xfffffff0,
136256 	.name          = "Broadcom Cygnus PHY",
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-	.features      = PHY_GBIT_FEATURES,
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+	/* PHY_GBIT_FEATURES */
138258 	.config_init   = bcm_cygnus_config_init,
139259 	.ack_interrupt = bcm_phy_ack_intr,
140260 	.config_intr   = bcm_phy_config_intr,
141261 	.suspend       = genphy_suspend,
142262 	.resume        = bcm_cygnus_resume,
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-} };
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+}, {
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+	.phy_id		= PHY_ID_BCM_OMEGA,
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+	.phy_id_mask	= 0xfffffff0,
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+	.name		= "Broadcom Omega Combo GPHY",
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+	/* PHY_GBIT_FEATURES */
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+	.flags		= PHY_IS_INTERNAL,
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+	.config_init	= bcm_omega_config_init,
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+	.suspend	= genphy_suspend,
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+	.resume		= bcm_omega_resume,
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+	.get_tunable	= bcm_omega_get_tunable,
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+	.set_tunable	= bcm_omega_set_tunable,
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+	.get_sset_count	= bcm_phy_get_sset_count,
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+	.get_strings	= bcm_phy_get_strings,
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+	.get_stats	= bcm_omega_get_phy_stats,
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+	.probe		= bcm_omega_probe,
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+}
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+};
144280 
145281 static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
146282 	{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },
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+	{ PHY_ID_BCM_OMEGA, 0xfffffff0, },
147284 	{ }
148285 };
149286 MODULE_DEVICE_TABLE(mdio, bcm_cygnus_phy_tbl);