~hc/RK356X_SDK_RELEASE.git

..	..	@@ -12,19 +12,28 @@
12	12	#define BNXT_H
13	13
14	14	#define DRV_MODULE_NAME "bnxt_en"
15		-#define DRV_MODULE_VERSION "1.9.2"
16	15
	16	+/* DO NOT CHANGE DRV_VER_* defines
	17	+ * FIXME: Delete them
	18	+ */
17	19	#define DRV_VER_MAJ 1
18		-#define DRV_VER_MIN 9
19		-#define DRV_VER_UPD 2
	20	+#define DRV_VER_MIN 10
	21	+#define DRV_VER_UPD 1
20	22
21	23	#include <linux/interrupt.h>
22	24	#include <linux/rhashtable.h>
	25	+#include <linux/crash_dump.h>
23	26	#include <net/devlink.h>
24	27	#include <net/dst_metadata.h>
25		-#include <net/switchdev.h>
26	28	#include <net/xdp.h>
27		-#include <linux/net_dim.h>
	29	+#include <linux/dim.h>
	30	+#ifdef CONFIG_TEE_BNXT_FW
	31	+#include <linux/firmware/broadcom/tee_bnxt_fw.h>
	32	+#endif
	33	+
	34	+extern struct list_head bnxt_block_cb_list;
	35	+
	36	+struct page_pool;
28	37
29	38	struct tx_bd {
30	39	__le32 tx_bd_len_flags_type;
..	..	@@ -111,6 +120,7 @@
111	120	#define CMP_TYPE_RX_AGG_CMP 18
112	121	#define CMP_TYPE_RX_L2_TPA_START_CMP 19
113	122	#define CMP_TYPE_RX_L2_TPA_END_CMP 21
	123	+ #define CMP_TYPE_RX_TPA_AGG_CMP 22
114	124	#define CMP_TYPE_STATUS_CMP 32
115	125	#define CMP_TYPE_REMOTE_DRIVER_REQ 34
116	126	#define CMP_TYPE_REMOTE_DRIVER_RESP 36
..	..	@@ -261,14 +271,21 @@
261	271	u32 rx_agg_cmp_opaque;
262	272	__le32 rx_agg_cmp_v;
263	273	#define RX_AGG_CMP_V (1 << 0)
	274	+ #define RX_AGG_CMP_AGG_ID (0xffff << 16)
	275	+ #define RX_AGG_CMP_AGG_ID_SHIFT 16
264	276	__le32 rx_agg_cmp_unused;
265	277	};
	278	+
	279	+#define TPA_AGG_AGG_ID(rx_agg) \
	280	+ ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
	281	+ RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
266	282
267	283	struct rx_tpa_start_cmp {
268	284	__le32 rx_tpa_start_cmp_len_flags_type;
269	285	#define RX_TPA_START_CMP_TYPE (0x3f << 0)
270	286	#define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
271	287	#define RX_TPA_START_CMP_FLAGS_SHIFT 6
	288	+ #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
272	289	#define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
273	290	#define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
274	291	#define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
..	..	@@ -276,6 +293,7 @@
276	293	#define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
277	294	#define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
278	295	#define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
	296	+ #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
279	297	#define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
280	298	#define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
281	299	#define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
..	..	@@ -289,6 +307,8 @@
289	307	#define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
290	308	#define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
291	309	#define RX_TPA_START_CMP_AGG_ID_SHIFT 25
	310	+ #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
	311	+ #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
292	312
293	313	__le32 rx_tpa_start_cmp_rss_hash;
294	314	};
..	..	@@ -306,6 +326,14 @@
306	326	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
307	327	RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
308	328
	329	+#define TPA_START_AGG_ID_P5(rx_tpa_start) \
	330	+ ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
	331	+ RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
	332	+
	333	+#define TPA_START_ERROR(rx_tpa_start) \
	334	+ ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
	335	+ cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
	336	+
309	337	struct rx_tpa_start_cmp_ext {
310	338	__le32 rx_tpa_start_cmp_flags2;
311	339	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
..	..	@@ -313,10 +341,20 @@
313	341	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
314	342	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
315	343	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
	344	+ #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
	345	+ #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
	346	+ #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
	347	+ #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
	348	+ #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
316	349
317	350	__le32 rx_tpa_start_cmp_metadata;
318	351	__le32 rx_tpa_start_cmp_cfa_code_v2;
319	352	#define RX_TPA_START_CMP_V2 (0x1 << 0)
	353	+ #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
	354	+ #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
	355	+ #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
	356	+ #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
	357	+ #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
320	358	#define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
321	359	#define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
322	360	__le32 rx_tpa_start_cmp_hdr_info;
..	..	@@ -329,6 +367,11 @@
329	367	#define TPA_START_IS_IPV6(rx_tpa_start) \
330	368	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
331	369	cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
	370	+
	371	+#define TPA_START_ERROR_CODE(rx_tpa_start) \
	372	+ ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
	373	+ RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
	374	+ RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
332	375
333	376	struct rx_tpa_end_cmp {
334	377	__le32 rx_tpa_end_cmp_len_flags_type;
..	..	@@ -359,6 +402,8 @@
359	402	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
360	403	#define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
361	404	#define RX_TPA_END_CMP_AGG_ID_SHIFT 25
	405	+ #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
	406	+ #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
362	407
363	408	__le32 rx_tpa_end_cmp_tsdelta;
364	409	#define RX_TPA_END_GRO_TS (0x1 << 31)
..	..	@@ -367,6 +412,18 @@
367	412	#define TPA_END_AGG_ID(rx_tpa_end) \
368	413	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
369	414	RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
	415	+
	416	+#define TPA_END_AGG_ID_P5(rx_tpa_end) \
	417	+ ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
	418	+ RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
	419	+
	420	+#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
	421	+ ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
	422	+ RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
	423	+
	424	+#define TPA_END_AGG_BUFS(rx_tpa_end) \
	425	+ ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
	426	+ RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
370	427
371	428	#define TPA_END_TPA_SEGS(rx_tpa_end) \
372	429	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
..	..	@@ -387,6 +444,10 @@
387	444	struct rx_tpa_end_cmp_ext {
388	445	__le32 rx_tpa_end_cmp_dup_acks;
389	446	#define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
	447	+ #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
	448	+ #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
	449	+ #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
	450	+ #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
390	451
391	452	__le32 rx_tpa_end_cmp_seg_len;
392	453	#define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
..	..	@@ -394,7 +455,13 @@
394	455	__le32 rx_tpa_end_cmp_errors_v2;
395	456	#define RX_TPA_END_CMP_V2 (0x1 << 0)
396	457	#define RX_TPA_END_CMP_ERRORS (0x3 << 1)
	458	+ #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
397	459	#define RX_TPA_END_CMPL_ERRORS_SHIFT 1
	460	+ #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
	461	+ #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
	462	+ #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
	463	+ #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
	464	+ #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
398	465
399	466	u32 rx_tpa_end_cmp_start_opaque;
400	467	};
..	..	@@ -402,6 +469,41 @@
402	469	#define TPA_END_ERRORS(rx_tpa_end_ext) \
403	470	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
404	471	cpu_to_le32(RX_TPA_END_CMP_ERRORS))
	472	+
	473	+#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
	474	+ ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
	475	+ RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
	476	+ RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
	477	+
	478	+#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
	479	+ ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
	480	+ RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
	481	+
	482	+#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
	483	+ (((data1) & \
	484	+ ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
	485	+ ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
	486	+
	487	+#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
	488	+ !!((data1) & \
	489	+ ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
	490	+
	491	+#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
	492	+ !!((data1) & \
	493	+ ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
	494	+
	495	+struct nqe_cn {
	496	+ __le16 type;
	497	+ #define NQ_CN_TYPE_MASK 0x3fUL
	498	+ #define NQ_CN_TYPE_SFT 0
	499	+ #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
	500	+ #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
	501	+ __le16 reserved16;
	502	+ __le32 cq_handle_low;
	503	+ __le32 v;
	504	+ #define NQ_CN_V 0x1UL
	505	+ __le32 cq_handle_high;
	506	+};
405	507
406	508	#define DB_IDX_MASK 0xffffff
407	509	#define DB_IDX_VALID (0x1 << 26)
..	..	@@ -415,6 +517,28 @@
415	517
416	518	#define BNXT_MIN_ROCE_CP_RINGS 2
417	519	#define BNXT_MIN_ROCE_STAT_CTXS 1
	520	+
	521	+/* 64-bit doorbell */
	522	+#define DBR_INDEX_MASK 0x0000000000ffffffULL
	523	+#define DBR_XID_MASK 0x000fffff00000000ULL
	524	+#define DBR_XID_SFT 32
	525	+#define DBR_PATH_L2 (0x1ULL << 56)
	526	+#define DBR_TYPE_SQ (0x0ULL << 60)
	527	+#define DBR_TYPE_RQ (0x1ULL << 60)
	528	+#define DBR_TYPE_SRQ (0x2ULL << 60)
	529	+#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
	530	+#define DBR_TYPE_CQ (0x4ULL << 60)
	531	+#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
	532	+#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
	533	+#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
	534	+#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
	535	+#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
	536	+#define DBR_TYPE_NQ (0xaULL << 60)
	537	+#define DBR_TYPE_NQ_ARM (0xbULL << 60)
	538	+#define DBR_TYPE_NULL (0xfULL << 60)
	539	+
	540	+#define DB_PF_OFFSET_P5 0x10000
	541	+#define DB_VF_OFFSET_P5 0x4000
418	542
419	543	#define INVALID_HW_RING_ID ((u16)-1)
420	544
..	..	@@ -445,7 +569,8 @@
445	569	#define BNXT_MAX_MTU 9500
446	570	#define BNXT_MAX_PAGE_MODE_MTU \
447	571	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
448		- XDP_PACKET_HEADROOM)
	572	+ XDP_PACKET_HEADROOM - \
	573	+ SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
449	574
450	575	#define BNXT_MIN_PKT_SIZE 52
451	576
..	..	@@ -453,6 +578,9 @@
453	578	#define BNXT_DEFAULT_TX_RING_SIZE 511
454	579
455	580	#define MAX_TPA 64
	581	+#define MAX_TPA_P5 256
	582	+#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
	583	+#define MAX_TPA_SEGS_P5 0x3f
456	584
457	585	#if (BNXT_PAGE_SHIFT == 16)
458	586	#define MAX_RX_PAGES 1
..	..	@@ -510,6 +638,9 @@
510	638	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
511	639	!((raw_cons) & bp->cp_bit))
512	640
	641	+#define NQ_CMP_VALID(nqcmp, raw_cons) \
	642	+ (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
	643	+
513	644	#define TX_CMP_TYPE(txcmp) \
514	645	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
515	646
..	..	@@ -530,15 +661,10 @@
530	661	#define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
531	662	#define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
532	663	#define DFLT_HWRM_CMD_TIMEOUT 500
	664	+#define SHORT_HWRM_CMD_TIMEOUT 20
533	665	#define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
534	666	#define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
535	667	#define HWRM_COREDUMP_TIMEOUT ((HWRM_CMD_TIMEOUT) * 12)
536		-#define HWRM_RESP_ERR_CODE_MASK 0xffff
537		-#define HWRM_RESP_LEN_OFFSET 4
538		-#define HWRM_RESP_LEN_MASK 0xffff0000
539		-#define HWRM_RESP_LEN_SFT 16
540		-#define HWRM_RESP_VALID_MASK 0xff000000
541		-#define HWRM_SEQ_ID_INVALID -1
542	668	#define BNXT_HWRM_REQ_MAX_SIZE 128
543	669	#define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
544	670	BNXT_HWRM_REQ_MAX_SIZE)
..	..	@@ -556,15 +682,24 @@
556	682
557	683	#define HWRM_VALID_BIT_DELAY_USEC 150
558	684
559		-#define BNXT_RX_EVENT 1
560		-#define BNXT_AGG_EVENT 2
561		-#define BNXT_TX_EVENT 4
	685	+#define BNXT_HWRM_CHNL_CHIMP 0
	686	+#define BNXT_HWRM_CHNL_KONG 1
	687	+
	688	+#define BNXT_RX_EVENT 1
	689	+#define BNXT_AGG_EVENT 2
	690	+#define BNXT_TX_EVENT 4
	691	+#define BNXT_REDIRECT_EVENT 8
562	692
563	693	struct bnxt_sw_tx_bd {
564		- struct sk_buff *skb;
	694	+ union {
	695	+ struct sk_buff *skb;
	696	+ struct xdp_frame *xdpf;
	697	+ };
565	698	DEFINE_DMA_UNMAP_ADDR(mapping);
	699	+ DEFINE_DMA_UNMAP_LEN(len);
566	700	u8 is_gso;
567	701	u8 is_push;
	702	+ u8 action;
568	703	union {
569	704	unsigned short nr_frags;
570	705	u16 rx_prod;
..	..	@@ -583,9 +718,17 @@
583	718	dma_addr_t mapping;
584	719	};
585	720
586		-struct bnxt_ring_struct {
	721	+struct bnxt_ring_mem_info {
587	722	int nr_pages;
588	723	int page_size;
	724	+ u16 flags;
	725	+#define BNXT_RMEM_VALID_PTE_FLAG 1
	726	+#define BNXT_RMEM_RING_PTE_FLAG 2
	727	+#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
	728	+
	729	+ u16 depth;
	730	+ u8 init_val;
	731	+
589	732	void **pg_arr;
590	733	dma_addr_t *dma_arr;
591	734
..	..	@@ -594,12 +737,17 @@
594	737
595	738	int vmem_size;
596	739	void **vmem;
	740	+};
	741	+
	742	+struct bnxt_ring_struct {
	743	+ struct bnxt_ring_mem_info ring_mem;
597	744
598	745	u16 fw_ring_id; /* Ring id filled by Chimp FW */
599	746	union {
600	747	u16 grp_idx;
601	748	u16 map_idx; /* Used by cmpl rings */
602	749	};
	750	+ u32 handle;
603	751	u8 queue_id;
604	752	};
605	753
..	..	@@ -615,12 +763,21 @@
615	763	u32 data[25];
616	764	};
617	765
	766	+struct bnxt_db_info {
	767	+ void __iomem *doorbell;
	768	+ union {
	769	+ u64 db_key64;
	770	+ u32 db_key32;
	771	+ };
	772	+};
	773	+
618	774	struct bnxt_tx_ring_info {
619	775	struct bnxt_napi *bnapi;
620	776	u16 tx_prod;
621	777	u16 tx_cons;
622	778	u16 txq_index;
623		- void __iomem *tx_doorbell;
	779	+ u8 kick_pending;
	780	+ struct bnxt_db_info tx_db;
624	781
625	782	struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
626	783	struct bnxt_sw_tx_bd *tx_buf_ring;
..	..	@@ -635,6 +792,42 @@
635	792	u32 dev_state;
636	793
637	794	struct bnxt_ring_struct tx_ring_struct;
	795	+};
	796	+
	797	+#define BNXT_LEGACY_COAL_CMPL_PARAMS \
	798	+ (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN \| \
	799	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX \| \
	800	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET \| \
	801	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE \| \
	802	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \| \
	803	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \| \
	804	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \| \
	805	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \| \
	806	+ RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
	807	+
	808	+#define BNXT_COAL_CMPL_ENABLES \
	809	+ (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR \| \
	810	+ RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR \| \
	811	+ RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX \| \
	812	+ RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
	813	+
	814	+#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
	815	+ RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
	816	+
	817	+#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
	818	+ RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
	819	+
	820	+struct bnxt_coal_cap {
	821	+ u32 cmpl_params;
	822	+ u32 nq_params;
	823	+ u16 num_cmpl_dma_aggr_max;
	824	+ u16 num_cmpl_dma_aggr_during_int_max;
	825	+ u16 cmpl_aggr_dma_tmr_max;
	826	+ u16 cmpl_aggr_dma_tmr_during_int_max;
	827	+ u16 int_lat_tmr_min_max;
	828	+ u16 int_lat_tmr_max_max;
	829	+ u16 num_cmpl_aggr_int_max;
	830	+ u16 timer_units;
638	831	};
639	832
640	833	struct bnxt_coal {
..	..	@@ -673,6 +866,15 @@
673	866	((hdr_info) & 0x1ff)
674	867
675	868	u16 cfa_code; /* cfa_code in TPA start compl */
	869	+ u8 agg_count;
	870	+ struct rx_agg_cmp *agg_arr;
	871	+};
	872	+
	873	+#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
	874	+
	875	+struct bnxt_tpa_idx_map {
	876	+ u16 agg_id_tbl[1024];
	877	+ unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
676	878	};
677	879
678	880	struct bnxt_rx_ring_info {
..	..	@@ -681,8 +883,8 @@
681	883	u16 rx_agg_prod;
682	884	u16 rx_sw_agg_prod;
683	885	u16 rx_next_cons;
684		- void __iomem *rx_doorbell;
685		- void __iomem *rx_agg_doorbell;
	886	+ struct bnxt_db_info rx_db;
	887	+ struct bnxt_db_info rx_agg_db;
686	888
687	889	struct bpf_prog *xdp_prog;
688	890
..	..	@@ -702,33 +904,71 @@
702	904	dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
703	905
704	906	struct bnxt_tpa_info *rx_tpa;
	907	+ struct bnxt_tpa_idx_map *rx_tpa_idx_map;
705	908
706	909	struct bnxt_ring_struct rx_ring_struct;
707	910	struct bnxt_ring_struct rx_agg_ring_struct;
708	911	struct xdp_rxq_info xdp_rxq;
	912	+ struct page_pool *page_pool;
	913	+};
	914	+
	915	+struct bnxt_rx_sw_stats {
	916	+ u64 rx_l4_csum_errors;
	917	+ u64 rx_resets;
	918	+ u64 rx_buf_errors;
	919	+};
	920	+
	921	+struct bnxt_cmn_sw_stats {
	922	+ u64 missed_irqs;
	923	+};
	924	+
	925	+struct bnxt_sw_stats {
	926	+ struct bnxt_rx_sw_stats rx;
	927	+ struct bnxt_cmn_sw_stats cmn;
	928	+};
	929	+
	930	+struct bnxt_stats_mem {
	931	+ u64 *sw_stats;
	932	+ u64 *hw_masks;
	933	+ void *hw_stats;
	934	+ dma_addr_t hw_stats_map;
	935	+ int len;
709	936	};
710	937
711	938	struct bnxt_cp_ring_info {
	939	+ struct bnxt_napi *bnapi;
712	940	u32 cp_raw_cons;
713		- void __iomem *cp_doorbell;
	941	+ struct bnxt_db_info cp_db;
	942	+
	943	+ u8 had_work_done:1;
	944	+ u8 has_more_work:1;
	945	+
	946	+ u32 last_cp_raw_cons;
714	947
715	948	struct bnxt_coal rx_ring_coal;
716	949	u64 rx_packets;
717	950	u64 rx_bytes;
718	951	u64 event_ctr;
719	952
720		- struct net_dim dim;
	953	+ struct dim dim;
721	954
722		- struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
	955	+ union {
	956	+ struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
	957	+ struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
	958	+ };
723	959
724	960	dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
725	961
726		- struct ctx_hw_stats *hw_stats;
727		- dma_addr_t hw_stats_map;
	962	+ struct bnxt_stats_mem stats;
728	963	u32 hw_stats_ctx_id;
729		- u64 rx_l4_csum_errors;
	964	+
	965	+ struct bnxt_sw_stats sw_stats;
730	966
731	967	struct bnxt_ring_struct cp_ring_struct;
	968	+
	969	+ struct bnxt_cp_ring_info *cp_ring_arr[2];
	970	+#define BNXT_RX_HDL 0
	971	+#define BNXT_TX_HDL 1
732	972	};
733	973
734	974	struct bnxt_napi {
..	..	@@ -742,6 +982,9 @@
742	982
743	983	void (tx_int)(struct bnxt , struct bnxt_napi *,
744	984	int);
	985	+ int tx_pkts;
	986	+ u8 events;
	987	+
745	988	u32 flags;
746	989	#define BNXT_NAPI_FLAG_XDP 0x1
747	990
..	..	@@ -761,6 +1004,7 @@
761	1004	#define HWRM_RING_ALLOC_RX 0x2
762	1005	#define HWRM_RING_ALLOC_AGG 0x4
763	1006	#define HWRM_RING_ALLOC_CMPL 0x8
	1007	+#define HWRM_RING_ALLOC_NQ 0x10
764	1008
765	1009	#define INVALID_STATS_CTX_ID -1
766	1010
..	..	@@ -774,7 +1018,7 @@
774	1018
775	1019	struct bnxt_vnic_info {
776	1020	u16 fw_vnic_id; /* returned by Chimp during alloc */
777		-#define BNXT_MAX_CTX_PER_VNIC 2
	1021	+#define BNXT_MAX_CTX_PER_VNIC 8
778	1022	u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
779	1023	u16 fw_l2_ctx_id;
780	1024	#define BNXT_MAX_UC_ADDRS 4
..	..	@@ -788,6 +1032,15 @@
788	1032	__le16 *rss_table;
789	1033	dma_addr_t rss_hash_key_dma_addr;
790	1034	u64 *rss_hash_key;
	1035	+ int rss_table_size;
	1036	+#define BNXT_RSS_TABLE_ENTRIES_P5 64
	1037	+#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
	1038	+#define BNXT_RSS_TABLE_MAX_TBL_P5 8
	1039	+#define BNXT_MAX_RSS_TABLE_SIZE_P5 \
	1040	+ (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
	1041	+#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
	1042	+ (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
	1043	+
791	1044	u32 rx_mask;
792	1045
793	1046	u8 *mc_list;
..	..	@@ -827,7 +1080,10 @@
827	1080	u16 resv_vnics;
828	1081	u16 min_stat_ctxs;
829	1082	u16 max_stat_ctxs;
	1083	+ u16 resv_stat_ctxs;
	1084	+ u16 max_nqs;
830	1085	u16 max_irqs;
	1086	+ u16 resv_irqs;
831	1087	};
832	1088
833	1089	#if defined(CONFIG_BNXT_SRIOV)
..	..	@@ -838,6 +1094,7 @@
838	1094	* stored by PF.
839	1095	*/
840	1096	u16 vlan;
	1097	+ u16 func_qcfg_flags;
841	1098	u32 flags;
842	1099	#define BNXT_VF_QOS 0x1
843	1100	#define BNXT_VF_SPOOFCHK 0x2
..	..	@@ -859,6 +1116,7 @@
859	1116	u8 mac_addr[ETH_ALEN];
860	1117	u32 first_vf_id;
861	1118	u16 active_vfs;
	1119	+ u16 registered_vfs;
862	1120	u16 max_vfs;
863	1121	u32 max_encap_records;
864	1122	u32 max_decap_records;
..	..	@@ -902,7 +1160,10 @@
902	1160	#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
903	1161	#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
904	1162	u8 wire_speed;
905		- u8 loop_back;
	1163	+ u8 phy_state;
	1164	+#define BNXT_PHY_STATE_ENABLED 0
	1165	+#define BNXT_PHY_STATE_DISABLED 1
	1166	+
906	1167	u8 link_up;
907	1168	u8 duplex;
908	1169	#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
..	..	@@ -938,6 +1199,7 @@
938	1199	#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
939	1200	#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
940	1201	u16 support_speeds;
	1202	+ u16 support_pam4_speeds;
941	1203	u16 auto_link_speeds; /* fw adv setting */
942	1204	#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
943	1205	#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
..	..	@@ -949,24 +1211,51 @@
949	1211	#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
950	1212	#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
951	1213	#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
	1214	+ u16 auto_pam4_link_speeds;
	1215	+#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
	1216	+#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
	1217	+#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
952	1218	u16 support_auto_speeds;
	1219	+ u16 support_pam4_auto_speeds;
953	1220	u16 lp_auto_link_speeds;
	1221	+ u16 lp_auto_pam4_link_speeds;
954	1222	u16 force_link_speed;
	1223	+ u16 force_pam4_link_speed;
955	1224	u32 preemphasis;
956	1225	u8 module_status;
	1226	+ u8 active_fec_sig_mode;
957	1227	u16 fec_cfg;
	1228	+#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
	1229	+#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
958	1230	#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
	1231	+#define BNXT_FEC_ENC_BASE_R_CAP \
	1232	+ PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
959	1233	#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
960		-#define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
	1234	+#define BNXT_FEC_ENC_RS_CAP \
	1235	+ PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
	1236	+#define BNXT_FEC_ENC_LLRS_CAP \
	1237	+ (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED \| \
	1238	+ PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
	1239	+#define BNXT_FEC_ENC_RS \
	1240	+ (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED \| \
	1241	+ PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED \| \
	1242	+ PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
	1243	+#define BNXT_FEC_ENC_LLRS \
	1244	+ (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED \| \
	1245	+ PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
961	1246
962	1247	/* copy of requested setting from ethtool cmd */
963	1248	u8 autoneg;
964	1249	#define BNXT_AUTONEG_SPEED 1
965	1250	#define BNXT_AUTONEG_FLOW_CTRL 2
	1251	+ u8 req_signal_mode;
	1252	+#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
	1253	+#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
966	1254	u8 req_duplex;
967	1255	u8 req_flow_ctrl;
968	1256	u16 req_link_speed;
969	1257	u16 advertising; /* user adv setting */
	1258	+ u16 advertising_pam4;
970	1259	bool force_link_chng;
971	1260
972	1261	bool phy_retry;
..	..	@@ -977,6 +1266,49 @@
977	1266	*/
978	1267	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
979	1268	};
	1269	+
	1270	+#define BNXT_FEC_RS544_ON \
	1271	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE \| \
	1272	+ PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
	1273	+
	1274	+#define BNXT_FEC_RS544_OFF \
	1275	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE \| \
	1276	+ PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
	1277	+
	1278	+#define BNXT_FEC_RS272_ON \
	1279	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE \| \
	1280	+ PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
	1281	+
	1282	+#define BNXT_FEC_RS272_OFF \
	1283	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE \| \
	1284	+ PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
	1285	+
	1286	+#define BNXT_PAM4_SUPPORTED(link_info) \
	1287	+ ((link_info)->support_pam4_speeds)
	1288	+
	1289	+#define BNXT_FEC_RS_ON(link_info) \
	1290	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE \| \
	1291	+ PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE \| \
	1292	+ (BNXT_PAM4_SUPPORTED(link_info) ? \
	1293	+ (BNXT_FEC_RS544_ON \| BNXT_FEC_RS272_OFF) : 0))
	1294	+
	1295	+#define BNXT_FEC_LLRS_ON \
	1296	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE \| \
	1297	+ PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE \| \
	1298	+ BNXT_FEC_RS272_ON \| BNXT_FEC_RS544_OFF)
	1299	+
	1300	+#define BNXT_FEC_RS_OFF(link_info) \
	1301	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE \| \
	1302	+ (BNXT_PAM4_SUPPORTED(link_info) ? \
	1303	+ (BNXT_FEC_RS544_OFF \| BNXT_FEC_RS272_OFF) : 0))
	1304	+
	1305	+#define BNXT_FEC_BASE_R_ON(link_info) \
	1306	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE \| \
	1307	+ BNXT_FEC_RS_OFF(link_info))
	1308	+
	1309	+#define BNXT_FEC_ALL_OFF(link_info) \
	1310	+ (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE \| \
	1311	+ BNXT_FEC_RS_OFF(link_info))
980	1312
981	1313	#define BNXT_MAX_QUEUE 8
982	1314
..	..	@@ -1004,19 +1336,39 @@
1004	1336	struct bnxt_test_info {
1005	1337	u8 offline_mask;
1006	1338	u8 flags;
1007		-#define BNXT_TEST_FL_EXT_LPBK 0x1
	1339	+#define BNXT_TEST_FL_EXT_LPBK 0x1
	1340	+#define BNXT_TEST_FL_AN_PHY_LPBK 0x2
1008	1341	u16 timeout;
1009	1342	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1010	1343	};
1011	1344
1012		-#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1013		-#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1014		-#define BNXT_CAG_REG_BASE 0x300000
	1345	+#define CHIMP_REG_VIEW_ADDR \
	1346	+ ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
	1347	+
	1348	+#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
	1349	+#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
	1350	+#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
	1351	+#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
	1352	+#define BNXT_CAG_REG_BASE 0x300000
	1353	+
	1354	+#define BNXT_GRCPF_REG_KONG_COMM 0xA00
	1355	+#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
	1356	+
	1357	+#define BNXT_GRC_BASE_MASK 0xfffff000
	1358	+#define BNXT_GRC_OFFSET_MASK 0x00000ffc
1015	1359
1016	1360	struct bnxt_tc_flow_stats {
1017	1361	u64 packets;
1018	1362	u64 bytes;
1019	1363	};
	1364	+
	1365	+#ifdef CONFIG_BNXT_FLOWER_OFFLOAD
	1366	+struct bnxt_flower_indr_block_cb_priv {
	1367	+ struct net_device *tunnel_netdev;
	1368	+ struct bnxt *bp;
	1369	+ struct list_head list;
	1370	+};
	1371	+#endif
1020	1372
1021	1373	struct bnxt_tc_info {
1022	1374	bool enabled;
..	..	@@ -1074,6 +1426,131 @@
1074	1426	struct bnxt_vf_rep_stats tx_stats;
1075	1427	};
1076	1428
	1429	+#define PTU_PTE_VALID 0x1UL
	1430	+#define PTU_PTE_LAST 0x2UL
	1431	+#define PTU_PTE_NEXT_TO_LAST 0x4UL
	1432	+
	1433	+#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
	1434	+#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
	1435	+
	1436	+struct bnxt_ctx_pg_info {
	1437	+ u32 entries;
	1438	+ u32 nr_pages;
	1439	+ void *ctx_pg_arr[MAX_CTX_PAGES];
	1440	+ dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
	1441	+ struct bnxt_ring_mem_info ring_mem;
	1442	+ struct bnxt_ctx_pg_info **ctx_pg_tbl;
	1443	+};
	1444	+
	1445	+#define BNXT_MAX_TQM_SP_RINGS 1
	1446	+#define BNXT_MAX_TQM_FP_RINGS 8
	1447	+#define BNXT_MAX_TQM_RINGS \
	1448	+ (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
	1449	+
	1450	+#define BNXT_SET_CTX_PAGE_ATTR(attr) \
	1451	+do { \
	1452	+ if (BNXT_PAGE_SIZE == 0x2000) \
	1453	+ attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
	1454	+ else if (BNXT_PAGE_SIZE == 0x10000) \
	1455	+ attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
	1456	+ else \
	1457	+ attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
	1458	+} while (0)
	1459	+
	1460	+struct bnxt_ctx_mem_info {
	1461	+ u32 qp_max_entries;
	1462	+ u16 qp_min_qp1_entries;
	1463	+ u16 qp_max_l2_entries;
	1464	+ u16 qp_entry_size;
	1465	+ u16 srq_max_l2_entries;
	1466	+ u32 srq_max_entries;
	1467	+ u16 srq_entry_size;
	1468	+ u16 cq_max_l2_entries;
	1469	+ u32 cq_max_entries;
	1470	+ u16 cq_entry_size;
	1471	+ u16 vnic_max_vnic_entries;
	1472	+ u16 vnic_max_ring_table_entries;
	1473	+ u16 vnic_entry_size;
	1474	+ u32 stat_max_entries;
	1475	+ u16 stat_entry_size;
	1476	+ u16 tqm_entry_size;
	1477	+ u32 tqm_min_entries_per_ring;
	1478	+ u32 tqm_max_entries_per_ring;
	1479	+ u32 mrav_max_entries;
	1480	+ u16 mrav_entry_size;
	1481	+ u16 tim_entry_size;
	1482	+ u32 tim_max_entries;
	1483	+ u16 mrav_num_entries_units;
	1484	+ u8 tqm_entries_multiple;
	1485	+ u8 ctx_kind_initializer;
	1486	+ u8 tqm_fp_rings_count;
	1487	+
	1488	+ u32 flags;
	1489	+ #define BNXT_CTX_FLAG_INITED 0x01
	1490	+
	1491	+ struct bnxt_ctx_pg_info qp_mem;
	1492	+ struct bnxt_ctx_pg_info srq_mem;
	1493	+ struct bnxt_ctx_pg_info cq_mem;
	1494	+ struct bnxt_ctx_pg_info vnic_mem;
	1495	+ struct bnxt_ctx_pg_info stat_mem;
	1496	+ struct bnxt_ctx_pg_info mrav_mem;
	1497	+ struct bnxt_ctx_pg_info tim_mem;
	1498	+ struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
	1499	+};
	1500	+
	1501	+struct bnxt_fw_health {
	1502	+ u32 flags;
	1503	+ u32 polling_dsecs;
	1504	+ u32 master_func_wait_dsecs;
	1505	+ u32 normal_func_wait_dsecs;
	1506	+ u32 post_reset_wait_dsecs;
	1507	+ u32 post_reset_max_wait_dsecs;
	1508	+ u32 regs[4];
	1509	+ u32 mapped_regs[4];
	1510	+#define BNXT_FW_HEALTH_REG 0
	1511	+#define BNXT_FW_HEARTBEAT_REG 1
	1512	+#define BNXT_FW_RESET_CNT_REG 2
	1513	+#define BNXT_FW_RESET_INPROG_REG 3
	1514	+ u32 fw_reset_inprog_reg_mask;
	1515	+ u32 last_fw_heartbeat;
	1516	+ u32 last_fw_reset_cnt;
	1517	+ u8 enabled:1;
	1518	+ u8 master:1;
	1519	+ u8 fatal:1;
	1520	+ u8 status_reliable:1;
	1521	+ u8 tmr_multiplier;
	1522	+ u8 tmr_counter;
	1523	+ u8 fw_reset_seq_cnt;
	1524	+ u32 fw_reset_seq_regs[16];
	1525	+ u32 fw_reset_seq_vals[16];
	1526	+ u32 fw_reset_seq_delay_msec[16];
	1527	+ struct devlink_health_reporter *fw_reporter;
	1528	+ struct devlink_health_reporter *fw_reset_reporter;
	1529	+ struct devlink_health_reporter *fw_fatal_reporter;
	1530	+};
	1531	+
	1532	+struct bnxt_fw_reporter_ctx {
	1533	+ unsigned long sp_event;
	1534	+};
	1535	+
	1536	+#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
	1537	+#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
	1538	+#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
	1539	+#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
	1540	+#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
	1541	+
	1542	+#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
	1543	+#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
	1544	+
	1545	+#define BNXT_FW_HEALTH_WIN_BASE 0x3000
	1546	+#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
	1547	+
	1548	+#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
	1549	+ ((reg) & BNXT_GRC_OFFSET_MASK))
	1550	+
	1551	+#define BNXT_FW_STATUS_HEALTHY 0x8000
	1552	+#define BNXT_FW_STATUS_SHUTDOWN 0x100000
	1553	+
1077	1554	struct bnxt {
1078	1555	void __iomem *bar0;
1079	1556	void __iomem *bar1;
..	..	@@ -1102,10 +1579,20 @@
1102	1579	#define CHIP_NUM_57414L 0x16db
1103	1580
1104	1581	#define CHIP_NUM_5745X 0xd730
	1582	+#define CHIP_NUM_57452 0xc452
	1583	+#define CHIP_NUM_57454 0xc454
	1584	+
	1585	+#define CHIP_NUM_57508 0x1750
	1586	+#define CHIP_NUM_57504 0x1751
	1587	+#define CHIP_NUM_57502 0x1752
1105	1588
1106	1589	#define CHIP_NUM_58802 0xd802
1107	1590	#define CHIP_NUM_58804 0xd804
1108	1591	#define CHIP_NUM_58808 0xd808
	1592	+
	1593	+ u8 chip_rev;
	1594	+
	1595	+#define CHIP_NUM_58818 0xd818
1109	1596
1110	1597	#define BNXT_CHIP_NUM_5730X(chip_num) \
1111	1598	((chip_num) >= CHIP_NUM_57301 && \
..	..	@@ -1130,7 +1617,10 @@
1130	1617	((chip_num) == CHIP_NUM_58700)
1131	1618
1132	1619	#define BNXT_CHIP_NUM_5745X(chip_num) \
1133		- ((chip_num) == CHIP_NUM_5745X)
	1620	+ ((chip_num) == CHIP_NUM_5745X \|\| \
	1621	+ (chip_num) == CHIP_NUM_57452 \|\| \
	1622	+ (chip_num) == CHIP_NUM_57454)
	1623	+
1134	1624
1135	1625	#define BNXT_CHIP_NUM_57X0X(chip_num) \
1136	1626	(BNXT_CHIP_NUM_5730X(chip_num) \|\| BNXT_CHIP_NUM_5740X(chip_num))
..	..	@@ -1143,12 +1633,17 @@
1143	1633	(chip_num) == CHIP_NUM_58804 \|\| \
1144	1634	(chip_num) == CHIP_NUM_58808)
1145	1635
	1636	+#define BNXT_VPD_FLD_LEN 32
	1637	+ char board_partno[BNXT_VPD_FLD_LEN];
	1638	+ char board_serialno[BNXT_VPD_FLD_LEN];
	1639	+
1146	1640	struct net_device *dev;
1147	1641	struct pci_dev *pdev;
1148	1642
1149	1643	atomic_t intr_sem;
1150	1644
1151	1645	u32 flags;
	1646	+ #define BNXT_FLAG_CHIP_P5 0x1
1152	1647	#define BNXT_FLAG_VF 0x2
1153	1648	#define BNXT_FLAG_LRO 0x4
1154	1649	#ifdef CONFIG_INET
..	..	@@ -1177,7 +1672,9 @@
1177	1672	BNXT_FLAG_ROCEV2_CAP)
1178	1673	#define BNXT_FLAG_NO_AGG_RINGS 0x20000
1179	1674	#define BNXT_FLAG_RX_PAGE_MODE 0x40000
	1675	+ #define BNXT_FLAG_CHIP_SR2 0x80000
1180	1676	#define BNXT_FLAG_MULTI_HOST 0x100000
	1677	+ #define BNXT_FLAG_DSN_VALID 0x200000
1181	1678	#define BNXT_FLAG_DOUBLE_DB 0x400000
1182	1679	#define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1183	1680	#define BNXT_FLAG_DIM 0x2000000
..	..	@@ -1193,16 +1690,37 @@
1193	1690	#define BNXT_NPAR(bp) ((bp)->port_partition_type)
1194	1691	#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1195	1692	#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
	1693	+#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) \|\| \
	1694	+ ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) && \
	1695	+ (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1196	1696	#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1197	1697	#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
	1698	+#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
	1699	+ (!((bp)->flags & BNXT_FLAG_CHIP_P5) \|\| \
	1700	+ (bp)->max_tpa_v2) && !is_kdump_kernel())
1198	1701
1199		-/* Chip class phase 4 and later */
1200		-#define BNXT_CHIP_P4_PLUS(bp) \
	1702	+#define BNXT_CHIP_SR2(bp) \
	1703	+ ((bp)->chip_num == CHIP_NUM_58818)
	1704	+
	1705	+#define BNXT_CHIP_P5_THOR(bp) \
	1706	+ ((bp)->chip_num == CHIP_NUM_57508 \|\| \
	1707	+ (bp)->chip_num == CHIP_NUM_57504 \|\| \
	1708	+ (bp)->chip_num == CHIP_NUM_57502)
	1709	+
	1710	+/* Chip class phase 5 */
	1711	+#define BNXT_CHIP_P5(bp) \
	1712	+ (BNXT_CHIP_P5_THOR(bp) \|\| BNXT_CHIP_SR2(bp))
	1713	+
	1714	+/* Chip class phase 4.x */
	1715	+#define BNXT_CHIP_P4(bp) \
1201	1716	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) \|\| \
1202	1717	BNXT_CHIP_NUM_5745X((bp)->chip_num) \|\| \
1203	1718	BNXT_CHIP_NUM_588XX((bp)->chip_num) \|\| \
1204	1719	(BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1205	1720	!BNXT_CHIP_TYPE_NITRO_A0(bp)))
	1721	+
	1722	+#define BNXT_CHIP_P4_PLUS(bp) \
	1723	+ (BNXT_CHIP_P4(bp) \|\| BNXT_CHIP_P5(bp))
1206	1724
1207	1725	struct bnxt_en_dev *edev;
1208	1726	struct bnxt_en_dev * (ulp_probe)(struct net_device );
..	..	@@ -1221,6 +1739,8 @@
1221	1739	u16, void , u8 , dma_addr_t,
1222	1740	unsigned int);
1223	1741
	1742	+ u16 max_tpa_v2;
	1743	+ u16 max_tpa;
1224	1744	u32 rx_buf_size;
1225	1745	u32 rx_buf_use_size; /* useable size */
1226	1746	u16 rx_offset;
..	..	@@ -1253,12 +1773,12 @@
1253	1773	int cp_nr_pages;
1254	1774	int cp_nr_rings;
1255	1775
1256		- int num_stat_ctxs;
1257		-
1258	1776	/* grp_info indexed by completion ring index */
1259	1777	struct bnxt_ring_grp_info *grp_info;
1260	1778	struct bnxt_vnic_info *vnic_info;
1261	1779	int nr_vnics;
	1780	+ u16 *rss_indir_tbl;
	1781	+ u16 rss_indir_tbl_entries;
1262	1782	u32 rss_hash_cfg;
1263	1783
1264	1784	u16 max_mtu;
..	..	@@ -1266,6 +1786,8 @@
1266	1786	u8 max_lltc; /* lossless TCs */
1267	1787	struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1268	1788	u8 tc_to_qidx[BNXT_MAX_QUEUE];
	1789	+ u8 q_ids[BNXT_MAX_QUEUE];
	1790	+ u8 max_q;
1269	1791
1270	1792	unsigned int current_interval;
1271	1793	#define BNXT_TIMER_INTERVAL HZ
..	..	@@ -1276,6 +1798,16 @@
1276	1798	#define BNXT_STATE_OPEN 0
1277	1799	#define BNXT_STATE_IN_SP_TASK 1
1278	1800	#define BNXT_STATE_READ_STATS 2
	1801	+#define BNXT_STATE_FW_RESET_DET 3
	1802	+#define BNXT_STATE_IN_FW_RESET 4
	1803	+#define BNXT_STATE_ABORT_ERR 5
	1804	+#define BNXT_STATE_FW_FATAL_COND 6
	1805	+#define BNXT_STATE_DRV_REGISTERED 7
	1806	+#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
	1807	+
	1808	+#define BNXT_NO_FW_ACCESS(bp) \
	1809	+ (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) \|\| \
	1810	+ pci_channel_offline((bp)->pdev))
1279	1811
1280	1812	struct bnxt_irq *irq_tbl;
1281	1813	int total_irqs;
..	..	@@ -1292,31 +1824,53 @@
1292	1824	u32 msg_enable;
1293	1825
1294	1826	u32 fw_cap;
1295		- #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1296		- #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1297		- #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1298		- #define BNXT_FW_CAP_NEW_RM 0x00000008
1299		- #define BNXT_FW_CAP_IF_CHANGE 0x00000010
	1827	+ #define BNXT_FW_CAP_SHORT_CMD 0x00000001
	1828	+ #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
	1829	+ #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
	1830	+ #define BNXT_FW_CAP_NEW_RM 0x00000008
	1831	+ #define BNXT_FW_CAP_IF_CHANGE 0x00000010
	1832	+ #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
	1833	+ #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
	1834	+ #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
	1835	+ #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000
	1836	+ #define BNXT_FW_CAP_PKG_VER 0x00004000
	1837	+ #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
	1838	+ #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 0x00010000
	1839	+ #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
	1840	+ #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
	1841	+ #define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000
	1842	+ #define BNXT_FW_CAP_HOT_RESET 0x00200000
	1843	+ #define BNXT_FW_CAP_SHARED_PORT_CFG 0x00400000
	1844	+ #define BNXT_FW_CAP_VLAN_RX_STRIP 0x01000000
	1845	+ #define BNXT_FW_CAP_VLAN_TX_INSERT 0x02000000
	1846	+ #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED 0x04000000
	1847	+ #define BNXT_FW_CAP_PORT_STATS_NO_RESET 0x10000000
	1848	+ #define BNXT_FW_CAP_RING_MONITOR 0x40000000
1300	1849
1301	1850	#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1302	1851	u32 hwrm_spec_code;
1303	1852	u16 hwrm_cmd_seq;
1304		- u32 hwrm_intr_seq_id;
	1853	+ u16 hwrm_cmd_kong_seq;
	1854	+ u16 hwrm_intr_seq_id;
1305	1855	void *hwrm_short_cmd_req_addr;
1306	1856	dma_addr_t hwrm_short_cmd_req_dma_addr;
1307	1857	void *hwrm_cmd_resp_addr;
1308	1858	dma_addr_t hwrm_cmd_resp_dma_addr;
	1859	+ void *hwrm_cmd_kong_resp_addr;
	1860	+ dma_addr_t hwrm_cmd_kong_resp_dma_addr;
1309	1861
1310	1862	struct rtnl_link_stats64 net_stats_prev;
1311		- struct rx_port_stats *hw_rx_port_stats;
1312		- struct tx_port_stats *hw_tx_port_stats;
1313		- struct rx_port_stats_ext *hw_rx_port_stats_ext;
1314		- dma_addr_t hw_rx_port_stats_map;
1315		- dma_addr_t hw_tx_port_stats_map;
1316		- dma_addr_t hw_rx_port_stats_ext_map;
1317		- int hw_port_stats_size;
	1863	+ struct bnxt_stats_mem port_stats;
	1864	+ struct bnxt_stats_mem rx_port_stats_ext;
	1865	+ struct bnxt_stats_mem tx_port_stats_ext;
	1866	+ u16 fw_rx_stats_ext_size;
	1867	+ u16 fw_tx_stats_ext_size;
	1868	+ u16 hw_ring_stats_size;
	1869	+ u8 pri2cos_idx[8];
	1870	+ u8 pri2cos_valid;
1318	1871
1319	1872	u16 hwrm_max_req_len;
	1873	+ u16 hwrm_max_ext_req_len;
1320	1874	int hwrm_cmd_timeout;
1321	1875	struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1322	1876	struct hwrm_ver_get_output ver_resp;
..	..	@@ -1324,20 +1878,22 @@
1324	1878	#define BC_HWRM_STR_LEN 21
1325	1879	#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1326	1880	char fw_ver_str[FW_VER_STR_LEN];
1327		- __be16 vxlan_port;
1328		- u8 vxlan_port_cnt;
1329		- __le16 vxlan_fw_dst_port_id;
1330		- __be16 nge_port;
1331		- u8 nge_port_cnt;
1332		- __le16 nge_fw_dst_port_id;
	1881	+ char hwrm_ver_supp[FW_VER_STR_LEN];
	1882	+ char nvm_cfg_ver[FW_VER_STR_LEN];
	1883	+ u64 fw_ver_code;
	1884	+#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
	1885	+ ((u64)(maj) << 48 \| (u64)(min) << 32 \| (u64)(bld) << 16 \| (rsv))
	1886	+#define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
	1887	+
	1888	+ u16 vxlan_fw_dst_port_id;
	1889	+ u16 nge_fw_dst_port_id;
1333	1890	u8 port_partition_type;
1334	1891	u8 port_count;
1335	1892	u16 br_mode;
1336	1893
	1894	+ struct bnxt_coal_cap coal_cap;
1337	1895	struct bnxt_coal rx_coal;
1338	1896	struct bnxt_coal tx_coal;
1339		-
1340		-#define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
1341	1897
1342	1898	u32 stats_coal_ticks;
1343	1899	#define BNXT_DEF_STATS_COAL_TICKS 1000000
..	..	@@ -1350,22 +1906,40 @@
1350	1906	#define BNXT_RX_NTP_FLTR_SP_EVENT 1
1351	1907	#define BNXT_LINK_CHNG_SP_EVENT 2
1352	1908	#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1353		-#define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1354		-#define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1355	1909	#define BNXT_RESET_TASK_SP_EVENT 6
1356	1910	#define BNXT_RST_RING_SP_EVENT 7
1357	1911	#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1358	1912	#define BNXT_PERIODIC_STATS_SP_EVENT 9
1359	1913	#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1360	1914	#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1361		-#define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1362		-#define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1363	1915	#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1364	1916	#define BNXT_FLOW_STATS_SP_EVENT 15
1365	1917	#define BNXT_UPDATE_PHY_SP_EVENT 16
	1918	+#define BNXT_RING_COAL_NOW_SP_EVENT 17
	1919	+#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
	1920	+#define BNXT_FW_EXCEPTION_SP_EVENT 19
	1921	+#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
	1922	+
	1923	+ struct delayed_work fw_reset_task;
	1924	+ int fw_reset_state;
	1925	+#define BNXT_FW_RESET_STATE_POLL_VF 1
	1926	+#define BNXT_FW_RESET_STATE_RESET_FW 2
	1927	+#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
	1928	+#define BNXT_FW_RESET_STATE_POLL_FW 4
	1929	+#define BNXT_FW_RESET_STATE_OPENING 5
	1930	+#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
	1931	+
	1932	+ u16 fw_reset_min_dsecs;
	1933	+#define BNXT_DFLT_FW_RST_MIN_DSECS 20
	1934	+ u16 fw_reset_max_dsecs;
	1935	+#define BNXT_DFLT_FW_RST_MAX_DSECS 60
	1936	+ unsigned long fw_reset_timestamp;
	1937	+
	1938	+ struct bnxt_fw_health *fw_health;
1366	1939
1367	1940	struct bnxt_hw_resc hw_resc;
1368	1941	struct bnxt_pf_info pf;
	1942	+ struct bnxt_ctx_mem_info *ctx;
1369	1943	#ifdef CONFIG_BNXT_SRIOV
1370	1944	int nr_vfs;
1371	1945	struct bnxt_vf_info vf;
..	..	@@ -1379,6 +1953,12 @@
1379	1953	*/
1380	1954	struct mutex sriov_lock;
1381	1955	#endif
	1956	+
	1957	+#if BITS_PER_LONG == 32
	1958	+ /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
	1959	+ spinlock_t db_lock;
	1960	+#endif
	1961	+ int db_size;
1382	1962
1383	1963	#define BNXT_NTP_FLTR_MAX_FLTR 4096
1384	1964	#define BNXT_NTP_FLTR_HASH_SIZE 512
..	..	@@ -1406,30 +1986,71 @@
1406	1986
1407	1987	u8 num_leds;
1408	1988	struct bnxt_led_info leds[BNXT_MAX_LED];
	1989	+ u16 dump_flag;
	1990	+#define BNXT_DUMP_LIVE 0
	1991	+#define BNXT_DUMP_CRASH 1
1409	1992
1410	1993	struct bpf_prog *xdp_prog;
1411	1994
1412	1995	/* devlink interface and vf-rep structs */
1413	1996	struct devlink *dl;
	1997	+ struct devlink_port dl_port;
1414	1998	enum devlink_eswitch_mode eswitch_mode;
1415	1999	struct bnxt_vf_rep *vf_reps; / array of vf-rep ptrs */
1416	2000	u16 cfa_code_map; / cfa_code -> vf_idx map */
1417		- u8 switch_id[8];
	2001	+ u8 dsn[8];
1418	2002	struct bnxt_tc_info *tc_info;
	2003	+ struct list_head tc_indr_block_list;
1419	2004	struct dentry *debugfs_pdev;
1420		- struct dentry *debugfs_dim;
1421	2005	struct device *hwmon_dev;
1422	2006	};
	2007	+
	2008	+#define BNXT_NUM_RX_RING_STATS 8
	2009	+#define BNXT_NUM_TX_RING_STATS 8
	2010	+#define BNXT_NUM_TPA_RING_STATS 4
	2011	+#define BNXT_NUM_TPA_RING_STATS_P5 5
	2012	+#define BNXT_NUM_TPA_RING_STATS_P5_SR2 6
	2013	+
	2014	+#define BNXT_RING_STATS_SIZE_P5 \
	2015	+ ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
	2016	+ BNXT_NUM_TPA_RING_STATS_P5) * 8)
	2017	+
	2018	+#define BNXT_RING_STATS_SIZE_P5_SR2 \
	2019	+ ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
	2020	+ BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
	2021	+
	2022	+#define BNXT_GET_RING_STATS64(sw, counter) \
	2023	+ (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
	2024	+
	2025	+#define BNXT_GET_RX_PORT_STATS64(sw, counter) \
	2026	+ (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
	2027	+
	2028	+#define BNXT_GET_TX_PORT_STATS64(sw, counter) \
	2029	+ (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
	2030	+
	2031	+#define BNXT_PORT_STATS_SIZE \
	2032	+ (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
	2033	+
	2034	+#define BNXT_TX_PORT_STATS_BYTE_OFFSET \
	2035	+ (sizeof(struct rx_port_stats) + 512)
1423	2036
1424	2037	#define BNXT_RX_STATS_OFFSET(counter) \
1425	2038	(offsetof(struct rx_port_stats, counter) / 8)
1426	2039
1427	2040	#define BNXT_TX_STATS_OFFSET(counter) \
1428	2041	((offsetof(struct tx_port_stats, counter) + \
1429		- sizeof(struct rx_port_stats) + 512) / 8)
	2042	+ BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
1430	2043
1431	2044	#define BNXT_RX_STATS_EXT_OFFSET(counter) \
1432	2045	(offsetof(struct rx_port_stats_ext, counter) / 8)
	2046	+
	2047	+#define BNXT_TX_STATS_EXT_OFFSET(counter) \
	2048	+ (offsetof(struct tx_port_stats_ext, counter) / 8)
	2049	+
	2050	+#define BNXT_HW_FEATURE_VLAN_ALL_RX \
	2051	+ (NETIF_F_HW_VLAN_CTAG_RX \| NETIF_F_HW_VLAN_STAG_RX)
	2052	+#define BNXT_HW_FEATURE_VLAN_ALL_TX \
	2053	+ (NETIF_F_HW_VLAN_CTAG_TX \| NETIF_F_HW_VLAN_STAG_TX)
1433	2054
1434	2055	#define I2C_DEV_ADDR_A0 0xa0
1435	2056	#define I2C_DEV_ADDR_A2 0xa2
..	..	@@ -1449,21 +2070,103 @@
1449	2070	((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1450	2071	}
1451	2072
	2073	+#if BITS_PER_LONG == 32
	2074	+#define writeq(val64, db) \
	2075	+do { \
	2076	+ spin_lock(&bp->db_lock); \
	2077	+ writel((val64) & 0xffffffff, db); \
	2078	+ writel((val64) >> 32, (db) + 4); \
	2079	+ spin_unlock(&bp->db_lock); \
	2080	+} while (0)
	2081	+
	2082	+#define writeq_relaxed writeq
	2083	+#endif
	2084	+
1452	2085	/* For TX and RX ring doorbells with no ordering guarantee*/
1453		-static inline void bnxt_db_write_relaxed(struct bnxt bp, void __iomem db,
1454		- u32 val)
	2086	+static inline void bnxt_db_write_relaxed(struct bnxt *bp,
	2087	+ struct bnxt_db_info *db, u32 idx)
1455	2088	{
1456		- writel_relaxed(val, db);
1457		- if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1458		- writel_relaxed(val, db);
	2089	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	2090	+ writeq_relaxed(db->db_key64 \| idx, db->doorbell);
	2091	+ } else {
	2092	+ u32 db_val = db->db_key32 \| idx;
	2093	+
	2094	+ writel_relaxed(db_val, db->doorbell);
	2095	+ if (bp->flags & BNXT_FLAG_DOUBLE_DB)
	2096	+ writel_relaxed(db_val, db->doorbell);
	2097	+ }
1459	2098	}
1460	2099
1461	2100	/* For TX and RX ring doorbells */
1462		-static inline void bnxt_db_write(struct bnxt bp, void __iomem db, u32 val)
	2101	+static inline void bnxt_db_write(struct bnxt bp, struct bnxt_db_info db,
	2102	+ u32 idx)
1463	2103	{
1464		- writel(val, db);
1465		- if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1466		- writel(val, db);
	2104	+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
	2105	+ writeq(db->db_key64 \| idx, db->doorbell);
	2106	+ } else {
	2107	+ u32 db_val = db->db_key32 \| idx;
	2108	+
	2109	+ writel(db_val, db->doorbell);
	2110	+ if (bp->flags & BNXT_FLAG_DOUBLE_DB)
	2111	+ writel(db_val, db->doorbell);
	2112	+ }
	2113	+}
	2114	+
	2115	+static inline bool bnxt_cfa_hwrm_message(u16 req_type)
	2116	+{
	2117	+ switch (req_type) {
	2118	+ case HWRM_CFA_ENCAP_RECORD_ALLOC:
	2119	+ case HWRM_CFA_ENCAP_RECORD_FREE:
	2120	+ case HWRM_CFA_DECAP_FILTER_ALLOC:
	2121	+ case HWRM_CFA_DECAP_FILTER_FREE:
	2122	+ case HWRM_CFA_EM_FLOW_ALLOC:
	2123	+ case HWRM_CFA_EM_FLOW_FREE:
	2124	+ case HWRM_CFA_EM_FLOW_CFG:
	2125	+ case HWRM_CFA_FLOW_ALLOC:
	2126	+ case HWRM_CFA_FLOW_FREE:
	2127	+ case HWRM_CFA_FLOW_INFO:
	2128	+ case HWRM_CFA_FLOW_FLUSH:
	2129	+ case HWRM_CFA_FLOW_STATS:
	2130	+ case HWRM_CFA_METER_PROFILE_ALLOC:
	2131	+ case HWRM_CFA_METER_PROFILE_FREE:
	2132	+ case HWRM_CFA_METER_PROFILE_CFG:
	2133	+ case HWRM_CFA_METER_INSTANCE_ALLOC:
	2134	+ case HWRM_CFA_METER_INSTANCE_FREE:
	2135	+ return true;
	2136	+ default:
	2137	+ return false;
	2138	+ }
	2139	+}
	2140	+
	2141	+static inline bool bnxt_kong_hwrm_message(struct bnxt bp, struct input req)
	2142	+{
	2143	+ return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
	2144	+ bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
	2145	+}
	2146	+
	2147	+static inline bool bnxt_hwrm_kong_chnl(struct bnxt bp, struct input req)
	2148	+{
	2149	+ return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
	2150	+ req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
	2151	+}
	2152	+
	2153	+static inline void bnxt_get_hwrm_resp_addr(struct bnxt bp, void *req)
	2154	+{
	2155	+ if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
	2156	+ return bp->hwrm_cmd_kong_resp_addr;
	2157	+ else
	2158	+ return bp->hwrm_cmd_resp_addr;
	2159	+}
	2160	+
	2161	+static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
	2162	+{
	2163	+ u16 seq_id;
	2164	+
	2165	+ if (dst == BNXT_HWRM_CHNL_CHIMP)
	2166	+ seq_id = bp->hwrm_cmd_seq++;
	2167	+ else
	2168	+ seq_id = bp->hwrm_cmd_kong_seq++;
	2169	+ return seq_id;
1467	2170	}
1468	2171
1469	2172	extern const u16 bnxt_lhint_arr[];
..	..	@@ -1471,6 +2174,7 @@
1471	2174	int bnxt_alloc_rx_data(struct bnxt bp, struct bnxt_rx_ring_info rxr,
1472	2175	u16 prod, gfp_t gfp);
1473	2176	void bnxt_reuse_rx_data(struct bnxt_rx_ring_info rxr, u16 cons, void data);
	2177	+u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
1474	2178	void bnxt_set_tpa_flags(struct bnxt *bp);
1475	2179	void bnxt_set_ring_params(struct bnxt *);
1476	2180	int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
..	..	@@ -1479,19 +2183,22 @@
1479	2183	int _hwrm_send_message_silent(struct bnxt bp, void msg, u32 len, int timeout);
1480	2184	int hwrm_send_message(struct bnxt , void , u32, int);
1481	2185	int hwrm_send_message_silent(struct bnxt , void , u32, int);
1482		-int bnxt_hwrm_func_rgtr_async_events(struct bnxt bp, unsigned long bmap,
1483		- int bmap_size);
	2186	+int bnxt_hwrm_func_drv_rgtr(struct bnxt bp, unsigned long bmap,
	2187	+ int bmap_size, bool async_only);
	2188	+int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
1484	2189	int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1485	2190	int __bnxt_hwrm_get_tx_rings(struct bnxt bp, u16 fid, int tx_rings);
	2191	+int bnxt_nq_rings_in_use(struct bnxt *bp);
1486	2192	int bnxt_hwrm_set_coal(struct bnxt *);
1487	2193	unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1488		-void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
	2194	+unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
1489	2195	unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1490		-unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp);
	2196	+unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
1491	2197	int bnxt_get_avail_msix(struct bnxt *bp, int num);
1492		-int bnxt_reserve_rings(struct bnxt *bp);
	2198	+int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
1493	2199	void bnxt_tx_disable(struct bnxt *bp);
1494	2200	void bnxt_tx_enable(struct bnxt *bp);
	2201	+int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
1495	2202	int bnxt_hwrm_set_pause(struct bnxt *);
1496	2203	int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1497	2204	int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
..	..	@@ -1502,12 +2209,17 @@
1502	2209	int bnxt_half_open_nic(struct bnxt *bp);
1503	2210	void bnxt_half_close_nic(struct bnxt *bp);
1504	2211	int bnxt_close_nic(struct bnxt *, bool, bool);
	2212	+int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
	2213	+ u32 *reg_buf);
	2214	+void bnxt_fw_exception(struct bnxt *bp);
	2215	+void bnxt_fw_reset(struct bnxt *bp);
1505	2216	int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1506	2217	int tx_xdp);
1507	2218	int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1508	2219	int bnxt_get_max_rings(struct bnxt , int , int *, bool);
1509	2220	int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1510		-int bnxt_port_attr_get(struct bnxt bp, struct switchdev_attr attr);
	2221	+int bnxt_get_port_parent_id(struct net_device *dev,
	2222	+ struct netdev_phys_item_id *ppid);
1511	2223	void bnxt_dim_work(struct work_struct *work);
1512	2224	int bnxt_hwrm_set_ring_coal(struct bnxt bp, struct bnxt_napi bnapi);
1513	2225