forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
....@@ -74,16 +74,22 @@
7474 	__stringify(BCM_5710_FW_MINOR_VERSION) "."	\
7575 	__stringify(BCM_5710_FW_REVISION_VERSION) "."	\
7676 	__stringify(BCM_5710_FW_ENGINEERING_VERSION)
77
+
78
+#define FW_FILE_VERSION_V15				\
79
+	__stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
80
+	__stringify(BCM_5710_FW_MINOR_VERSION) "."	\
81
+	__stringify(BCM_5710_FW_REVISION_VERSION_V15) "."	\
82
+	__stringify(BCM_5710_FW_ENGINEERING_VERSION)
83
+
7784 #define FW_FILE_NAME_E1		"bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
7885 #define FW_FILE_NAME_E1H	"bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
7986 #define FW_FILE_NAME_E2		"bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
87
+#define FW_FILE_NAME_E1_V15	"bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw"
88
+#define FW_FILE_NAME_E1H_V15	"bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw"
89
+#define FW_FILE_NAME_E2_V15	"bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw"
8090 
8191 /* Time in jiffies before concluding the transmitter is hung */
8292 #define TX_TIMEOUT		(5*HZ)
83
-
84
-static char version[] =
85
-	"QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
86
-	DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
8793 
8894 MODULE_AUTHOR("Eliezer Tamir");
8995 MODULE_DESCRIPTION("QLogic "
....@@ -91,10 +97,12 @@
9197 		   "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
9298 		   "57840/57840_MF Driver");
9399 MODULE_LICENSE("GPL");
94
-MODULE_VERSION(DRV_MODULE_VERSION);
95100 MODULE_FIRMWARE(FW_FILE_NAME_E1);
96101 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
97102 MODULE_FIRMWARE(FW_FILE_NAME_E2);
103
+MODULE_FIRMWARE(FW_FILE_NAME_E1_V15);
104
+MODULE_FIRMWARE(FW_FILE_NAME_E1H_V15);
105
+MODULE_FIRMWARE(FW_FILE_NAME_E2_V15);
98106 
99107 int bnx2x_num_queues;
100108 module_param_named(num_queues, bnx2x_num_queues, int, 0444);
....@@ -280,6 +288,13 @@
280288 };
281289 
282290 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
291
+
292
+const u32 dmae_reg_go_c[] = {
293
+	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
294
+	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
295
+	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
296
+	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
297
+};
283298 
284299 /* Global resources for unloading a previously loaded device */
285300 #define BNX2X_PREV_WAIT_NEEDED 1
....@@ -745,9 +760,7 @@
745760 		  CHIP_IS_E1(bp) ? "everest1" :
746761 		  CHIP_IS_E1H(bp) ? "everest1h" :
747762 		  CHIP_IS_E2(bp) ? "everest2" : "everest3",
748
-		  BCM_5710_FW_MAJOR_VERSION,
749
-		  BCM_5710_FW_MINOR_VERSION,
750
-		  BCM_5710_FW_REVISION_VERSION);
763
+		  bp->fw_major, bp->fw_minor, bp->fw_rev);
751764 
752765 	return rc;
753766 }
....@@ -869,9 +882,6 @@
869882 	   "write %x to HC %d (addr 0x%x)\n",
870883 	   val, port, addr);
871884 
872
-	/* flush all outstanding writes */
873
-	mmiowb();
874
-
875885 	REG_WR(bp, addr, val);
876886 	if (REG_RD(bp, addr) != val)
877887 		BNX2X_ERR("BUG! Proper val not read from IGU!\n");
....@@ -886,9 +896,6 @@
886896 		 IGU_PF_CONF_ATTN_BIT_EN);
887897 
888898 	DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
889
-
890
-	/* flush all outstanding writes */
891
-	mmiowb();
892899 
893900 	REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
894901 	if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
....@@ -1180,9 +1187,18 @@
11801187 	}
11811188 #endif
11821189 	if (IS_PF(bp)) {
1190
+		int tmp_msg_en = bp->msg_enable;
1191
+
11831192 		bnx2x_fw_dump(bp);
1193
+		bp->msg_enable |= NETIF_MSG_HW;
1194
+		BNX2X_ERR("Idle check (1st round) ----------\n");
1195
+		bnx2x_idle_chk(bp);
1196
+		BNX2X_ERR("Idle check (2nd round) ----------\n");
1197
+		bnx2x_idle_chk(bp);
1198
+		bp->msg_enable = tmp_msg_en;
11841199 		bnx2x_mc_assert(bp);
11851200 	}
1201
+
11861202 	BNX2X_ERR("end crash dump -----------------\n");
11871203 }
11881204 
....@@ -1595,7 +1611,6 @@
15951611 	/*
15961612 	 * Ensure that HC_CONFIG is written before leading/trailing edge config
15971613 	 */
1598
-	mmiowb();
15991614 	barrier();
16001615 
16011616 	if (!CHIP_IS_E1(bp)) {
....@@ -1611,9 +1626,6 @@
16111626 		REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
16121627 		REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
16131628 	}
1614
-
1615
-	/* Make sure that interrupts are indeed enabled from here on */
1616
-	mmiowb();
16171629 }
16181630 
16191631 static void bnx2x_igu_int_enable(struct bnx2x *bp)
....@@ -1674,9 +1686,6 @@
16741686 
16751687 	REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
16761688 	REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1677
-
1678
-	/* Make sure that interrupts are indeed enabled from here on */
1679
-	mmiowb();
16801689 }
16811690 
16821691 void bnx2x_int_enable(struct bnx2x *bp)
....@@ -3088,9 +3097,9 @@
30883097 /**
30893098  * bnx2x_get_common_flags - Return common flags
30903099  *
3091
- * @bp		device handle
3092
- * @fp		queue handle
3093
- * @zero_stats	TRUE if statistics zeroing is needed
3100
+ * @bp:		device handle
3101
+ * @fp:		queue handle
3102
+ * @zero_stats:	TRUE if statistics zeroing is needed
30943103  *
30953104  * Return the flags that are common for the Tx-only and not normal connections.
30963105  */
....@@ -3833,7 +3842,6 @@
38333842 
38343843 	REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
38353844 			 bp->spq_prod_idx);
3836
-	mmiowb();
38373845 }
38383846 
38393847 /**
....@@ -5244,7 +5252,6 @@
52445252 {
52455253 	/* No memory barriers */
52465254 	storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5247
-	mmiowb(); /* keep prod updates ordered */
52485255 }
52495256 
52505257 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
....@@ -6317,11 +6324,11 @@
63176324 	case FW_MSG_CODE_DRV_LOAD_COMMON:
63186325 	case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
63196326 		bnx2x_init_internal_common(bp);
6320
-		/* no break */
6327
+		fallthrough;
63216328 
63226329 	case FW_MSG_CODE_DRV_LOAD_PORT:
63236330 		/* nothing to do */
6324
-		/* no break */
6331
+		fallthrough;
63256332 
63266333 	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
63276334 		/* internal memory per function is
....@@ -6513,7 +6520,6 @@
65136520 
65146521 	/* flush all */
65156522 	mb();
6516
-	mmiowb();
65176523 }
65186524 
65196525 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
....@@ -6553,7 +6559,6 @@
65536559 
65546560 	/* flush all before enabling interrupts */
65556561 	mb();
6556
-	mmiowb();
65576562 
65586563 	bnx2x_int_enable(bp);
65596564 
....@@ -7728,6 +7733,9 @@
77287733 		REG_WR(bp, reg_addr, val);
77297734 	}
77307735 
7736
+	if (CHIP_IS_E3B0(bp))
7737
+		bp->flags |= PTP_SUPPORTED;
7738
+
77317739 	return 0;
77327740 }
77337741 
....@@ -7772,12 +7780,10 @@
77727780 	DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
77737781 			 data, igu_addr_data);
77747782 	REG_WR(bp, igu_addr_data, data);
7775
-	mmiowb();
77767783 	barrier();
77777784 	DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
77787785 			  ctl, igu_addr_ctl);
77797786 	REG_WR(bp, igu_addr_ctl, ctl);
7780
-	mmiowb();
77817787 	barrier();
77827788 
77837789 	/* wait for clean up to finish */
....@@ -8605,11 +8611,11 @@
86058611 			       bp->num_queues,
86068612 			       1 + bp->num_cnic_queues);
86078613 
8608
-		/* fall through */
8614
+		fallthrough;
86098615 	case BNX2X_INT_MODE_MSI:
86108616 		bnx2x_enable_msi(bp);
86118617 
8612
-		/* fall through */
8618
+		fallthrough;
86138619 	case BNX2X_INT_MODE_INTX:
86148620 		bp->num_ethernet_queues = 1;
86158621 		bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
....@@ -9462,8 +9468,13 @@
94629468 	 * function stop ramrod is sent, since as part of this ramrod FW access
94639469 	 * PTP registers.
94649470 	 */
9465
-	if (bp->flags & PTP_SUPPORTED)
9471
+	if (bp->flags & PTP_SUPPORTED) {
94669472 		bnx2x_stop_ptp(bp);
9473
+		if (bp->ptp_clock) {
9474
+			ptp_clock_unregister(bp->ptp_clock);
9475
+			bp->ptp_clock = NULL;
9476
+		}
9477
+	}
94679478 
94689479 	/* Disable HW interrupts, NAPI */
94699480 	bnx2x_netif_stop(bp, 1);
....@@ -9549,7 +9560,6 @@
95499560 
95509561 	DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
95519562 		close ? "closing" : "opening");
9552
-	mmiowb();
95539563 }
95549564 
95559565 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
....@@ -9673,7 +9683,6 @@
96739683 	if (!CHIP_IS_E1(bp)) {
96749684 		REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
96759685 		REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9676
-		mmiowb();
96779686 	}
96789687 }
96799688 
....@@ -9773,16 +9782,13 @@
97739782 	       reset_mask1 & (~not_reset_mask1));
97749783 
97759784 	barrier();
9776
-	mmiowb();
97779785 
97789786 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
97799787 	       reset_mask2 & (~stay_reset2));
97809788 
97819789 	barrier();
9782
-	mmiowb();
97839790 
97849791 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9785
-	mmiowb();
97869792 }
97879793 
97889794 /**
....@@ -9865,9 +9871,6 @@
98659871 	/* Clear "unprepared" bit */
98669872 	REG_WR(bp, MISC_REG_UNPREPARED, 0);
98679873 	barrier();
9868
-
9869
-	/* Make sure all is written to the chip before the reset */
9870
-	mmiowb();
98719874 
98729875 	/* Wait for 1ms to empty GLUE and PCI-E core queues,
98739876 	 * PSWHST, GRC and PSWRD Tetris buffer.
....@@ -10160,7 +10163,6 @@
1016010163 {
1016110164 	struct bnx2x_func_switch_update_params *switch_update_params;
1016210165 	struct bnx2x_func_state_params func_params = {NULL};
10163
-	struct bnx2x_udp_tunnel *udp_tunnel;
1016410166 	u16 vxlan_port = 0, geneve_port = 0;
1016510167 	int rc;
1016610168 
....@@ -10177,15 +10179,13 @@
1017710179 	__set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1017810180 		  &switch_update_params->changes);
1017910181 
10180
-	if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10181
-		udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10182
-		geneve_port = udp_tunnel->dst_port;
10182
+	if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) {
10183
+		geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
1018310184 		switch_update_params->geneve_dst_port = geneve_port;
1018410185 	}
1018510186 
10186
-	if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10187
-		udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10188
-		vxlan_port = udp_tunnel->dst_port;
10187
+	if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) {
10188
+		vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
1018910189 		switch_update_params->vxlan_dst_port = vxlan_port;
1019010190 	}
1019110191 
....@@ -10205,93 +10205,26 @@
1020510205 	return rc;
1020610206 }
1020710207 
10208
-static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10209
-				 enum bnx2x_udp_port_type type)
10210
-{
10211
-	struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10212
-
10213
-	if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
10214
-		return;
10215
-
10216
-	if (udp_port->count && udp_port->dst_port == port) {
10217
-		udp_port->count++;
10218
-		return;
10219
-	}
10220
-
10221
-	if (udp_port->count) {
10222
-		DP(BNX2X_MSG_SP,
10223
-		   "UDP tunnel [%d] -  destination port limit reached\n",
10224
-		   type);
10225
-		return;
10226
-	}
10227
-
10228
-	udp_port->dst_port = port;
10229
-	udp_port->count = 1;
10230
-	bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10231
-}
10232
-
10233
-static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10234
-				 enum bnx2x_udp_port_type type)
10235
-{
10236
-	struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10237
-
10238
-	if (!IS_PF(bp) || CHIP_IS_E1x(bp))
10239
-		return;
10240
-
10241
-	if (!udp_port->count || udp_port->dst_port != port) {
10242
-		DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10243
-		   type);
10244
-		return;
10245
-	}
10246
-
10247
-	/* Remove reference, and make certain it's no longer in use */
10248
-	udp_port->count--;
10249
-	if (udp_port->count)
10250
-		return;
10251
-	udp_port->dst_port = 0;
10252
-
10253
-	if (netif_running(bp->dev))
10254
-		bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10255
-	else
10256
-		DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10257
-		   type, port);
10258
-}
10259
-
10260
-static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10261
-				 struct udp_tunnel_info *ti)
10208
+static int bnx2x_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
1026210209 {
1026310210 	struct bnx2x *bp = netdev_priv(netdev);
10264
-	u16 t_port = ntohs(ti->port);
10211
+	struct udp_tunnel_info ti;
1026510212 
10266
-	switch (ti->type) {
10267
-	case UDP_TUNNEL_TYPE_VXLAN:
10268
-		__bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10269
-		break;
10270
-	case UDP_TUNNEL_TYPE_GENEVE:
10271
-		__bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10272
-		break;
10273
-	default:
10274
-		break;
10275
-	}
10213
+	udp_tunnel_nic_get_port(netdev, table, 0, &ti);
10214
+	bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port);
10215
+
10216
+	return bnx2x_udp_port_update(bp);
1027610217 }
1027710218 
10278
-static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10279
-				 struct udp_tunnel_info *ti)
10280
-{
10281
-	struct bnx2x *bp = netdev_priv(netdev);
10282
-	u16 t_port = ntohs(ti->port);
10283
-
10284
-	switch (ti->type) {
10285
-	case UDP_TUNNEL_TYPE_VXLAN:
10286
-		__bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10287
-		break;
10288
-	case UDP_TUNNEL_TYPE_GENEVE:
10289
-		__bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10290
-		break;
10291
-	default:
10292
-		break;
10293
-	}
10294
-}
10219
+static const struct udp_tunnel_nic_info bnx2x_udp_tunnels = {
10220
+	.sync_table	= bnx2x_udp_tunnel_sync,
10221
+	.flags		= UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
10222
+			  UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
10223
+	.tables		= {
10224
+		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },
10225
+		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
10226
+	},
10227
+};
1029510228 
1029610229 static int bnx2x_close(struct net_device *dev);
1029710230 
....@@ -10414,24 +10347,6 @@
1041410347 
1041510348 	if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state))
1041610349 		bnx2x_handle_update_svid_cmd(bp);
10417
-
10418
-	if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
10419
-			       &bp->sp_rtnl_state)) {
10420
-		if (bnx2x_udp_port_update(bp)) {
10421
-			/* On error, forget configuration */
10422
-			memset(bp->udp_tunnel_ports, 0,
10423
-			       sizeof(struct bnx2x_udp_tunnel) *
10424
-			       BNX2X_UDP_PORT_MAX);
10425
-		} else {
10426
-			/* Since we don't store additional port information,
10427
-			 * if no ports are configured for any feature ask for
10428
-			 * information about currently configured ports.
10429
-			 */
10430
-			if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10431
-			    !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10432
-				udp_tunnel_get_rx_info(bp->dev);
10433
-		}
10434
-	}
1043510350 
1043610351 	/* work which needs rtnl lock not-taken (as it takes the lock itself and
1043710352 	 * can be called from other contexts as well)
....@@ -11305,7 +11220,7 @@
1130511220 			   dev_info.port_hw_config[port].external_phy_config),
1130611221 			   SHMEM_RD(bp,
1130711222 			   dev_info.port_hw_config[port].external_phy_config2));
11308
-			return;
11223
+		return;
1130911224 	}
1131011225 
1131111226 	if (CHIP_IS_E3(bp))
....@@ -12005,7 +11920,7 @@
1200511920 static int bnx2x_get_hwinfo(struct bnx2x *bp)
1200611921 {
1200711922 	int /*abs*/func = BP_ABS_FUNC(bp);
12008
-	int vn, mfw_vn;
11923
+	int vn;
1200911924 	u32 val = 0, val2 = 0;
1201011925 	int rc = 0;
1201111926 
....@@ -12090,12 +12005,10 @@
1209012005 	/*
1209112006 	 * Initialize MF configuration
1209212007 	 */
12093
-
1209412008 	bp->mf_ov = 0;
1209512009 	bp->mf_mode = 0;
1209612010 	bp->mf_sub_mode = 0;
1209712011 	vn = BP_VN(bp);
12098
-	mfw_vn = BP_FW_MB_IDX(bp);
1209912012 
1210012013 	if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
1210112014 		BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
....@@ -12488,7 +12401,7 @@
1248812401 	}
1248912402 
1249012403 	if (CHIP_IS_E1(bp))
12491
-		bp->dropless_fc = 0;
12404
+		bp->dropless_fc = false;
1249212405 	else
1249312406 		bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
1249412407 
....@@ -12551,9 +12464,6 @@
1255112464 	BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
1255212465 
1255312466 	bp->dump_preset_idx = 1;
12554
-
12555
-	if (CHIP_IS_E3B0(bp))
12556
-		bp->flags |= PTP_SUPPORTED;
1255712467 
1255812468 	return rc;
1255912469 }
....@@ -12632,9 +12542,6 @@
1263212542 	rc = bnx2x_nic_load(bp, LOAD_OPEN);
1263312543 	if (rc)
1263412544 		return rc;
12635
-
12636
-	if (IS_PF(bp))
12637
-		udp_tunnel_get_rx_info(dev);
1263812545 
1263912546 	return 0;
1264012547 }
....@@ -13166,6 +13073,7 @@
1316613073 	.ndo_set_vf_mac		= bnx2x_set_vf_mac,
1316713074 	.ndo_set_vf_vlan	= bnx2x_set_vf_vlan,
1316813075 	.ndo_get_vf_config	= bnx2x_get_vf_config,
13076
+	.ndo_set_vf_spoofchk	= bnx2x_set_vf_spoofchk,
1316913077 #endif
1317013078 #ifdef NETDEV_FCOE_WWNN
1317113079 	.ndo_fcoe_get_wwn	= bnx2x_fcoe_get_wwn,
....@@ -13174,8 +13082,8 @@
1317413082 	.ndo_get_phys_port_id	= bnx2x_get_phys_port_id,
1317513083 	.ndo_set_vf_link_state	= bnx2x_set_vf_link_state,
1317613084 	.ndo_features_check	= bnx2x_features_check,
13177
-	.ndo_udp_tunnel_add	= bnx2x_udp_tunnel_add,
13178
-	.ndo_udp_tunnel_del	= bnx2x_udp_tunnel_del,
13085
+	.ndo_udp_tunnel_add	= udp_tunnel_nic_add_port,
13086
+	.ndo_udp_tunnel_del	= udp_tunnel_nic_del_port,
1317913087 };
1318013088 
1318113089 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
....@@ -13370,6 +13278,9 @@
1337013278 
1337113279 		dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
1337213280 					    NETIF_F_GSO_UDP_TUNNEL_CSUM;
13281
+
13282
+		if (IS_PF(bp))
13283
+			dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels;
1337313284 	}
1337413285 
1337513286 	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
....@@ -13466,16 +13377,11 @@
1346613377 	/* Check FW version */
1346713378 	offset = be32_to_cpu(fw_hdr->fw_version.offset);
1346813379 	fw_ver = firmware->data + offset;
13469
-	if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13470
-	    (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13471
-	    (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13472
-	    (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
13380
+	if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor ||
13381
+	    fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) {
1347313382 		BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13474
-		       fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13475
-		       BCM_5710_FW_MAJOR_VERSION,
13476
-		       BCM_5710_FW_MINOR_VERSION,
13477
-		       BCM_5710_FW_REVISION_VERSION,
13478
-		       BCM_5710_FW_ENGINEERING_VERSION);
13383
+			  fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13384
+			  bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng);
1347913385 		return -EINVAL;
1348013386 	}
1348113387 
....@@ -13555,31 +13461,48 @@
1355513461 
1355613462 static int bnx2x_init_firmware(struct bnx2x *bp)
1355713463 {
13558
-	const char *fw_file_name;
13464
+	const char *fw_file_name, *fw_file_name_v15;
1355913465 	struct bnx2x_fw_file_hdr *fw_hdr;
1356013466 	int rc;
1356113467 
1356213468 	if (bp->firmware)
1356313469 		return 0;
1356413470 
13565
-	if (CHIP_IS_E1(bp))
13471
+	if (CHIP_IS_E1(bp)) {
1356613472 		fw_file_name = FW_FILE_NAME_E1;
13567
-	else if (CHIP_IS_E1H(bp))
13473
+		fw_file_name_v15 = FW_FILE_NAME_E1_V15;
13474
+	} else if (CHIP_IS_E1H(bp)) {
1356813475 		fw_file_name = FW_FILE_NAME_E1H;
13569
-	else if (!CHIP_IS_E1x(bp))
13476
+		fw_file_name_v15 = FW_FILE_NAME_E1H_V15;
13477
+	} else if (!CHIP_IS_E1x(bp)) {
1357013478 		fw_file_name = FW_FILE_NAME_E2;
13571
-	else {
13479
+		fw_file_name_v15 = FW_FILE_NAME_E2_V15;
13480
+	} else {
1357213481 		BNX2X_ERR("Unsupported chip revision\n");
1357313482 		return -EINVAL;
1357413483 	}
13484
+
1357513485 	BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
1357613486 
1357713487 	rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
1357813488 	if (rc) {
13579
-		BNX2X_ERR("Can't load firmware file %s\n",
13580
-			  fw_file_name);
13581
-		goto request_firmware_exit;
13489
+		BNX2X_DEV_INFO("Trying to load older fw %s\n", fw_file_name_v15);
13490
+
13491
+		/* try to load prev version */
13492
+		rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev);
13493
+
13494
+		if (rc)
13495
+			goto request_firmware_exit;
13496
+
13497
+		bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15;
13498
+	} else {
13499
+		bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI;
13500
+		bp->fw_rev = BCM_5710_FW_REVISION_VERSION;
1358213501 	}
13502
+
13503
+	bp->fw_major = BCM_5710_FW_MAJOR_VERSION;
13504
+	bp->fw_minor = BCM_5710_FW_MINOR_VERSION;
13505
+	bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION;
1358313506 
1358413507 	rc = bnx2x_check_firmware(bp);
1358513508 	if (rc) {
....@@ -13691,8 +13614,8 @@
1369113614 
1369213615 /**
1369313616  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13694
- *
13695
- * @dev:	pci device
13617
+ * @pdev: pci device
13618
+ * @cnic_cnt: count
1369613619  *
1369713620  */
1369813621 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
....@@ -13945,7 +13868,7 @@
1394513868 	return -ENOTSUPP;
1394613869 }
1394713870 
13948
-static void bnx2x_register_phc(struct bnx2x *bp)
13871
+void bnx2x_register_phc(struct bnx2x *bp)
1394913872 {
1395013873 	/* Fill the ptp_clock_info struct and register PTP clock*/
1395113874 	bp->ptp_clock_info.owner = THIS_MODULE;
....@@ -14076,7 +13999,7 @@
1407613999 			rc = -ENOMEM;
1407714000 			goto init_one_freemem;
1407814001 		}
14079
-		bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
14002
+		bp->doorbells = ioremap(pci_resource_start(pdev, 2),
1408014003 						doorbell_size);
1408114004 	}
1408214005 	if (!bp->doorbells) {
....@@ -14147,8 +14070,6 @@
1414714070 	       dev->base_addr, bp->pdev->irq, dev->dev_addr);
1414814071 	pcie_print_link_status(bp->pdev);
1414914072 
14150
-	bnx2x_register_phc(bp);
14151
-
1415214073 	if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
1415314074 		bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
1415414075 
....@@ -14181,11 +14102,6 @@
1418114102 			   struct bnx2x *bp,
1418214103 			   bool remove_netdev)
1418314104 {
14184
-	if (bp->ptp_clock) {
14185
-		ptp_clock_unregister(bp->ptp_clock);
14186
-		bp->ptp_clock = NULL;
14187
-	}
14188
-
1418914105 	/* Delete storage MAC address */
1419014106 	if (!NO_FCOE(bp)) {
1419114107 		rtnl_lock();
....@@ -14297,10 +14213,6 @@
1429714213 
1429814214 	/* Stop Tx */
1429914215 	bnx2x_tx_disable(bp);
14300
-	/* Delete all NAPI objects */
14301
-	bnx2x_del_all_napi(bp);
14302
-	if (CNIC_LOADED(bp))
14303
-		bnx2x_del_all_napi_cnic(bp);
1430414216 	netdev_reset_tc(bp->dev);
1430514217 
1430614218 	del_timer_sync(&bp->timer);
....@@ -14405,6 +14317,11 @@
1440514317 		bnx2x_drain_tx_queues(bp);
1440614318 		bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
1440714319 		bnx2x_netif_stop(bp, 1);
14320
+		bnx2x_del_all_napi(bp);
14321
+
14322
+		if (CNIC_LOADED(bp))
14323
+			bnx2x_del_all_napi_cnic(bp);
14324
+
1440814325 		bnx2x_free_irq(bp);
1440914326 
1441014327 		/* Report UNLOAD_DONE to MCP */
....@@ -14429,14 +14346,6 @@
1442914346 	}
1443014347 
1443114348 	rtnl_unlock();
14432
-
14433
-	/* If AER, perform cleanup of the PCIe registers */
14434
-	if (bp->flags & AER_ENABLED) {
14435
-		if (pci_cleanup_aer_uncorrect_error_status(pdev))
14436
-			BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14437
-		else
14438
-			DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14439
-	}
1444014349 
1444114350 	return PCI_ERS_RESULT_RECOVERED;
1444214351 }
....@@ -14505,8 +14414,7 @@
1450514414 	.id_table    = bnx2x_pci_tbl,
1450614415 	.probe       = bnx2x_init_one,
1450714416 	.remove      = bnx2x_remove_one,
14508
-	.suspend     = bnx2x_suspend,
14509
-	.resume      = bnx2x_resume,
14417
+	.driver.pm   = &bnx2x_pm_ops,
1451014418 	.err_handler = &bnx2x_err_handler,
1451114419 #ifdef CONFIG_BNX2X_SRIOV
1451214420 	.sriov_configure = bnx2x_sriov_configure,
....@@ -14517,8 +14425,6 @@
1451714425 static int __init bnx2x_init(void)
1451814426 {
1451914427 	int ret;
14520
-
14521
-	pr_info("%s", version);
1452214428 
1452314429 	bnx2x_wq = create_singlethread_workqueue("bnx2x");
1452414430 	if (bnx2x_wq == NULL) {
....@@ -14569,9 +14475,7 @@
1456914475 
1457014476 /**
1457114477  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14572
- *
1457314478  * @bp:		driver handle
14574
- * @set:	set or clear the CAM entry
1457514479  *
1457614480  * This function will wait until the ramrod completion returns.
1457714481  * Return 0 if success, -ENODEV if ramrod doesn't return.
....@@ -14854,7 +14758,6 @@
1485414758 		if (rc)
1485514759 			break;
1485614760 
14857
-		mmiowb();
1485814761 		barrier();
1485914762 
1486014763 		/* Start accepting on iSCSI L2 ring */
....@@ -14889,7 +14792,6 @@
1488914792 		if (!bnx2x_wait_sp_comp(bp, sp_bits))
1489014793 			BNX2X_ERR("rx_mode completion timed out!\n");
1489114794 
14892
-		mmiowb();
1489314795 		barrier();
1489414796 
1489514797 		/* Unset iSCSI L2 MAC */
....@@ -15417,27 +15319,48 @@
1541715319 	return 0;
1541815320 }
1541915321 
15322
+#define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5
15323
+#define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB
15324
+#define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15325
+#define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15326
+#define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE)
15327
+#define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE)
15328
+#define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA)
15329
+#define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE)
15330
+#define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF)
15331
+#define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF)
15332
+#define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15333
+#define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15334
+
1542015335 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
1542115336 {
1542215337 	int port = BP_PORT(bp);
15338
+	u32 param, rule;
1542315339 	int rc;
1542415340 
1542515341 	if (!bp->hwtstamp_ioctl_called)
1542615342 		return 0;
1542715343 
15344
+	param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15345
+		NIG_REG_P0_TLLH_PTP_PARAM_MASK;
15346
+	rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15347
+		NIG_REG_P0_TLLH_PTP_RULE_MASK;
1542815348 	switch (bp->tx_type) {
1542915349 	case HWTSTAMP_TX_ON:
1543015350 		bp->flags |= TX_TIMESTAMPING_EN;
15431
-		REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15432
-		       NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15433
-		REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15434
-		       NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15351
+		REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK);
15352
+		REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK);
1543515353 		break;
1543615354 	case HWTSTAMP_TX_ONESTEP_SYNC:
15355
+	case HWTSTAMP_TX_ONESTEP_P2P:
1543715356 		BNX2X_ERR("One-step timestamping is not supported\n");
1543815357 		return -ERANGE;
1543915358 	}
1544015359 
15360
+	param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15361
+		NIG_REG_P0_LLH_PTP_PARAM_MASK;
15362
+	rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15363
+		NIG_REG_P0_LLH_PTP_RULE_MASK;
1544115364 	switch (bp->rx_filter) {
1544215365 	case HWTSTAMP_FILTER_NONE:
1544315366 		break;
....@@ -15451,30 +15374,24 @@
1545115374 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1545215375 		bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1545315376 		/* Initialize PTP detection for UDP/IPv4 events */
15454
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15455
-		       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15456
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15457
-		       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15377
+		REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK);
15378
+		REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK);
1545815379 		break;
1545915380 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1546015381 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1546115382 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1546215383 		bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1546315384 		/* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15464
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15465
-		       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15466
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15467
-		       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15385
+		REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK);
15386
+		REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK);
1546815387 		break;
1546915388 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1547015389 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1547115390 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1547215391 		bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1547315392 		/* Initialize PTP detection L2 events */
15474
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15475
-		       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15476
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15477
-		       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15393
+		REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK);
15394
+		REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK);
1547815395 
1547915396 		break;
1548015397 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
....@@ -15482,10 +15399,8 @@
1548215399 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1548315400 		bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1548415401 		/* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15485
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15486
-		       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15487
-		REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15488
-		       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15402
+		REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK);
15403
+		REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK);
1548915404 		break;
1549015405 	}
1549115406 
....@@ -15519,7 +15434,7 @@
1551915434 		return -EINVAL;
1552015435 	}
1552115436 
15522
-	bp->hwtstamp_ioctl_called = 1;
15437
+	bp->hwtstamp_ioctl_called = true;
1552315438 	bp->tx_type = config.tx_type;
1552415439 	bp->rx_filter = config.rx_filter;
1552515440 
....@@ -15601,7 +15516,7 @@
1560115516 		bnx2x_init_cyclecounter(bp);
1560215517 		timecounter_init(&bp->timecounter, &bp->cyclecounter,
1560315518 				 ktime_to_ns(ktime_get_real()));
15604
-		bp->timecounter_init_done = 1;
15519
+		bp->timecounter_init_done = true;
1560515520 	}
1560615521 
1560715522 	DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");