mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/misc/cardreader/rts5227.c
..
..
@@ -1,19 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
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 /* Driver for Realtek PCI-Express card reader
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  *
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  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License as published by the
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- * Free Software Foundation; either version 2, or (at your option) any
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- * later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License along
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- * with this program; if not, see <http://www.gnu.org/licenses/>.
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  *
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  * Author:
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  *   Wei WANG <wei_wang@realsil.com.cn>
..
..
@@ -68,9 +56,10 @@
68
56
 
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 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
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 {
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+	struct pci_dev *pdev = pcr->pci;
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 	u32 reg;
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61
 
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-	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
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+	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
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 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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64
 
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 	if (!rtsx_vendor_setting_valid(reg))
..
..
@@ -81,30 +70,82 @@
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 	pcr->card_drive_sel &= 0x3F;
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 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
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72
 
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-	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
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+	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
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 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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+	if (rtsx_check_mmc_support(reg))
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+		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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 	if (rtsx_reg_check_reverse_socket(reg))
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 		pcr->flags |= PCR_REVERSE_SOCKET;
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80
 }
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81
 
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-static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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+static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
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 {
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-	/* Set relink_time to 0 */
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-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
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-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
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-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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+	struct pci_dev *pdev = pcr->pci;
85
+	int l1ss;
86
+	u32 lval;
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+	struct rtsx_cr_option *option = &pcr->option;
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88
 
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-	if (pm_state == HOST_ENTER_S3)
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-		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
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+	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
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+	if (!l1ss)
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+		return;
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92
 
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-	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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+	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
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+
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+	if (CHK_PCI_PID(pcr, 0x522A)) {
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+		if (0 == (lval & 0x0F))
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+			rtsx_pci_enable_oobs_polling(pcr);
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+		else
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+			rtsx_pci_disable_oobs_polling(pcr);
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+	}
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+
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+	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
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+		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
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+	else
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+		rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
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+
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+	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
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+		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
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+	else
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+		rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
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+
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+	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
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+		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
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+	else
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+		rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
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+
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+	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
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+		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
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+	else
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+		rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
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+
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+	if (option->ltr_en) {
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+		u16 val;
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+
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+		pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
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+		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
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+			option->ltr_enabled = true;
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+			option->ltr_active = true;
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+			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
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+		} else {
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+			option->ltr_enabled = false;
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+		}
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+	}
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+
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+	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
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+				| PM_L1_1_EN | PM_L1_2_EN))
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+		option->force_clkreq_0 = false;
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+	else
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+		option->force_clkreq_0 = true;
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+
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141
 }
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142
 
104
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 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
105
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 {
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 	u16 cap;
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+	struct rtsx_cr_option *option = &pcr->option;
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147
 
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+	rts5227_init_from_cfg(pcr);
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 	rtsx_pci_init_cmd(pcr);
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150
 
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 	/* Configure GPIO as output */
..
..
@@ -126,9 +167,17 @@
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 	rts5227_fill_driving(pcr, OUTPUT_3V3);
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 	/* Configure force_clock_req */
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 	if (pcr->flags & PCR_REVERSE_SOCKET)
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-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
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+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
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 	else
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-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
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+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
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+
174
+	if (option->force_clkreq_0)
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+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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+				FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
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+	else
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+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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+				FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
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+
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 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
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182
 
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 	return rtsx_pci_send_cmd(pcr, 100);
..
..
@@ -170,35 +219,46 @@
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 {
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 	int err;
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221
 
222
+	if (pcr->option.ocp_en)
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+		rtsx_pci_enable_ocp(pcr);
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+
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 	rtsx_pci_init_cmd(pcr);
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 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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 			SD_POWER_MASK, SD_PARTIAL_POWER_ON);
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+
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 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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 			LDO3318_PWR_MASK, 0x02);
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+
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 	err = rtsx_pci_send_cmd(pcr, 100);
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 	if (err < 0)
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 		return err;
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235
 
182
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 	/* To avoid too large in-rush current */
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-	udelay(150);
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-
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+	msleep(20);
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 	rtsx_pci_init_cmd(pcr);
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 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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 			SD_POWER_MASK, SD_POWER_ON);
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+
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 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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 			LDO3318_PWR_MASK, 0x06);
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+
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+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
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+			SD_OUTPUT_EN, SD_OUTPUT_EN);
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+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
248
+			MS_OUTPUT_EN, MS_OUTPUT_EN);
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 	return rtsx_pci_send_cmd(pcr, 100);
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 }
192
251
 
193
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 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
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253
 {
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-	rtsx_pci_init_cmd(pcr);
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-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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-			SD_POWER_MASK | PMOS_STRG_MASK,
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-			SD_POWER_OFF | PMOS_STRG_400mA);
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-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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-			LDO3318_PWR_MASK, 0X00);
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-	return rtsx_pci_send_cmd(pcr, 100);
254
+	if (pcr->option.ocp_en)
255
+		rtsx_pci_disable_ocp(pcr);
256
+
257
+	rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
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+			PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
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+	rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
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+
261
+	return 0;
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262
 }
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263
 
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 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
..
..
@@ -239,7 +299,6 @@
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 	.switch_output_voltage = rts5227_switch_output_voltage,
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 	.cd_deglitch = NULL,
241
301
 	.conv_clk_and_div_n = NULL,
242
-	.force_power_down = rts5227_force_power_down,
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302
 };
244
303
 
245
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 /* SD Pull Control Enable:
..
..
@@ -353,6 +412,53 @@
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 	return 0;
354
413
 }
355
414
 
415
+static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
416
+{
417
+	int err;
418
+
419
+	if (voltage == OUTPUT_3V3) {
420
+		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
421
+		if (err < 0)
422
+			return err;
423
+	} else if (voltage == OUTPUT_1V8) {
424
+		err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
425
+		if (err < 0)
426
+			return err;
427
+		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
428
+		if (err < 0)
429
+			return err;
430
+	} else {
431
+		return -EINVAL;
432
+	}
433
+
434
+	/* set pad drive */
435
+	rtsx_pci_init_cmd(pcr);
436
+	rts5227_fill_driving(pcr, voltage);
437
+	return rtsx_pci_send_cmd(pcr, 100);
438
+}
439
+
440
+static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
441
+{
442
+	struct rtsx_cr_option *option = &pcr->option;
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+	int aspm_L1_1, aspm_L1_2;
444
+	u8 val = 0;
445
+
446
+	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
447
+	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
448
+
449
+	if (active) {
450
+		/* run, latency: 60us */
451
+		if (aspm_L1_1)
452
+			val = option->ltr_l1off_snooze_sspwrgate;
453
+	} else {
454
+		/* l1off, latency: 300us */
455
+		if (aspm_L1_2)
456
+			val = option->ltr_l1off_sspwrgate;
457
+	}
458
+
459
+	rtsx_set_l1off_sub(pcr, val);
460
+}
461
+
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 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
357
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  */
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 static const struct pcr_ops rts522a_pcr_ops = {
..
..
@@ -365,16 +471,36 @@
365
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 	.disable_auto_blink = rts5227_disable_auto_blink,
366
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 	.card_power_on = rts5227_card_power_on,
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 	.card_power_off = rts5227_card_power_off,
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-	.switch_output_voltage = rts5227_switch_output_voltage,
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+	.switch_output_voltage = rts522a_switch_output_voltage,
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 	.cd_deglitch = NULL,
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 	.conv_clk_and_div_n = NULL,
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-	.force_power_down = rts5227_force_power_down,
477
+	.set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
372
478
 };
373
479
 
374
480
 void rts522a_init_params(struct rtsx_pcr *pcr)
375
481
 {
482
+	struct rtsx_cr_option *option = &pcr->option;
483
+
376
484
 	rts5227_init_params(pcr);
377
485
 	pcr->ops = &rts522a_pcr_ops;
378
486
 	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
379
487
 	pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
488
+
489
+	option->dev_flags = LTR_L1SS_PWR_GATE_EN;
490
+	option->ltr_en = true;
491
+
492
+	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
493
+	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
494
+	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
495
+	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
496
+	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
497
+	option->ltr_l1off_sspwrgate = 0x7F;
498
+	option->ltr_l1off_snooze_sspwrgate = 0x78;
499
+
500
+	pcr->option.ocp_en = 1;
501
+	if (pcr->option.ocp_en)
502
+		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
503
+	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
504
+	pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
505
+
380
506
 }