forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376
kernel/drivers/mfd/rk630.c
....@@ -13,7 +13,7 @@
1313 #include <linux/gpio/consumer.h>
1414 #include <linux/mfd/rk630.h>
1515
16
-static int rk630_macphy_enable(struct rk630 *rk630, unsigned long rate)
16
+static int rk630_macphy_enable(struct rk630 *rk630)
1717 {
1818 u32 val;
1919 int ret;
....@@ -41,7 +41,7 @@
4141 dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
4242 return ret;
4343 }
44
- usleep_range(20, 30);
44
+ udelay(20);
4545
4646 val = BIT(12 + 16);
4747 ret = regmap_write(rk630->cru, CRU_REG(0x50), val);
....@@ -49,7 +49,7 @@
4949 dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
5050 return ret;
5151 }
52
- usleep_range(20, 30);
52
+ udelay(20);
5353
5454 /* power up && led*/
5555 val = BIT(1 + 16) | BIT(1) | BIT(2 + 16);
....@@ -68,23 +68,8 @@
6868 return ret;
6969 }
7070
71
- /* mode sel: RMII && BGS value: OTP && id */
72
- val = (2 << 14) | (0 << 12) | (0x1 << 8) | 1;
73
- switch (rate) {
74
- case 24000000:
75
- val |= 0x6 << 5;
76
- break;
77
- case 25000000:
78
- val |= 0x4 << 5;
79
- break;
80
- case 27000000:
81
- val |= 0x5 << 5;
82
- break;
83
- default:
84
- dev_err(rk630->dev, "Unsupported clock rate: %ld\n", rate);
85
- return -EINVAL;
86
- }
87
-
71
+ /* mode sel: RMII && clock sel: 24M && BGS value: OTP && id */
72
+ val = (2 << 14) | (0 << 12) | (0x1 << 8) | (6 << 5) | 1;
8873 ret = regmap_write(rk630->grf, GRF_REG(0x404), val | 0xffff0000);
8974 if (ret != 0) {
9075 dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
....@@ -113,28 +98,12 @@
11398
11499 static const struct mfd_cell rk630_devs[] = {
115100 {
116
- .name = "rk630-efuse",
117
- .of_compatible = "rockchip,rk630-efuse",
118
- },
119
- {
120
- .name = "rk630-pinctrl",
121
- .of_compatible = "rockchip,rk630-pinctrl",
122
- },
123
- {
124101 .name = "rk630-tve",
125102 .of_compatible = "rockchip,rk630-tve",
126103 },
127104 {
128
- .name = "rk630-rtc",
129
- .of_compatible = "rockchip,rk630-rtc",
130
- },
131
- {
132105 .name = "rk630-macphy",
133106 .of_compatible = "rockchip,rk630-macphy",
134
- },
135
- {
136
- .name = "rk630-codec",
137
- .of_compatible = "rockchip,rk630-codec",
138107 },
139108 };
140109
....@@ -170,27 +139,6 @@
170139 };
171140 EXPORT_SYMBOL_GPL(rk630_grf_regmap_config);
172141
173
-static const struct regmap_range rk630_pinctrl_readable_ranges[] = {
174
- regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID),
175
- regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID),
176
-};
177
-
178
-static const struct regmap_access_table rk630_pinctrl_readable_table = {
179
- .yes_ranges = rk630_pinctrl_readable_ranges,
180
- .n_yes_ranges = ARRAY_SIZE(rk630_pinctrl_readable_ranges),
181
-};
182
-
183
-const struct regmap_config rk630_pinctrl_regmap_config = {
184
- .name = "pinctrl",
185
- .reg_bits = 32,
186
- .val_bits = 32,
187
- .reg_stride = 4,
188
- .max_register = GPIO_MAX_REGISTER,
189
- .reg_format_endian = REGMAP_ENDIAN_NATIVE,
190
- .val_format_endian = REGMAP_ENDIAN_NATIVE,
191
- .rd_table = &rk630_pinctrl_readable_table,
192
-};
193
-
194142 static const struct regmap_range rk630_cru_readable_ranges[] = {
195143 regmap_reg_range(CRU_SPLL_CON0, CRU_SPLL_CON2),
196144 regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON),
....@@ -214,51 +162,13 @@
214162 .val_format_endian = REGMAP_ENDIAN_NATIVE,
215163 .rd_table = &rk630_cru_readable_table,
216164 };
217
-
218
-static const struct regmap_range rk630_rtc_readable_ranges[] = {
219
- regmap_reg_range(RTC_SET_SECONDS, RTC_CNT_3),
220
-};
221
-
222
-static const struct regmap_access_table rk630_rtc_readable_table = {
223
- .yes_ranges = rk630_rtc_readable_ranges,
224
- .n_yes_ranges = ARRAY_SIZE(rk630_rtc_readable_ranges),
225
-};
226
-
227
-const struct regmap_config rk630_rtc_regmap_config = {
228
- .name = "rtc",
229
- .reg_bits = 32,
230
- .val_bits = 32,
231
- .reg_stride = 4,
232
- .max_register = RTC_MAX_REGISTER,
233
- .reg_format_endian = REGMAP_ENDIAN_NATIVE,
234
- .val_format_endian = REGMAP_ENDIAN_NATIVE,
235
- .rd_table = &rk630_rtc_readable_table,
236
-};
165
+EXPORT_SYMBOL_GPL(rk630_cru_regmap_config);
237166
238167 int rk630_core_probe(struct rk630 *rk630)
239168 {
240169 bool macphy_enabled = false;
241170 struct device_node *np;
242
- unsigned long rate;
243171 int ret;
244
-
245
- rk630->ref_clk = devm_clk_get(rk630->dev, "ref");
246
- if (IS_ERR(rk630->ref_clk)) {
247
- dev_err(rk630->dev, "failed to get ref clk source\n");
248
- return PTR_ERR(rk630->ref_clk);
249
- }
250
-
251
- ret = clk_prepare_enable(rk630->ref_clk);
252
- if (ret < 0) {
253
- dev_err(rk630->dev, "failed to enable ref clk - %d\n", ret);
254
- return ret;
255
- }
256
- rate = clk_get_rate(rk630->ref_clk);
257
-
258
- ret = devm_add_action_or_reset(rk630->dev, (void (*) (void *))clk_disable_unprepare,
259
- rk630->ref_clk);
260
- if (ret)
261
- return ret;
262172
263173 rk630->reset_gpio = devm_gpiod_get(rk630->dev, "reset", 0);
264174 if (IS_ERR(rk630->reset_gpio)) {
....@@ -272,17 +182,6 @@
272182 gpiod_direction_output(rk630->reset_gpio, 1);
273183 usleep_range(50000, 60000);
274184 gpiod_direction_output(rk630->reset_gpio, 0);
275
-
276
- if (!rk630->irq) {
277
- dev_err(rk630->dev, "No interrupt support, no core IRQ\n");
278
- return -EINVAL;
279
- }
280
-
281
- regmap_update_bits(rk630->grf, PLUMAGE_GRF_SOC_CON0,
282
- RTC_CLAMP_EN_MASK, RTC_CLAMP_EN(1));
283
-
284
- /* disable ext_off\vbat_det\msec\sys_int\periodic interrupt by default */
285
- regmap_write(rk630->rtc, RTC_INT1_EN, 0);
286185
287186 ret = devm_mfd_add_devices(rk630->dev, PLATFORM_DEVID_NONE,
288187 rk630_devs, ARRAY_SIZE(rk630_devs),
....@@ -305,7 +204,7 @@
305204 }
306205
307206 if (macphy_enabled)
308
- rk630_macphy_enable(rk630, rate);
207
+ rk630_macphy_enable(rk630);
309208 else
310209 rk630_macphy_disable(rk630);
311210