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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/memory/tegra/mc.c
....@@ -1,17 +1,16 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
74  */
85 
96 #include <linux/clk.h>
107 #include <linux/delay.h>
8
+#include <linux/dma-mapping.h>
119 #include <linux/interrupt.h>
1210 #include <linux/kernel.h>
1311 #include <linux/module.h>
1412 #include <linux/of.h>
13
+#include <linux/of_device.h>
1514 #include <linux/platform_device.h>
1615 #include <linux/slab.h>
1716 #include <linux/sort.h>
....@@ -20,38 +19,9 @@
2019 
2120 #include "mc.h"
2221 
23
-#define MC_INTSTATUS 0x000
24
-
25
-#define MC_INTMASK 0x004
26
-
27
-#define MC_ERR_STATUS 0x08
28
-#define  MC_ERR_STATUS_TYPE_SHIFT 28
29
-#define  MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
30
-#define  MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
31
-#define  MC_ERR_STATUS_READABLE (1 << 27)
32
-#define  MC_ERR_STATUS_WRITABLE (1 << 26)
33
-#define  MC_ERR_STATUS_NONSECURE (1 << 25)
34
-#define  MC_ERR_STATUS_ADR_HI_SHIFT 20
35
-#define  MC_ERR_STATUS_ADR_HI_MASK 0x3
36
-#define  MC_ERR_STATUS_SECURITY (1 << 17)
37
-#define  MC_ERR_STATUS_RW (1 << 16)
38
-
39
-#define MC_ERR_ADR 0x0c
40
-
41
-#define MC_DECERR_EMEM_OTHERS_STATUS	0x58
42
-#define MC_SECURITY_VIOLATION_STATUS	0x74
43
-
44
-#define MC_EMEM_ARB_CFG 0x90
45
-#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)	(((x) & 0x1ff) << 0)
46
-#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK	0x1ff
47
-#define MC_EMEM_ARB_MISC0 0xd8
48
-
49
-#define MC_EMEM_ADR_CFG 0x54
50
-#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
51
-
5222 static const struct of_device_id tegra_mc_of_match[] = {
5323 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
54
-	{ .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
24
+	{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
5525 #endif
5626 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
5727 	{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
....@@ -72,7 +42,7 @@
7242 };
7343 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
7444 
75
-static int terga_mc_block_dma_common(struct tegra_mc *mc,
45
+static int tegra_mc_block_dma_common(struct tegra_mc *mc,
7646 				     const struct tegra_mc_reset *rst)
7747 {
7848 	unsigned long flags;
....@@ -88,13 +58,13 @@
8858 	return 0;
8959 }
9060 
91
-static bool terga_mc_dma_idling_common(struct tegra_mc *mc,
61
+static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
9262 				       const struct tegra_mc_reset *rst)
9363 {
9464 	return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
9565 }
9666 
97
-static int terga_mc_unblock_dma_common(struct tegra_mc *mc,
67
+static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
9868 				       const struct tegra_mc_reset *rst)
9969 {
10070 	unsigned long flags;
....@@ -110,17 +80,17 @@
11080 	return 0;
11181 }
11282 
113
-static int terga_mc_reset_status_common(struct tegra_mc *mc,
83
+static int tegra_mc_reset_status_common(struct tegra_mc *mc,
11484 					const struct tegra_mc_reset *rst)
11585 {
11686 	return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
11787 }
11888 
119
-const struct tegra_mc_reset_ops terga_mc_reset_ops_common = {
120
-	.block_dma = terga_mc_block_dma_common,
121
-	.dma_idling = terga_mc_dma_idling_common,
122
-	.unblock_dma = terga_mc_unblock_dma_common,
123
-	.reset_status = terga_mc_reset_status_common,
89
+const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
90
+	.block_dma = tegra_mc_block_dma_common,
91
+	.dma_idling = tegra_mc_dma_idling_common,
92
+	.unblock_dma = tegra_mc_unblock_dma_common,
93
+	.reset_status = tegra_mc_reset_status_common,
12494 };
12595 
12696 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
....@@ -161,7 +131,7 @@
161131 		/* block clients DMA requests */
162132 		err = rst_ops->block_dma(mc, rst);
163133 		if (err) {
164
-			dev_err(mc->dev, "Failed to block %s DMA: %d\n",
134
+			dev_err(mc->dev, "failed to block %s DMA: %d\n",
165135 				rst->name, err);
166136 			return err;
167137 		}
....@@ -171,7 +141,7 @@
171141 		/* wait for completion of the outstanding DMA requests */
172142 		while (!rst_ops->dma_idling(mc, rst)) {
173143 			if (!retries--) {
174
-				dev_err(mc->dev, "Failed to flush %s DMA\n",
144
+				dev_err(mc->dev, "failed to flush %s DMA\n",
175145 					rst->name);
176146 				return -EBUSY;
177147 			}
....@@ -184,7 +154,7 @@
184154 		/* clear clients DMA requests sitting before arbitration */
185155 		err = rst_ops->hotreset_assert(mc, rst);
186156 		if (err) {
187
-			dev_err(mc->dev, "Failed to hot reset %s: %d\n",
157
+			dev_err(mc->dev, "failed to hot reset %s: %d\n",
188158 				rst->name, err);
189159 			return err;
190160 		}
....@@ -213,7 +183,7 @@
213183 		/* take out client from hot reset */
214184 		err = rst_ops->hotreset_deassert(mc, rst);
215185 		if (err) {
216
-			dev_err(mc->dev, "Failed to deassert hot reset %s: %d\n",
186
+			dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
217187 				rst->name, err);
218188 			return err;
219189 		}
....@@ -223,7 +193,7 @@
223193 		/* allow new DMA requests to proceed to arbitration */
224194 		err = rst_ops->unblock_dma(mc, rst);
225195 		if (err) {
226
-			dev_err(mc->dev, "Failed to unblock %s DMA : %d\n",
196
+			dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
227197 				rst->name, err);
228198 			return err;
229199 		}
....@@ -283,26 +253,29 @@
283253 	tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
284254 	do_div(tick, NSEC_PER_SEC);
285255 
286
-	value = readl(mc->regs + MC_EMEM_ARB_CFG);
256
+	value = mc_readl(mc, MC_EMEM_ARB_CFG);
287257 	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
288258 	value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
289
-	writel(value, mc->regs + MC_EMEM_ARB_CFG);
259
+	mc_writel(mc, value, MC_EMEM_ARB_CFG);
290260 
291261 	/* write latency allowance defaults */
292262 	for (i = 0; i < mc->soc->num_clients; i++) {
293263 		const struct tegra_mc_la *la = &mc->soc->clients[i].la;
294264 		u32 value;
295265 
296
-		value = readl(mc->regs + la->reg);
266
+		value = mc_readl(mc, la->reg);
297267 		value &= ~(la->mask << la->shift);
298268 		value |= (la->def & la->mask) << la->shift;
299
-		writel(value, mc->regs + la->reg);
269
+		mc_writel(mc, value, la->reg);
300270 	}
271
+
272
+	/* latch new values */
273
+	mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
301274 
302275 	return 0;
303276 }
304277 
305
-void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
278
+int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
306279 {
307280 	unsigned int i;
308281 	struct tegra_mc_timing *timing = NULL;
....@@ -317,11 +290,13 @@
317290 	if (!timing) {
318291 		dev_err(mc->dev, "no memory timing registered for rate %lu\n",
319292 			rate);
320
-		return;
293
+		return -EINVAL;
321294 	}
322295 
323296 	for (i = 0; i < mc->soc->num_emem_regs; ++i)
324297 		mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
298
+
299
+	return 0;
325300 }
326301 
327302 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
....@@ -345,7 +320,7 @@
345320 	err = of_property_read_u32(node, "clock-frequency", &tmp);
346321 	if (err) {
347322 		dev_err(mc->dev,
348
-			"timing %s: failed to read rate\n", node->name);
323
+			"timing %pOFn: failed to read rate\n", node);
349324 		return err;
350325 	}
351326 
....@@ -360,8 +335,8 @@
360335 					 mc->soc->num_emem_regs);
361336 	if (err) {
362337 		dev_err(mc->dev,
363
-			"timing %s: failed to read EMEM configuration\n",
364
-			node->name);
338
+			"timing %pOFn: failed to read EMEM configuration\n",
339
+			node);
365340 		return err;
366341 	}
367342 
....@@ -575,8 +550,15 @@
575550 			break;
576551 
577552 		case MC_INT_INVALID_GART_PAGE:
578
-			dev_err_ratelimited(mc->dev, "%s\n", error);
579
-			continue;
553
+			reg = MC_GART_ERROR_REQ;
554
+			value = mc_readl(mc, reg);
555
+
556
+			id = (value >> 1) & mc->soc->client_id_mask;
557
+			desc = error_names[2];
558
+
559
+			if (value & BIT(0))
560
+				direction = "write";
561
+			break;
580562 
581563 		case MC_INT_SECURITY_VIOLATION:
582564 			reg = MC_SECURITY_VIOLATION_STATUS;
....@@ -611,15 +593,11 @@
611593 
612594 static int tegra_mc_probe(struct platform_device *pdev)
613595 {
614
-	const struct of_device_id *match;
615596 	struct resource *res;
616597 	struct tegra_mc *mc;
617598 	void *isr;
599
+	u64 mask;
618600 	int err;
619
-
620
-	match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
621
-	if (!match)
622
-		return -ENODEV;
623601 
624602 	mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
625603 	if (!mc)
....@@ -627,8 +605,16 @@
627605 
628606 	platform_set_drvdata(pdev, mc);
629607 	spin_lock_init(&mc->lock);
630
-	mc->soc = match->data;
608
+	mc->soc = of_device_get_match_data(&pdev->dev);
631609 	mc->dev = &pdev->dev;
610
+
611
+	mask = DMA_BIT_MASK(mc->soc->num_address_bits);
612
+
613
+	err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
614
+	if (err < 0) {
615
+		dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
616
+		return err;
617
+	}
632618 
633619 	/* length of MC tick in nanoseconds */
634620 	mc->tick = 30;
....@@ -638,27 +624,26 @@
638624 	if (IS_ERR(mc->regs))
639625 		return PTR_ERR(mc->regs);
640626 
627
+	mc->clk = devm_clk_get(&pdev->dev, "mc");
628
+	if (IS_ERR(mc->clk)) {
629
+		dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
630
+			PTR_ERR(mc->clk));
631
+		return PTR_ERR(mc->clk);
632
+	}
633
+
641634 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
642635 	if (mc->soc == &tegra20_mc_soc) {
643
-		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
644
-		mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
645
-		if (IS_ERR(mc->regs2))
646
-			return PTR_ERR(mc->regs2);
647
-
648636 		isr = tegra20_mc_irq;
649637 	} else
650638 #endif
651639 	{
652
-		mc->clk = devm_clk_get(&pdev->dev, "mc");
653
-		if (IS_ERR(mc->clk)) {
654
-			dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
655
-				PTR_ERR(mc->clk));
656
-			return PTR_ERR(mc->clk);
657
-		}
640
+		/* ensure that debug features are disabled */
641
+		mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
658642 
659643 		err = tegra_mc_setup_latency_allowance(mc);
660644 		if (err < 0) {
661
-			dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
645
+			dev_err(&pdev->dev,
646
+				"failed to setup latency allowance: %d\n",
662647 				err);
663648 			return err;
664649 		}
....@@ -679,11 +664,11 @@
679664 		return mc->irq;
680665 	}
681666 
682
-	WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
667
+	WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
683668 
684669 	mc_writel(mc, mc->soc->intmask, MC_INTMASK);
685670 
686
-	err = devm_request_irq(&pdev->dev, mc->irq, isr, IRQF_SHARED,
671
+	err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
687672 			       dev_name(&pdev->dev), mc);
688673 	if (err < 0) {
689674 		dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
....@@ -696,20 +681,65 @@
696681 		dev_err(&pdev->dev, "failed to register reset controller: %d\n",
697682 			err);
698683 
699
-	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
684
+	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
700685 		mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
701
-		if (IS_ERR(mc->smmu))
686
+		if (IS_ERR(mc->smmu)) {
702687 			dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
703688 				PTR_ERR(mc->smmu));
689
+			mc->smmu = NULL;
690
+		}
691
+	}
692
+
693
+	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
694
+		mc->gart = tegra_gart_probe(&pdev->dev, mc);
695
+		if (IS_ERR(mc->gart)) {
696
+			dev_err(&pdev->dev, "failed to probe GART: %ld\n",
697
+				PTR_ERR(mc->gart));
698
+			mc->gart = NULL;
699
+		}
704700 	}
705701 
706702 	return 0;
707703 }
708704 
705
+static int tegra_mc_suspend(struct device *dev)
706
+{
707
+	struct tegra_mc *mc = dev_get_drvdata(dev);
708
+	int err;
709
+
710
+	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
711
+		err = tegra_gart_suspend(mc->gart);
712
+		if (err)
713
+			return err;
714
+	}
715
+
716
+	return 0;
717
+}
718
+
719
+static int tegra_mc_resume(struct device *dev)
720
+{
721
+	struct tegra_mc *mc = dev_get_drvdata(dev);
722
+	int err;
723
+
724
+	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
725
+		err = tegra_gart_resume(mc->gart);
726
+		if (err)
727
+			return err;
728
+	}
729
+
730
+	return 0;
731
+}
732
+
733
+static const struct dev_pm_ops tegra_mc_pm_ops = {
734
+	.suspend = tegra_mc_suspend,
735
+	.resume = tegra_mc_resume,
736
+};
737
+
709738 static struct platform_driver tegra_mc_driver = {
710739 	.driver = {
711740 		.name = "tegra-mc",
712741 		.of_match_table = tegra_mc_of_match,
742
+		.pm = &tegra_mc_pm_ops,
713743 		.suppress_bind_attrs = true,
714744 	},
715745 	.prevent_deferred_probe = true,