forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/media/platform/vsp1/vsp1_regs.h
....@@ -15,8 +15,8 @@
1515  */
1616 
1717 #define VI6_CMD(n)			(0x0000 + (n) * 4)
18
-#define VI6_CMD_UPDHDR			(1 << 4)
19
-#define VI6_CMD_STRCMD			(1 << 0)
18
+#define VI6_CMD_UPDHDR			BIT(4)
19
+#define VI6_CMD_STRCMD			BIT(0)
2020 
2121 #define VI6_CLK_DCSWT			0x0018
2222 #define VI6_CLK_DCSWT_CSTPW_MASK	(0xff << 8)
....@@ -25,29 +25,29 @@
2525 #define VI6_CLK_DCSWT_CSTRW_SHIFT	0
2626 
2727 #define VI6_SRESET			0x0028
28
-#define VI6_SRESET_SRTS(n)		(1 << (n))
28
+#define VI6_SRESET_SRTS(n)		BIT(n)
2929 
3030 #define VI6_STATUS			0x0038
31
-#define VI6_STATUS_FLD_STD(n)		(1 << ((n) + 28))
32
-#define VI6_STATUS_SYS_ACT(n)		(1 << ((n) + 8))
31
+#define VI6_STATUS_FLD_STD(n)		BIT((n) + 28)
32
+#define VI6_STATUS_SYS_ACT(n)		BIT((n) + 8)
3333 
3434 #define VI6_WPF_IRQ_ENB(n)		(0x0048 + (n) * 12)
35
-#define VI6_WFP_IRQ_ENB_DFEE		(1 << 1)
36
-#define VI6_WFP_IRQ_ENB_FREE		(1 << 0)
35
+#define VI6_WFP_IRQ_ENB_DFEE		BIT(1)
36
+#define VI6_WFP_IRQ_ENB_FREE		BIT(0)
3737 
3838 #define VI6_WPF_IRQ_STA(n)		(0x004c + (n) * 12)
39
-#define VI6_WFP_IRQ_STA_DFE		(1 << 1)
40
-#define VI6_WFP_IRQ_STA_FRE		(1 << 0)
39
+#define VI6_WFP_IRQ_STA_DFE		BIT(1)
40
+#define VI6_WFP_IRQ_STA_FRE		BIT(0)
4141 
42
-#define VI6_DISP_IRQ_ENB		0x0078
43
-#define VI6_DISP_IRQ_ENB_DSTE		(1 << 8)
44
-#define VI6_DISP_IRQ_ENB_MAEE		(1 << 5)
45
-#define VI6_DISP_IRQ_ENB_LNEE(n)	(1 << (n))
42
+#define VI6_DISP_IRQ_ENB(n)		(0x0078 + (n) * 60)
43
+#define VI6_DISP_IRQ_ENB_DSTE		BIT(8)
44
+#define VI6_DISP_IRQ_ENB_MAEE		BIT(5)
45
+#define VI6_DISP_IRQ_ENB_LNEE(n)	BIT(n)
4646 
47
-#define VI6_DISP_IRQ_STA		0x007c
48
-#define VI6_DISP_IRQ_STA_DST		(1 << 8)
49
-#define VI6_DISP_IRQ_STA_MAE		(1 << 5)
50
-#define VI6_DISP_IRQ_STA_LNE(n)		(1 << (n))
47
+#define VI6_DISP_IRQ_STA(n)		(0x007c + (n) * 60)
48
+#define VI6_DISP_IRQ_STA_DST		BIT(8)
49
+#define VI6_DISP_IRQ_STA_MAE		BIT(5)
50
+#define VI6_DISP_IRQ_STA_LNE(n)		BIT(n)
5151 
5252 #define VI6_WPF_LINE_COUNT(n)		(0x0084 + (n) * 4)
5353 #define VI6_WPF_LINE_COUNT_MASK		(0x1fffff << 0)
....@@ -59,32 +59,32 @@
5959 #define VI6_DL_CTRL			0x0100
6060 #define VI6_DL_CTRL_AR_WAIT_MASK	(0xffff << 16)
6161 #define VI6_DL_CTRL_AR_WAIT_SHIFT	16
62
-#define VI6_DL_CTRL_DC2			(1 << 12)
63
-#define VI6_DL_CTRL_DC1			(1 << 8)
64
-#define VI6_DL_CTRL_DC0			(1 << 4)
65
-#define VI6_DL_CTRL_CFM0		(1 << 2)
66
-#define VI6_DL_CTRL_NH0			(1 << 1)
67
-#define VI6_DL_CTRL_DLE			(1 << 0)
62
+#define VI6_DL_CTRL_DC2			BIT(12)
63
+#define VI6_DL_CTRL_DC1			BIT(8)
64
+#define VI6_DL_CTRL_DC0			BIT(4)
65
+#define VI6_DL_CTRL_CFM0		BIT(2)
66
+#define VI6_DL_CTRL_NH0			BIT(1)
67
+#define VI6_DL_CTRL_DLE			BIT(0)
6868 
6969 #define VI6_DL_HDR_ADDR(n)		(0x0104 + (n) * 4)
7070 
7171 #define VI6_DL_SWAP			0x0114
72
-#define VI6_DL_SWAP_LWS			(1 << 2)
73
-#define VI6_DL_SWAP_WDS			(1 << 1)
74
-#define VI6_DL_SWAP_BTS			(1 << 0)
72
+#define VI6_DL_SWAP_LWS			BIT(2)
73
+#define VI6_DL_SWAP_WDS			BIT(1)
74
+#define VI6_DL_SWAP_BTS			BIT(0)
7575 
7676 #define VI6_DL_EXT_CTRL(n)		(0x011c + (n) * 36)
77
-#define VI6_DL_EXT_CTRL_NWE		(1 << 16)
77
+#define VI6_DL_EXT_CTRL_NWE		BIT(16)
7878 #define VI6_DL_EXT_CTRL_POLINT_MASK	(0x3f << 8)
7979 #define VI6_DL_EXT_CTRL_POLINT_SHIFT	8
80
-#define VI6_DL_EXT_CTRL_DLPRI		(1 << 5)
81
-#define VI6_DL_EXT_CTRL_EXPRI		(1 << 4)
82
-#define VI6_DL_EXT_CTRL_EXT		(1 << 0)
80
+#define VI6_DL_EXT_CTRL_DLPRI		BIT(5)
81
+#define VI6_DL_EXT_CTRL_EXPRI		BIT(4)
82
+#define VI6_DL_EXT_CTRL_EXT		BIT(0)
8383 
8484 #define VI6_DL_EXT_AUTOFLD_INT		BIT(0)
8585 
8686 #define VI6_DL_BODY_SIZE		0x0120
87
-#define VI6_DL_BODY_SIZE_UPD		(1 << 24)
87
+#define VI6_DL_BODY_SIZE_UPD		BIT(24)
8888 #define VI6_DL_BODY_SIZE_BS_MASK	(0x1ffff << 0)
8989 #define VI6_DL_BODY_SIZE_BS_SHIFT	0
9090 
....@@ -107,10 +107,10 @@
107107 #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT	0
108108 
109109 #define VI6_RPF_INFMT			0x0308
110
-#define VI6_RPF_INFMT_VIR		(1 << 28)
111
-#define VI6_RPF_INFMT_CIPM		(1 << 16)
112
-#define VI6_RPF_INFMT_SPYCS		(1 << 15)
113
-#define VI6_RPF_INFMT_SPUVS		(1 << 14)
110
+#define VI6_RPF_INFMT_VIR		BIT(28)
111
+#define VI6_RPF_INFMT_CIPM		BIT(16)
112
+#define VI6_RPF_INFMT_SPYCS		BIT(15)
113
+#define VI6_RPF_INFMT_SPUVS		BIT(14)
114114 #define VI6_RPF_INFMT_CEXT_ZERO		(0 << 12)
115115 #define VI6_RPF_INFMT_CEXT_EXT		(1 << 12)
116116 #define VI6_RPF_INFMT_CEXT_ONE		(2 << 12)
....@@ -120,19 +120,19 @@
120120 #define VI6_RPF_INFMT_RDTM_BT709	(2 << 9)
121121 #define VI6_RPF_INFMT_RDTM_BT709_EXT	(3 << 9)
122122 #define VI6_RPF_INFMT_RDTM_MASK		(7 << 9)
123
-#define VI6_RPF_INFMT_CSC		(1 << 8)
123
+#define VI6_RPF_INFMT_CSC		BIT(8)
124124 #define VI6_RPF_INFMT_RDFMT_MASK	(0x7f << 0)
125125 #define VI6_RPF_INFMT_RDFMT_SHIFT	0
126126 
127127 #define VI6_RPF_DSWAP			0x030c
128
-#define VI6_RPF_DSWAP_A_LLS		(1 << 11)
129
-#define VI6_RPF_DSWAP_A_LWS		(1 << 10)
130
-#define VI6_RPF_DSWAP_A_WDS		(1 << 9)
131
-#define VI6_RPF_DSWAP_A_BTS		(1 << 8)
132
-#define VI6_RPF_DSWAP_P_LLS		(1 << 3)
133
-#define VI6_RPF_DSWAP_P_LWS		(1 << 2)
134
-#define VI6_RPF_DSWAP_P_WDS		(1 << 1)
135
-#define VI6_RPF_DSWAP_P_BTS		(1 << 0)
128
+#define VI6_RPF_DSWAP_A_LLS		BIT(11)
129
+#define VI6_RPF_DSWAP_A_LWS		BIT(10)
130
+#define VI6_RPF_DSWAP_A_WDS		BIT(9)
131
+#define VI6_RPF_DSWAP_A_BTS		BIT(8)
132
+#define VI6_RPF_DSWAP_P_LLS		BIT(3)
133
+#define VI6_RPF_DSWAP_P_LWS		BIT(2)
134
+#define VI6_RPF_DSWAP_P_WDS		BIT(1)
135
+#define VI6_RPF_DSWAP_P_BTS		BIT(0)
136136 
137137 #define VI6_RPF_LOC			0x0310
138138 #define VI6_RPF_LOC_HCOORD_MASK		(0x1fff << 16)
....@@ -150,7 +150,7 @@
150150 #define VI6_RPF_ALPH_SEL_ASEL_SHIFT	28
151151 #define VI6_RPF_ALPH_SEL_IROP_MASK	(0xf << 24)
152152 #define VI6_RPF_ALPH_SEL_IROP_SHIFT	24
153
-#define VI6_RPF_ALPH_SEL_BSEL		(1 << 23)
153
+#define VI6_RPF_ALPH_SEL_BSEL		BIT(23)
154154 #define VI6_RPF_ALPH_SEL_AEXT_ZERO	(0 << 18)
155155 #define VI6_RPF_ALPH_SEL_AEXT_EXT	(1 << 18)
156156 #define VI6_RPF_ALPH_SEL_AEXT_ONE	(2 << 18)
....@@ -171,7 +171,7 @@
171171 #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT	0
172172 
173173 #define VI6_RPF_MSK_CTRL		0x031c
174
-#define VI6_RPF_MSK_CTRL_MSK_EN		(1 << 24)
174
+#define VI6_RPF_MSK_CTRL_MSK_EN		BIT(24)
175175 #define VI6_RPF_MSK_CTRL_MGR_MASK	(0xff << 16)
176176 #define VI6_RPF_MSK_CTRL_MGR_SHIFT	16
177177 #define VI6_RPF_MSK_CTRL_MGG_MASK	(0xff << 8)
....@@ -191,9 +191,9 @@
191191 #define VI6_RPF_MSK_SET_MSB_SHIFT	0
192192 
193193 #define VI6_RPF_CKEY_CTRL		0x0328
194
-#define VI6_RPF_CKEY_CTRL_CV		(1 << 4)
195
-#define VI6_RPF_CKEY_CTRL_SAPE1		(1 << 1)
196
-#define VI6_RPF_CKEY_CTRL_SAPE0		(1 << 0)
194
+#define VI6_RPF_CKEY_CTRL_CV		BIT(4)
195
+#define VI6_RPF_CKEY_CTRL_SAPE1		BIT(1)
196
+#define VI6_RPF_CKEY_CTRL_SAPE0		BIT(0)
197197 
198198 #define VI6_RPF_CKEY_SET0		0x032c
199199 #define VI6_RPF_CKEY_SET1		0x0330
....@@ -250,7 +250,7 @@
250250 
251251 #define VI6_WPF_HSZCLIP			0x1004
252252 #define VI6_WPF_VSZCLIP			0x1008
253
-#define VI6_WPF_SZCLIP_EN		(1 << 28)
253
+#define VI6_WPF_SZCLIP_EN		BIT(28)
254254 #define VI6_WPF_SZCLIP_OFST_MASK	(0xff << 16)
255255 #define VI6_WPF_SZCLIP_OFST_SHIFT	16
256256 #define VI6_WPF_SZCLIP_SIZE_MASK	(0xfff << 0)
....@@ -259,12 +259,12 @@
259259 #define VI6_WPF_OUTFMT			0x100c
260260 #define VI6_WPF_OUTFMT_PDV_MASK		(0xff << 24)
261261 #define VI6_WPF_OUTFMT_PDV_SHIFT	24
262
-#define VI6_WPF_OUTFMT_PXA		(1 << 23)
263
-#define VI6_WPF_OUTFMT_ROT		(1 << 18)
264
-#define VI6_WPF_OUTFMT_HFLP		(1 << 17)
265
-#define VI6_WPF_OUTFMT_FLP		(1 << 16)
266
-#define VI6_WPF_OUTFMT_SPYCS		(1 << 15)
267
-#define VI6_WPF_OUTFMT_SPUVS		(1 << 14)
262
+#define VI6_WPF_OUTFMT_PXA		BIT(23)
263
+#define VI6_WPF_OUTFMT_ROT		BIT(18)
264
+#define VI6_WPF_OUTFMT_HFLP		BIT(17)
265
+#define VI6_WPF_OUTFMT_FLP		BIT(16)
266
+#define VI6_WPF_OUTFMT_SPYCS		BIT(15)
267
+#define VI6_WPF_OUTFMT_SPUVS		BIT(14)
268268 #define VI6_WPF_OUTFMT_DITH_DIS		(0 << 12)
269269 #define VI6_WPF_OUTFMT_DITH_EN		(3 << 12)
270270 #define VI6_WPF_OUTFMT_DITH_MASK	(3 << 12)
....@@ -273,18 +273,18 @@
273273 #define VI6_WPF_OUTFMT_WRTM_BT709	(2 << 9)
274274 #define VI6_WPF_OUTFMT_WRTM_BT709_EXT	(3 << 9)
275275 #define VI6_WPF_OUTFMT_WRTM_MASK	(7 << 9)
276
-#define VI6_WPF_OUTFMT_CSC		(1 << 8)
276
+#define VI6_WPF_OUTFMT_CSC		BIT(8)
277277 #define VI6_WPF_OUTFMT_WRFMT_MASK	(0x7f << 0)
278278 #define VI6_WPF_OUTFMT_WRFMT_SHIFT	0
279279 
280280 #define VI6_WPF_DSWAP			0x1010
281
-#define VI6_WPF_DSWAP_P_LLS		(1 << 3)
282
-#define VI6_WPF_DSWAP_P_LWS		(1 << 2)
283
-#define VI6_WPF_DSWAP_P_WDS		(1 << 1)
284
-#define VI6_WPF_DSWAP_P_BTS		(1 << 0)
281
+#define VI6_WPF_DSWAP_P_LLS		BIT(3)
282
+#define VI6_WPF_DSWAP_P_LWS		BIT(2)
283
+#define VI6_WPF_DSWAP_P_WDS		BIT(1)
284
+#define VI6_WPF_DSWAP_P_BTS		BIT(0)
285285 
286286 #define VI6_WPF_RNDCTRL			0x1014
287
-#define VI6_WPF_RNDCTRL_CBRM		(1 << 28)
287
+#define VI6_WPF_RNDCTRL_CBRM		BIT(28)
288288 #define VI6_WPF_RNDCTRL_ABRM_TRUNC	(0 << 24)
289289 #define VI6_WPF_RNDCTRL_ABRM_ROUND	(1 << 24)
290290 #define VI6_WPF_RNDCTRL_ABRM_THRESH	(2 << 24)
....@@ -297,7 +297,7 @@
297297 #define VI6_WPF_RNDCTRL_CLMD_MASK	(3 << 12)
298298 
299299 #define VI6_WPF_ROT_CTRL		0x1018
300
-#define VI6_WPF_ROT_CTRL_LN16		(1 << 17)
300
+#define VI6_WPF_ROT_CTRL_LN16		BIT(17)
301301 #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK	(0x1fff << 0)
302302 #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT	0
303303 
....@@ -307,8 +307,8 @@
307307 #define VI6_WPF_DSTM_ADDR_C0		0x1028
308308 #define VI6_WPF_DSTM_ADDR_C1		0x102c
309309 
310
-#define VI6_WPF_WRBCK_CTRL		0x1034
311
-#define VI6_WPF_WRBCK_CTRL_WBMD		(1 << 0)
310
+#define VI6_WPF_WRBCK_CTRL(n)		(0x1034 + (n) * 0x100)
311
+#define VI6_WPF_WRBCK_CTRL_WBMD		BIT(0)
312312 
313313 /* -----------------------------------------------------------------------------
314314  * UIF Control Registers
....@@ -317,20 +317,20 @@
317317 #define VI6_UIF_OFFSET			0x100
318318 
319319 #define VI6_UIF_DISCOM_DOCMCR		0x1c00
320
-#define VI6_UIF_DISCOM_DOCMCR_CMPRU	(1 << 16)
321
-#define VI6_UIF_DISCOM_DOCMCR_CMPR	(1 << 0)
320
+#define VI6_UIF_DISCOM_DOCMCR_CMPRU	BIT(16)
321
+#define VI6_UIF_DISCOM_DOCMCR_CMPR	BIT(0)
322322 
323323 #define VI6_UIF_DISCOM_DOCMSTR		0x1c04
324
-#define VI6_UIF_DISCOM_DOCMSTR_CMPPRE	(1 << 1)
325
-#define VI6_UIF_DISCOM_DOCMSTR_CMPST	(1 << 0)
324
+#define VI6_UIF_DISCOM_DOCMSTR_CMPPRE	BIT(1)
325
+#define VI6_UIF_DISCOM_DOCMSTR_CMPST	BIT(0)
326326 
327327 #define VI6_UIF_DISCOM_DOCMCLSTR	0x1c08
328
-#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE	(1 << 1)
329
-#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST	(1 << 0)
328
+#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE	BIT(1)
329
+#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST	BIT(0)
330330 
331331 #define VI6_UIF_DISCOM_DOCMIENR		0x1c0c
332
-#define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN	(1 << 1)
333
-#define VI6_UIF_DISCOM_DOCMIENR_CMPIEN		(1 << 0)
332
+#define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN	BIT(1)
333
+#define VI6_UIF_DISCOM_DOCMIENR_CMPIEN		BIT(0)
334334 
335335 #define VI6_UIF_DISCOM_DOCMMDR		0x1c10
336336 #define VI6_UIF_DISCOM_DOCMMDR_INTHRH(n)	((n) << 16)
....@@ -338,7 +338,7 @@
338338 #define VI6_UIF_DISCOM_DOCMPMR		0x1c14
339339 #define VI6_UIF_DISCOM_DOCMPMR_CMPDFF(n)	((n) << 17)
340340 #define VI6_UIF_DISCOM_DOCMPMR_CMPDFA(n)	((n) << 8)
341
-#define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF		(1 << 7)
341
+#define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF		BIT(7)
342342 #define VI6_UIF_DISCOM_DOCMPMR_SEL(n)		((n) << 0)
343343 
344344 #define VI6_UIF_DISCOM_DOCMECRCR	0x1c18
....@@ -365,7 +365,7 @@
365365 #define VI6_DPR_HSI_ROUTE		0x2048
366366 #define VI6_DPR_BRU_ROUTE		0x204c
367367 #define VI6_DPR_ILV_BRS_ROUTE		0x2050
368
-#define VI6_DPR_ROUTE_BRSSEL		(1 << 28)
368
+#define VI6_DPR_ROUTE_BRSSEL		BIT(28)
369369 #define VI6_DPR_ROUTE_FXA_MASK		(0xff << 16)
370370 #define VI6_DPR_ROUTE_FXA_SHIFT		16
371371 #define VI6_DPR_ROUTE_FP_MASK		(0x3f << 8)
....@@ -407,10 +407,10 @@
407407 #define VI6_SRU_CTRL0_PARAM1_MASK	(0x1f << 8)
408408 #define VI6_SRU_CTRL0_PARAM1_SHIFT	8
409409 #define VI6_SRU_CTRL0_MODE_UPSCALE	(4 << 4)
410
-#define VI6_SRU_CTRL0_PARAM2		(1 << 3)
411
-#define VI6_SRU_CTRL0_PARAM3		(1 << 2)
412
-#define VI6_SRU_CTRL0_PARAM4		(1 << 1)
413
-#define VI6_SRU_CTRL0_EN		(1 << 0)
410
+#define VI6_SRU_CTRL0_PARAM2		BIT(3)
411
+#define VI6_SRU_CTRL0_PARAM3		BIT(2)
412
+#define VI6_SRU_CTRL0_PARAM4		BIT(1)
413
+#define VI6_SRU_CTRL0_EN		BIT(0)
414414 
415415 #define VI6_SRU_CTRL1			0x2204
416416 #define VI6_SRU_CTRL1_PARAM5		0x7ff
....@@ -427,18 +427,18 @@
427427 #define VI6_UDS_OFFSET			0x100
428428 
429429 #define VI6_UDS_CTRL			0x2300
430
-#define VI6_UDS_CTRL_AMD		(1 << 30)
431
-#define VI6_UDS_CTRL_FMD		(1 << 29)
432
-#define VI6_UDS_CTRL_BLADV		(1 << 28)
433
-#define VI6_UDS_CTRL_AON		(1 << 25)
434
-#define VI6_UDS_CTRL_ATHON		(1 << 24)
435
-#define VI6_UDS_CTRL_BC			(1 << 20)
436
-#define VI6_UDS_CTRL_NE_A		(1 << 19)
437
-#define VI6_UDS_CTRL_NE_RCR		(1 << 18)
438
-#define VI6_UDS_CTRL_NE_GY		(1 << 17)
439
-#define VI6_UDS_CTRL_NE_BCB		(1 << 16)
440
-#define VI6_UDS_CTRL_AMDSLH		(1 << 2)
441
-#define VI6_UDS_CTRL_TDIPC		(1 << 1)
430
+#define VI6_UDS_CTRL_AMD		BIT(30)
431
+#define VI6_UDS_CTRL_FMD		BIT(29)
432
+#define VI6_UDS_CTRL_BLADV		BIT(28)
433
+#define VI6_UDS_CTRL_AON		BIT(25)
434
+#define VI6_UDS_CTRL_ATHON		BIT(24)
435
+#define VI6_UDS_CTRL_BC			BIT(20)
436
+#define VI6_UDS_CTRL_NE_A		BIT(19)
437
+#define VI6_UDS_CTRL_NE_RCR		BIT(18)
438
+#define VI6_UDS_CTRL_NE_GY		BIT(17)
439
+#define VI6_UDS_CTRL_NE_BCB		BIT(16)
440
+#define VI6_UDS_CTRL_AMDSLH		BIT(2)
441
+#define VI6_UDS_CTRL_TDIPC		BIT(1)
442442 
443443 #define VI6_UDS_SCALE			0x2304
444444 #define VI6_UDS_SCALE_HMANT_MASK	(0xf << 28)
....@@ -477,12 +477,12 @@
477477 #define VI6_UDS_HPHASE_HEDP_SHIFT	0
478478 
479479 #define VI6_UDS_IPC			0x2318
480
-#define VI6_UDS_IPC_FIELD		(1 << 27)
480
+#define VI6_UDS_IPC_FIELD		BIT(27)
481481 #define VI6_UDS_IPC_VEDP_MASK		(0xfff << 0)
482482 #define VI6_UDS_IPC_VEDP_SHIFT		0
483483 
484484 #define VI6_UDS_HSZCLIP			0x231c
485
-#define VI6_UDS_HSZCLIP_HCEN		(1 << 28)
485
+#define VI6_UDS_HSZCLIP_HCEN		BIT(28)
486486 #define VI6_UDS_HSZCLIP_HCL_OFST_MASK	(0xff << 16)
487487 #define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT	16
488488 #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK	(0x1fff << 0)
....@@ -507,36 +507,36 @@
507507  */
508508 
509509 #define VI6_LUT_CTRL			0x2800
510
-#define VI6_LUT_CTRL_EN			(1 << 0)
510
+#define VI6_LUT_CTRL_EN			BIT(0)
511511 
512512 /* -----------------------------------------------------------------------------
513513  * CLU Control Registers
514514  */
515515 
516516 #define VI6_CLU_CTRL			0x2900
517
-#define VI6_CLU_CTRL_AAI		(1 << 28)
518
-#define VI6_CLU_CTRL_MVS		(1 << 24)
517
+#define VI6_CLU_CTRL_AAI		BIT(28)
518
+#define VI6_CLU_CTRL_MVS		BIT(24)
519519 #define VI6_CLU_CTRL_AX1I_2D		(3 << 14)
520520 #define VI6_CLU_CTRL_AX2I_2D		(1 << 12)
521521 #define VI6_CLU_CTRL_OS0_2D		(3 << 8)
522522 #define VI6_CLU_CTRL_OS1_2D		(1 << 6)
523523 #define VI6_CLU_CTRL_OS2_2D		(3 << 4)
524
-#define VI6_CLU_CTRL_M2D		(1 << 1)
525
-#define VI6_CLU_CTRL_EN			(1 << 0)
524
+#define VI6_CLU_CTRL_M2D		BIT(1)
525
+#define VI6_CLU_CTRL_EN			BIT(0)
526526 
527527 /* -----------------------------------------------------------------------------
528528  * HST Control Registers
529529  */
530530 
531531 #define VI6_HST_CTRL			0x2a00
532
-#define VI6_HST_CTRL_EN			(1 << 0)
532
+#define VI6_HST_CTRL_EN			BIT(0)
533533 
534534 /* -----------------------------------------------------------------------------
535535  * HSI Control Registers
536536  */
537537 
538538 #define VI6_HSI_CTRL			0x2b00
539
-#define VI6_HSI_CTRL_EN			(1 << 0)
539
+#define VI6_HSI_CTRL_EN			BIT(0)
540540 
541541 /* -----------------------------------------------------------------------------
542542  * BRS and BRU Control Registers
....@@ -563,7 +563,7 @@
563563 #define VI6_BRS_BASE			0x3900
564564 
565565 #define VI6_BRU_INCTRL			0x0000
566
-#define VI6_BRU_INCTRL_NRM		(1 << 28)
566
+#define VI6_BRU_INCTRL_NRM		BIT(28)
567567 #define VI6_BRU_INCTRL_DnON		(1 << (16 + (n)))
568568 #define VI6_BRU_INCTRL_DITHn_OFF	(0 << ((n) * 4))
569569 #define VI6_BRU_INCTRL_DITHn_18BPP	(1 << ((n) * 4))
....@@ -597,7 +597,7 @@
597597 #define VI6_BRU_VIRRPF_COL_BCB_SHIFT	0
598598 
599599 #define VI6_BRU_CTRL(n)			(0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4))
600
-#define VI6_BRU_CTRL_RBC		(1 << 31)
600
+#define VI6_BRU_CTRL_RBC		BIT(31)
601601 #define VI6_BRU_CTRL_DSTSEL_BRUIN(n)	(((n) <= 3 ? (n) : (n)+1) << 20)
602602 #define VI6_BRU_CTRL_DSTSEL_VRPF	(4 << 20)
603603 #define VI6_BRU_CTRL_DSTSEL_MASK	(7 << 20)
....@@ -610,7 +610,7 @@
610610 #define VI6_BRU_CTRL_AROP_MASK		(0xf << 0)
611611 
612612 #define VI6_BRU_BLD(n)			(0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4))
613
-#define VI6_BRU_BLD_CBES		(1 << 31)
613
+#define VI6_BRU_BLD_CBES		BIT(31)
614614 #define VI6_BRU_BLD_CCMDX_DST_A		(0 << 28)
615615 #define VI6_BRU_BLD_CCMDX_255_DST_A	(1 << 28)
616616 #define VI6_BRU_BLD_CCMDX_SRC_A		(2 << 28)
....@@ -624,7 +624,7 @@
624624 #define VI6_BRU_BLD_CCMDY_COEFY		(4 << 24)
625625 #define VI6_BRU_BLD_CCMDY_MASK		(7 << 24)
626626 #define VI6_BRU_BLD_CCMDY_SHIFT		24
627
-#define VI6_BRU_BLD_ABES		(1 << 23)
627
+#define VI6_BRU_BLD_ABES		BIT(23)
628628 #define VI6_BRU_BLD_ACMDX_DST_A		(0 << 20)
629629 #define VI6_BRU_BLD_ACMDX_255_DST_A	(1 << 20)
630630 #define VI6_BRU_BLD_ACMDX_SRC_A		(2 << 20)
....@@ -662,11 +662,11 @@
662662 #define VI6_HGO_SIZE_HSIZE_SHIFT	16
663663 #define VI6_HGO_SIZE_VSIZE_SHIFT	0
664664 #define VI6_HGO_MODE			0x3008
665
-#define VI6_HGO_MODE_STEP		(1 << 10)
666
-#define VI6_HGO_MODE_MAXRGB		(1 << 7)
667
-#define VI6_HGO_MODE_OFSB_R		(1 << 6)
668
-#define VI6_HGO_MODE_OFSB_G		(1 << 5)
669
-#define VI6_HGO_MODE_OFSB_B		(1 << 4)
665
+#define VI6_HGO_MODE_STEP		BIT(10)
666
+#define VI6_HGO_MODE_MAXRGB		BIT(7)
667
+#define VI6_HGO_MODE_OFSB_R		BIT(6)
668
+#define VI6_HGO_MODE_OFSB_G		BIT(5)
669
+#define VI6_HGO_MODE_OFSB_B		BIT(4)
670670 #define VI6_HGO_MODE_HRATIO_SHIFT	2
671671 #define VI6_HGO_MODE_VRATIO_SHIFT	0
672672 #define VI6_HGO_LB_TH			0x300c
....@@ -687,7 +687,7 @@
687687 #define VI6_HGO_EXT_HIST_ADDR		0x335c
688688 #define VI6_HGO_EXT_HIST_DATA		0x3360
689689 #define VI6_HGO_REGRST			0x33fc
690
-#define VI6_HGO_REGRST_RCLEA		(1 << 0)
690
+#define VI6_HGO_REGRST_RCLEA		BIT(0)
691691 
692692 /* -----------------------------------------------------------------------------
693693  * HGT Control Registers
....@@ -706,14 +706,14 @@
706706 #define VI6_HGT_HUE_AREA_LOWER_SHIFT	16
707707 #define VI6_HGT_HUE_AREA_UPPER_SHIFT	0
708708 #define VI6_HGT_LB_TH			0x3424
709
-#define VI6_HGT_LBn_H(n)		(0x3438 + (n) * 8)
709
+#define VI6_HGT_LBn_H(n)		(0x3428 + (n) * 8)
710710 #define VI6_HGT_LBn_V(n)		(0x342c + (n) * 8)
711711 #define VI6_HGT_HISTO(m, n)		(0x3450 + (m) * 128 + (n) * 4)
712712 #define VI6_HGT_MAXMIN			0x3750
713713 #define VI6_HGT_SUM			0x3754
714714 #define VI6_HGT_LB_DET			0x3758
715715 #define VI6_HGT_REGRST			0x37fc
716
-#define VI6_HGT_REGRST_RCLEA		(1 << 0)
716
+#define VI6_HGT_REGRST_RCLEA		BIT(0)
717717 
718718 /* -----------------------------------------------------------------------------
719719  * LIF Control Registers
....@@ -724,9 +724,9 @@
724724 #define VI6_LIF_CTRL			0x3b00
725725 #define VI6_LIF_CTRL_OBTH_MASK		(0x7ff << 16)
726726 #define VI6_LIF_CTRL_OBTH_SHIFT		16
727
-#define VI6_LIF_CTRL_CFMT		(1 << 4)
728
-#define VI6_LIF_CTRL_REQSEL		(1 << 1)
729
-#define VI6_LIF_CTRL_LIF_EN		(1 << 0)
727
+#define VI6_LIF_CTRL_CFMT		BIT(4)
728
+#define VI6_LIF_CTRL_REQSEL		BIT(1)
729
+#define VI6_LIF_CTRL_LIF_EN		BIT(0)
730730 
731731 #define VI6_LIF_CSBTH			0x3b04
732732 #define VI6_LIF_CSBTH_HBTH_MASK		(0x7ff << 16)
....@@ -735,7 +735,7 @@
735735 #define VI6_LIF_CSBTH_LBTH_SHIFT	0
736736 
737737 #define VI6_LIF_LBA			0x3b0c
738
-#define VI6_LIF_LBA_LBA0		(1 << 31)
738
+#define VI6_LIF_LBA_LBA0		BIT(31)
739739 #define VI6_LIF_LBA_LBA1_MASK		(0xfff << 16)
740740 #define VI6_LIF_LBA_LBA1_SHIFT		16
741741