mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/media/platform/rockchip/isp/rkisp.c
..
..
@@ -213,17 +213,16 @@
213
213
 		max_h = CIF_ISP_INPUT_H_MAX_V21;
214
214
 		break;
215
215
 	case ISP_V30:
216
-		if (dev->hw_dev->is_unite) {
217
-			max_w = CIF_ISP_INPUT_W_MAX_V30_UNITE;
218
-			max_h = CIF_ISP_INPUT_H_MAX_V30_UNITE;
219
-		} else {
220
-			max_w = CIF_ISP_INPUT_W_MAX_V30;
221
-			max_h = CIF_ISP_INPUT_H_MAX_V30;
222
-		}
216
+		max_w = dev->hw_dev->unite ?
217
+			CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
218
+		max_h = dev->hw_dev->unite ?
219
+			CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
223
220
 		break;
224
221
 	case ISP_V32:
225
-		max_w = CIF_ISP_INPUT_W_MAX_V32;
226
-		max_h = CIF_ISP_INPUT_H_MAX_V32;
222
+		max_w = dev->hw_dev->unite ?
223
+			CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
224
+		max_h = dev->hw_dev->unite ?
225
+			CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
227
226
 		break;
228
227
 	case ISP_V32_L:
229
228
 		max_w = CIF_ISP_INPUT_W_MAX_V32_L;
..
..
@@ -518,7 +517,9 @@
518
517
 	do_div(data_rate, 1000 * 1000);
519
518
 	/* increase margin: 25% * num */
520
519
 	data_rate += (data_rate >> 2) * num;
521
-
520
+	/* one frame two-run, data double */
521
+	if (hw->is_multi_overflow && num > 1)
522
+		data_rate *= 2;
522
523
 	/* compare with isp clock adjustment table */
523
524
 	for (i = 0; i < hw->num_clk_rate_tbl; i++)
524
525
 		if (data_rate <= hw->clk_rate_tbl[i].clk_rate)
..
..
@@ -528,7 +529,7 @@
528
529
 
529
530
 	/* set isp clock rate */
530
531
 	rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
531
-	if (hw->is_unite)
532
+	if (hw->unite == ISP_UNITE_TWO)
532
533
 		rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
533
534
 	/* aclk equal to core clk */
534
535
 	if (dev->isp_ver == ISP_V32)
..
..
@@ -541,48 +542,39 @@
541
542
 	struct rkisp_hw_dev *hw = dev->hw_dev;
542
543
 
543
544
 	if (on) {
544
-		/* enable bay3d and mi */
545
+		/* enable mi */
545
546
 		rkisp_update_regs(dev, ISP3X_MI_WR_CTRL, ISP3X_MI_WR_CTRL);
546
547
 		rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
547
-		if (dev->isp_ver == ISP_V21) {
548
-			rkisp_update_regs(dev, ISP21_BAY3D_CTRL, ISP21_BAY3D_CTRL);
549
-		} else if (dev->isp_ver == ISP_V30) {
548
+		if (dev->isp_ver == ISP_V30) {
550
549
 			rkisp_update_regs(dev, ISP3X_MPFBC_CTRL, ISP3X_MPFBC_CTRL);
551
550
 			rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
552
-			rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL);
553
551
 			rkisp_update_regs(dev, ISP3X_SWS_CFG, ISP3X_SWS_CFG);
554
552
 		} else if (dev->isp_ver == ISP_V32) {
555
553
 			rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
556
554
 			rkisp_update_regs(dev, ISP32_MI_BPDS_WR_CTRL, ISP32_MI_BPDS_WR_CTRL);
557
555
 			rkisp_update_regs(dev, ISP32_MI_MPDS_WR_CTRL, ISP32_MI_MPDS_WR_CTRL);
558
-			rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL);
559
556
 		}
560
557
 	} else {
561
-		/* disabled bay3d and mi. rv1106 sdmmc workaround, 3a_wr no close */
558
+		/* disabled mi. rv1106 sdmmc workaround, 3a_wr no close */
562
559
 		writel(CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN,
563
560
 		       hw->base_addr + ISP3X_MI_WR_CTRL);
564
-		if (dev->isp_ver == ISP_V21) {
565
-			writel(0, hw->base_addr + ISP21_BAY3D_CTRL);
566
-		} else if (dev->isp_ver == ISP_V30) {
561
+		if (dev->isp_ver == ISP_V30) {
567
562
 			writel(0, hw->base_addr + ISP3X_MPFBC_CTRL);
568
563
 			writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
569
-			writel(0, hw->base_addr + ISP3X_BAY3D_CTRL);
570
564
 			writel(0xc, hw->base_addr + ISP3X_SWS_CFG);
571
-			if (hw->is_unite) {
565
+			if (hw->unite == ISP_UNITE_TWO) {
572
566
 				writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL);
573
567
 				writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL);
574
568
 				writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL);
575
-				writel(0, hw->base_next_addr + ISP3X_BAY3D_CTRL);
576
569
 				writel(0xc, hw->base_next_addr + ISP3X_SWS_CFG);
577
570
 			}
578
571
 		} else if (dev->isp_ver == ISP_V32) {
579
572
 			writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
580
573
 			writel(0, hw->base_addr + ISP32_MI_BPDS_WR_CTRL);
581
574
 			writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL);
582
-			writel(0, hw->base_addr + ISP3X_BAY3D_CTRL);
583
575
 		}
584
576
 	}
585
-	rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
577
+	rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
586
578
 }
587
579
 
588
580
 /*
..
..
@@ -602,7 +594,8 @@
602
594
 	hw->cur_dev_id = dev->dev_id;
603
595
 	rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
604
596
 
605
-	if (hw->is_multi_overflow && is_try)
597
+	/* isp process the same frame */
598
+	if (is_try)
606
599
 		goto run_next;
607
600
 
608
601
 	val = 0;
..
..
@@ -632,13 +625,12 @@
632
625
 	}
633
626
 
634
627
 	if (rd_mode != dev->rd_mode) {
635
-		rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK,
636
-				     val, false, hw->is_unite);
628
+		rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, val, false);
637
629
 		dev->skip_frame = 2;
638
630
 		is_upd = true;
639
631
 	}
640
632
 
641
-	if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) {
633
+	if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL) {
642
634
 		if (dev->rd_mode != rd_mode && dev->br_dev.en) {
643
635
 			tmp = dev->isp_sdev.in_crop.height;
644
636
 			val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false);
..
..
@@ -659,12 +651,15 @@
659
651
 	}
660
652
 	dev->rd_mode = rd_mode;
661
653
 
662
-	rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
663
-			       dev->isp_sdev.quantization);
664
-	rkisp_params_cfg(params_vdev, cur_frame_id);
665
-	rkisp_config_cmsk(dev);
666
-	rkisp_stream_frame_start(dev, 0);
667
-	if (!hw->is_single && !is_try) {
654
+	if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_LEFT) {
655
+		rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
656
+				       dev->isp_sdev.quantization);
657
+		rkisp_params_cfg(params_vdev, cur_frame_id);
658
+		rkisp_config_cmsk(dev);
659
+		rkisp_stream_frame_start(dev, 0);
660
+	}
661
+
662
+	if (!hw->is_single) {
668
663
 		/* multi sensor need to reset isp resize mode if scale up */
669
664
 		val = 0;
670
665
 		if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
..
..
@@ -700,7 +695,7 @@
700
695
 		} else {
701
696
 			if (dev->isp_ver == ISP_V32_L)
702
697
 				rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
703
-			rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
698
+			rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
704
699
 		}
705
700
 		/* sensor mode & index */
706
701
 		if (dev->isp_ver >= ISP_V21) {
..
..
@@ -711,7 +706,7 @@
711
706
 			else
712
707
 				val |= ISP21_SENSOR_MODE(dev->multi_mode);
713
708
 			writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
714
-			if (hw->is_unite)
709
+			if (hw->unite == ISP_UNITE_TWO)
715
710
 				writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
716
711
 			v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
717
712
 				 "sensor mode:%d index:%d | 0x%x\n",
..
..
@@ -731,36 +726,88 @@
731
726
 	else
732
727
 		dev->rdbk_cnt_x1++;
733
728
 	dev->rdbk_cnt++;
734
-
735
-	rkisp_params_cfgsram(params_vdev);
736
-	params_vdev->rdbk_times = dma2frm + 1;
729
+	if (dev->isp_ver == ISP_V20)
730
+		params_vdev->rdbk_times = dma2frm + 1;
737
731
 
738
732
 run_next:
739
-	if (hw->is_multi_overflow && !dev->is_first_double) {
740
-		stats_vdev->rdbk_drop = false;
741
-		if (dev->sw_rd_cnt) {
742
-			rkisp_multi_overflow_hdl(dev, false);
743
-			params_vdev->rdbk_times += dev->sw_rd_cnt;
744
-			stats_vdev->rdbk_drop = true;
745
-			is_upd = true;
746
-		} else if (is_try) {
733
+	rkisp_params_cfgsram(params_vdev);
734
+	stats_vdev->rdbk_drop = false;
735
+	if (dev->is_frame_double) {
736
+		is_upd = true;
737
+		if (is_try) {
738
+			/* the frame second running to on mi */
747
739
 			rkisp_multi_overflow_hdl(dev, true);
748
-			is_upd = true;
740
+			rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE);
741
+
742
+			val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME;
743
+			if (dev->isp_ver == ISP_V32)
744
+				val |= ISP32_SHP_FST_FRAME;
745
+			else
746
+				val |= ISP3X_CNR_FST_FRAME;
747
+			rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false);
748
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
749
+			writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
750
+			if (hw->unite == ISP_UNITE_TWO)
751
+				writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
752
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
753
+			writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
754
+			if (hw->unite == ISP_UNITE_TWO)
755
+				writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
756
+		} else {
757
+			/* the frame first running to off mi to save bandwidth */
758
+			rkisp_multi_overflow_hdl(dev, false);
759
+
760
+			/* FST_FRAME no to read sram thumb */
761
+			val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME;
762
+			if (dev->isp_ver == ISP_V32)
763
+				val |= ISP32_SHP_FST_FRAME;
764
+			else
765
+				val |= ISP3X_CNR_FST_FRAME;
766
+			rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false);
767
+			/* ADRC low iir thumb weight for first sensor switch */
768
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
769
+			val &= ~ISP3X_DRC_IIR_WEIGHT_MASK;
770
+			writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
771
+			if (hw->unite == ISP_UNITE_TWO)
772
+				writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
773
+			/* ADRC iir5x5 and cur3x3 weight */
774
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
775
+			val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK;
776
+			writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
777
+			if (hw->unite == ISP_UNITE_TWO)
778
+				writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
779
+			/* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
780
+			val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
781
+			val |= ISP3X_YNR_THUMB_MIX_CUR_EN;
782
+			writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
783
+			if (hw->unite == ISP_UNITE_TWO)
784
+				writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
785
+			if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) {
786
+				/* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
787
+				val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
788
+				val |= ISP3X_CNR_THUMB_MIX_CUR_EN;
789
+				writel(val, hw->base_addr + ISP3X_CNR_CTRL);
790
+				if (hw->unite == ISP_UNITE_TWO)
791
+					writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
792
+			}
793
+			stats_vdev->rdbk_drop = true;
749
794
 		}
750
795
 	}
751
796
 
752
-	/* read 3d lut at frame end */
797
+	/* disable isp force update to read 3dlut
798
+	 * 3dlut auto update at frame end for single sensor
799
+	 */
753
800
 	if (hw->is_single && is_upd &&
754
801
 	    rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
755
-		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true, hw->is_unite);
802
+		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true);
756
803
 		is_3dlut_upd = true;
757
804
 	}
758
805
 	if (is_upd) {
759
806
 		val = rkisp_read(dev, ISP_CTRL, false);
760
807
 		val |= CIF_ISP_CTRL_ISP_CFG_UPD;
761
-		rkisp_unite_write(dev, ISP_CTRL, val, true, hw->is_unite);
808
+		rkisp_unite_write(dev, ISP_CTRL, val, true);
762
809
 		/* bayer pat after ISP_CFG_UPD for multi sensor to read lsc r/g/b table */
763
-		rkisp_update_regs(dev, ISP_ACQ_PROP, ISP_ACQ_PROP);
810
+		rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
764
811
 		/* fix ldch multi sensor case:
765
812
 		 * ldch will pre-read data when en and isp force upd or frame end,
766
813
 		 * udelay for ldch pre-read data.
..
..
@@ -771,12 +818,12 @@
771
818
 			udelay(50);
772
819
 			val &= ~(BIT(0) | BIT(31));
773
820
 			writel(val, hw->base_addr + ISP_LDCH_BASE);
774
-			if (hw->is_unite)
821
+			if (hw->unite == ISP_UNITE_TWO)
775
822
 				writel(val, hw->base_next_addr + ISP_LDCH_BASE);
776
823
 		}
777
824
 	}
778
825
 	if (is_3dlut_upd)
779
-		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true, hw->is_unite);
826
+		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true);
780
827
 
781
828
 	/* if output stream enable, wait it end */
782
829
 	val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
..
..
@@ -807,11 +854,13 @@
807
854
 	val &= ~SW_IBUF_OP_MODE(0xf);
808
855
 	tmp = SW_IBUF_OP_MODE(dev->rd_mode);
809
856
 	val |= tmp | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm);
857
+	if (dev->isp_ver > ISP_V20)
858
+		dma2frm = dev->sw_rd_cnt;
810
859
 	v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
811
-		 "readback frame:%d time:%d 0x%x\n",
812
-		 cur_frame_id, dma2frm + 1, val);
860
+		 "readback frame:%d time:%d 0x%x try:%d\n",
861
+		 cur_frame_id, dma2frm + 1, val, is_try);
813
862
 	if (!hw->is_shutdown)
814
-		rkisp_unite_write(dev, CSI2RX_CTRL0, val, true, hw->is_unite);
863
+		rkisp_unite_write(dev, CSI2RX_CTRL0, val, true);
815
864
 }
816
865
 
817
866
 static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current)
..
..
@@ -865,6 +914,12 @@
865
914
 			isp = dev;
866
915
 			is_try = true;
867
916
 			times = 0;
917
+			if (hw->unite == ISP_UNITE_ONE) {
918
+				if (dev->sw_rd_cnt < 2)
919
+					isp->unite_index = ISP_UNITE_RIGHT;
920
+				if (!hw->is_multi_overflow || (dev->sw_rd_cnt & 0x1))
921
+					is_try = false;
922
+			}
868
923
 			goto end;
869
924
 		}
870
925
 		hw->is_idle = true;
..
..
@@ -914,17 +969,40 @@
914
969
 		times = t.times;
915
970
 		hw->cur_dev_id = id;
916
971
 		hw->is_idle = false;
972
+		/* this frame will read count by isp */
917
973
 		isp->sw_rd_cnt = 0;
918
-		if (hw->is_multi_overflow && (hw->pre_dev_id != id)) {
974
+		/* frame double for multi camera resolution out of hardware limit
975
+		 * first for HW save this camera information, and second to output image
976
+		 */
977
+		isp->is_frame_double = false;
978
+		if (hw->is_multi_overflow &&
979
+		    (hw->unite == ISP_UNITE_ONE ||
980
+		     (hw->pre_dev_id != -1 && hw->pre_dev_id != id))) {
981
+			isp->is_frame_double = true;
919
982
 			isp->sw_rd_cnt = 1;
920
983
 			times = 0;
921
984
 		}
985
+		/* resolution out of hardware limit
986
+		 * frame is vertically divided into left and right
987
+		 */
988
+		isp->unite_index = ISP_UNITE_LEFT;
989
+		if (hw->unite == ISP_UNITE_ONE) {
990
+			isp->sw_rd_cnt *= 2;
991
+			isp->sw_rd_cnt += 1;
992
+		}
993
+		/* first frame handle twice for thunderboot
994
+		 * first output stats to AIQ and wait new params to run second
995
+		 */
922
996
 		if (isp->is_pre_on && t.frame_id == 0) {
923
997
 			isp->is_first_double = true;
924
998
 			isp->skip_frame = 1;
925
-			isp->sw_rd_cnt = 0;
999
+			if (hw->unite != ISP_UNITE_ONE) {
1000
+				isp->sw_rd_cnt = 0;
1001
+				isp->is_frame_double = false;
1002
+			}
926
1003
 			rkisp_fast_switch_rx_buf(isp, false);
927
1004
 		}
1005
+		isp->params_vdev.rdbk_times = isp->sw_rd_cnt + 1;
928
1006
 	}
929
1007
 end:
930
1008
 	spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
..
..
@@ -982,12 +1060,6 @@
982
1060
 {
983
1061
 	u32 val = 0;
984
1062
 
985
-	if (dev->hw_dev->is_multi_overflow &&
986
-	    dev->sw_rd_cnt &&
987
-	    irq & ISP_FRAME_END &&
988
-	    !dev->is_first_double)
989
-		goto end;
990
-
991
1063
 	dev->irq_ends |= (irq & dev->irq_ends_mask);
992
1064
 	v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
993
1065
 		 "%s irq:0x%x ends:0x%x mask:0x%x\n",
..
..
@@ -1001,6 +1073,9 @@
1001
1073
 	if ((dev->irq_ends & dev->irq_ends_mask) != dev->irq_ends_mask ||
1002
1074
 	    !IS_HDR_RDBK(dev->rd_mode))
1003
1075
 		return;
1076
+
1077
+	if (dev->sw_rd_cnt)
1078
+		goto end;
1004
1079
 
1005
1080
 	if (dev->is_first_double) {
1006
1081
 		rkisp_fast_switch_rx_buf(dev, true);
..
..
@@ -1068,26 +1143,25 @@
1068
1143
 {
1069
1144
 	struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
1070
1145
 	u32 width = out_crop->width, mult = 1;
1071
-	bool is_unite = dev->hw_dev->is_unite;
1146
+	u32 unite = dev->hw_dev->unite;
1072
1147
 
1073
1148
 	/* isp2.0 no ism */
1074
1149
 	if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 ||
1075
1150
 	    dev->isp_ver == ISP_V32_L)
1076
1151
 		return;
1077
1152
 
1078
-	if (is_unite)
1153
+	if (unite)
1079
1154
 		width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1080
-	rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false, is_unite);
1081
-	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false, is_unite);
1082
-	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false, is_unite);
1083
-	rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false, is_unite);
1084
-	rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false, is_unite);
1085
-	rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false, is_unite);
1086
-	rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false, is_unite);
1155
+	rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false);
1156
+	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false);
1157
+	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false);
1158
+	rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false);
1159
+	rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false);
1160
+	rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false);
1161
+	rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false);
1087
1162
 	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
1088
1163
 		mult = 2;
1089
-	rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult,
1090
-			  false, is_unite);
1164
+	rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false);
1091
1165
 
1092
1166
 	if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
1093
1167
 		return;
..
..
@@ -1389,20 +1463,18 @@
1389
1463
 
1390
1464
 	for (i = 0; i < 9; i++)
1391
1465
 		rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4,
1392
-				  *(coeff + i), false, dev->hw_dev->is_unite);
1466
+				  *(coeff + i), false);
1393
1467
 
1394
1468
 	val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
1395
1469
 
1396
1470
 	if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
1397
1471
 		rkisp_unite_write(dev, CIF_ISP_CTRL, val |
1398
1472
 				  CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1399
-				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA,
1400
-				  false, dev->hw_dev->is_unite);
1473
+				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false);
1401
1474
 	else
1402
1475
 		rkisp_unite_write(dev, CIF_ISP_CTRL, val &
1403
1476
 				  ~(CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1404
-				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA),
1405
-				  false, dev->hw_dev->is_unite);
1477
+				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA), false);
1406
1478
 }
1407
1479
 
1408
1480
 static void rkisp_config_cmsk_single(struct rkisp_device *dev,
..
..
@@ -1601,7 +1673,7 @@
1601
1673
 	cfg = dev->cmsk_cfg;
1602
1674
 	spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1603
1675
 
1604
-	if (!dev->hw_dev->is_unite)
1676
+	if (!dev->hw_dev->unite)
1605
1677
 		rkisp_config_cmsk_single(dev, &cfg);
1606
1678
 	else
1607
1679
 		rkisp_config_cmsk_dual(dev, &cfg);
..
..
@@ -1616,7 +1688,7 @@
1616
1688
 	struct ispsd_out_fmt *out_fmt;
1617
1689
 	struct v4l2_rect *in_crop;
1618
1690
 	struct rkisp_sensor_info *sensor;
1619
-	bool is_unite = dev->hw_dev->is_unite;
1691
+	bool is_unite = !!dev->hw_dev->unite;
1620
1692
 	u32 isp_ctrl = 0;
1621
1693
 	u32 irq_mask = 0;
1622
1694
 	u32 signal = 0;
..
..
@@ -1646,22 +1718,20 @@
1646
1718
 			    in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 ||
1647
1719
 			    in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) {
1648
1720
 				if (dev->isp_ver >= ISP_V20)
1649
-					rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1650
-							  0, false, is_unite);
1721
+					rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false);
1651
1722
 				else
1652
1723
 					rkisp_write(dev, CIF_ISP_DEMOSAIC,
1653
-						CIF_ISP_DEMOSAIC_BYPASS |
1654
-						CIF_ISP_DEMOSAIC_TH(0xc), false);
1724
+						    CIF_ISP_DEMOSAIC_BYPASS |
1725
+						    CIF_ISP_DEMOSAIC_TH(0xc), false);
1655
1726
 			} else {
1656
1727
 				if (dev->isp_ver >= ISP_V20)
1657
1728
 					rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1658
1729
 							  SW_DEBAYER_EN |
1659
1730
 							  SW_DEBAYER_FILTER_G_EN |
1660
-							  SW_DEBAYER_FILTER_C_EN,
1661
-							  false, is_unite);
1731
+							  SW_DEBAYER_FILTER_C_EN, false);
1662
1732
 				else
1663
1733
 					rkisp_write(dev, CIF_ISP_DEMOSAIC,
1664
-						CIF_ISP_DEMOSAIC_TH(0xc), false);
1734
+						    CIF_ISP_DEMOSAIC_TH(0xc), false);
1665
1735
 			}
1666
1736
 
1667
1737
 			if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
..
..
@@ -1714,38 +1784,31 @@
1714
1784
 	if (rkisp_read_reg_cache(dev, CIF_ISP_CTRL) & ISP32_MIR_ENABLE)
1715
1785
 		isp_ctrl |= ISP32_MIR_ENABLE;
1716
1786
 
1717
-	rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false, is_unite);
1787
+	rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false);
1718
1788
 	acq_prop |= signal | in_fmt->yuv_seq |
1719
1789
 		CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
1720
1790
 		CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
1721
-	rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false, is_unite);
1722
-	rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true, is_unite);
1791
+	rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false);
1792
+	rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true);
1723
1793
 
1724
1794
 	if (is_unite)
1725
1795
 		width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1726
1796
 	/* Acquisition Size */
1727
-	rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left,
1728
-			  false, is_unite);
1729
-	rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top,
1730
-			  false, is_unite);
1731
-	rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width,
1732
-			  false, is_unite);
1797
+	rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false);
1798
+	rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false);
1799
+	rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width, false);
1733
1800
 
1734
1801
 	/* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */
1735
-	rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true, is_unite);
1736
-	rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true, is_unite);
1737
-	rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false, is_unite);
1802
+	rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true);
1803
+	rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true);
1804
+	rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false);
1738
1805
 
1739
1806
 	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
1740
-		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2,
1741
-				  false, is_unite);
1742
-		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2,
1743
-				  false, is_unite);
1807
+		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false);
1808
+		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false);
1744
1809
 	} else {
1745
-		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line,
1746
-				  false, is_unite);
1747
-		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line,
1748
-				  false, is_unite);
1810
+		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false);
1811
+		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false);
1749
1812
 	}
1750
1813
 
1751
1814
 	/* interrupt mask */
..
..
@@ -1754,7 +1817,7 @@
1754
1817
 		irq_mask |= ISP2X_LSC_LUT_ERR;
1755
1818
 	if (dev->is_pre_on)
1756
1819
 		irq_mask |= CIF_ISP_FRAME_IN;
1757
-	rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true, is_unite);
1820
+	rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true);
1758
1821
 
1759
1822
 	if ((dev->isp_ver == ISP_V20 ||
1760
1823
 	     dev->isp_ver == ISP_V21) &&
..
..
@@ -1909,8 +1972,7 @@
1909
1972
 	if (dev->isp_ver == ISP_V32)
1910
1973
 		dpcl |= BIT(0);
1911
1974
 
1912
-	rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true,
1913
-			     dev->hw_dev->is_unite);
1975
+	rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
1914
1976
 	return ret;
1915
1977
 }
1916
1978
 
..
..
@@ -2007,9 +2069,9 @@
2007
2069
 
2008
2070
 	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2009
2071
 		 "%s refcnt:%d\n", __func__,
2010
-		 atomic_read(&dev->hw_dev->refcnt));
2072
+		 atomic_read(&hw->refcnt));
2011
2073
 
2012
-	if (atomic_read(&dev->hw_dev->refcnt) > 1)
2074
+	if (atomic_read(&hw->refcnt) > 1)
2013
2075
 		goto end;
2014
2076
 	/*
2015
2077
 	 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
..
..
@@ -2065,7 +2127,7 @@
2065
2127
 
2066
2128
 	val = readl(base + CIF_ISP_CTRL);
2067
2129
 	writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
2068
-	if (hw->is_unite)
2130
+	if (hw->unite == ISP_UNITE_TWO)
2069
2131
 		rkisp_next_write(dev, CIF_ISP_CTRL,
2070
2132
 				 val | CIF_ISP_CTRL_ISP_CFG_UPD, true);
2071
2133
 
..
..
@@ -2082,11 +2144,11 @@
2082
2144
 		safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL;
2083
2145
 		if (old_rate > safe_rate) {
2084
2146
 			rkisp_set_clk_rate(hw->clks[0], safe_rate);
2085
-			if (hw->is_unite)
2147
+			if (hw->unite == ISP_UNITE_TWO)
2086
2148
 				rkisp_set_clk_rate(hw->clks[5], safe_rate);
2087
2149
 			udelay(100);
2088
2150
 		}
2089
-		rkisp_soft_reset(dev->hw_dev, false);
2151
+		rkisp_soft_reset(hw, false);
2090
2152
 	}
2091
2153
 
2092
2154
 	if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
..
..
@@ -2097,18 +2159,20 @@
2097
2159
 		writel(0, base + CIF_ISP_CSI0_MASK3);
2098
2160
 	} else if (dev->isp_ver >= ISP_V20) {
2099
2161
 		writel(0, base + CSI2RX_CSI2_RESETN);
2100
-		if (hw->is_unite)
2162
+		if (hw->unite == ISP_UNITE_TWO)
2101
2163
 			rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
2102
2164
 	}
2103
2165
 
2104
2166
 	hw->is_dvfs = false;
2105
2167
 	hw->is_runing = false;
2106
-	dev->hw_dev->is_idle = true;
2107
-	dev->hw_dev->is_mi_update = false;
2168
+	hw->is_idle = true;
2169
+	hw->is_mi_update = false;
2170
+	hw->pre_dev_id = -1;
2108
2171
 end:
2109
2172
 	dev->irq_ends_mask = 0;
2110
2173
 	dev->hdr.op_mode = 0;
2111
2174
 	dev->sw_rd_cnt = 0;
2175
+	dev->stats_vdev.rdbk_drop = false;
2112
2176
 	rkisp_set_state(&dev->isp_state, ISP_STOP);
2113
2177
 
2114
2178
 	if (dev->isp_ver >= ISP_V20)
..
..
@@ -2154,12 +2218,9 @@
2154
2218
 			val = dev->isp_sdev.out_crop.height / 15;
2155
2219
 			val = dev->cap_dev.wait_line / val;
2156
2220
 			val = ISP3X_RAWAF_INELINE0(val) | ISP3X_RAWAF_INTLINE0_EN;
2157
-			rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE,
2158
-				val, false, dev->hw_dev->is_unite);
2159
-			rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0,
2160
-				ISP2X_3A_RAWAF, false, dev->hw_dev->is_unite);
2161
-			rkisp_unite_clear_bits(dev, CIF_ISP_IMSC,
2162
-				ISP2X_LSC_LUT_ERR, false, dev->hw_dev->is_unite);
2221
+			rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE, val, false);
2222
+			rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0, ISP2X_3A_RAWAF, false);
2223
+			rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, ISP2X_LSC_LUT_ERR, false);
2163
2224
 			dev->rawaf_irq_cnt = 0;
2164
2225
 		}
2165
2226
 	}
..
..
@@ -2187,12 +2248,11 @@
2187
2248
 		val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1);
2188
2249
 	if (atomic_read(&dev->hw_dev->refcnt) > 1)
2189
2250
 		is_direct = false;
2190
-	rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct, dev->hw_dev->is_unite);
2251
+	rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct);
2191
2252
 	rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
2192
2253
 
2193
2254
 	dev->isp_err_cnt = 0;
2194
2255
 	dev->isp_isr_cnt = 0;
2195
-	dev->isp_state = ISP_START | ISP_FRAME_END;
2196
2256
 	dev->irq_ends_mask |= ISP_FRAME_END;
2197
2257
 	dev->irq_ends = 0;
2198
2258
 
..
..
@@ -2668,14 +2728,16 @@
2668
2728
 				max_h = CIF_ISP_INPUT_H_MAX_V21;
2669
2729
 				break;
2670
2730
 			case ISP_V30:
2671
-				max_w = dev->hw_dev->is_unite ?
2731
+				max_w = dev->hw_dev->unite ?
2672
2732
 					CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
2673
-				max_h = dev->hw_dev->is_unite ?
2733
+				max_h = dev->hw_dev->unite ?
2674
2734
 					CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
2675
2735
 				break;
2676
2736
 			case ISP_V32:
2677
-				max_w = CIF_ISP_INPUT_W_MAX_V32;
2678
-				max_h = CIF_ISP_INPUT_H_MAX_V32;
2737
+				max_w = dev->hw_dev->unite ?
2738
+					CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
2739
+				max_h = dev->hw_dev->unite ?
2740
+					CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
2679
2741
 				break;
2680
2742
 			case ISP_V32_L:
2681
2743
 				max_w = CIF_ISP_INPUT_W_MAX_V32_L;
..
..
@@ -2901,6 +2963,7 @@
2901
2963
 	rkisp_config_cif(isp_dev);
2902
2964
 	rkisp_isp_start(isp_dev);
2903
2965
 	rkisp_global_update_mi(isp_dev);
2966
+	isp_dev->isp_state = ISP_START | ISP_FRAME_END;
2904
2967
 	rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
2905
2968
 	return 0;
2906
2969
 }
..
..
@@ -2936,7 +2999,7 @@
2936
2999
 	u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
2937
3000
 
2938
3001
 	rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
2939
-	if (dev->hw_dev->is_unite) {
3002
+	if (dev->hw_dev->unite == ISP_UNITE_TWO) {
2940
3003
 		u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
2941
3004
 
2942
3005
 		if (stream->memory)
..
..
@@ -3412,7 +3475,7 @@
3412
3475
 	if (dev->is_bigmode)
3413
3476
 		mode |= RKISP_ISP_BIGMODE;
3414
3477
 	info->mode = mode;
3415
-	if (dev->hw_dev->is_unite)
3478
+	if (dev->hw_dev->unite)
3416
3479
 		info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
3417
3480
 	else
3418
3481
 		info->act_width = in_crop->width;
..
..
@@ -3699,7 +3762,7 @@
3699
3762
 	struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
3700
3763
 	struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
3701
3764
 
3702
-	*in_fmt = rkisp_isp_input_formats[0];
3765
+	*in_fmt = rkisp_isp_input_formats[8];
3703
3766
 	in_frm->width = RKISP_DEFAULT_WIDTH;
3704
3767
 	in_frm->height = RKISP_DEFAULT_HEIGHT;
3705
3768
 	in_frm->code = in_fmt->mbus_code;
..
..
@@ -3805,8 +3868,52 @@
3805
3868
 })
3806
3869
 
3807
3870
 #ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
3871
+static void rkisp_save_tb_info(struct rkisp_device *isp_dev)
3872
+{
3873
+	struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3874
+	void *resmem_va = phys_to_virt(isp_dev->resmem_pa);
3875
+	struct rkisp_thunderboot_resmem_head *head = resmem_va;
3876
+	int size = 0, offset = 0;
3877
+	void *param = NULL;
3878
+
3879
+	switch (isp_dev->isp_ver) {
3880
+	case ISP_V32:
3881
+		size = sizeof(struct rkisp32_thunderboot_resmem_head);
3882
+		offset = size * isp_dev->dev_id;
3883
+		break;
3884
+	default:
3885
+		break;
3886
+	}
3887
+
3888
+	if (size && size < isp_dev->resmem_size) {
3889
+		dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
3890
+					size, DMA_FROM_DEVICE);
3891
+		params_vdev->is_first_cfg = true;
3892
+		if (isp_dev->isp_ver == ISP_V32) {
3893
+			struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
3894
+
3895
+			param = &tmp->cfg;
3896
+			head = &tmp->head;
3897
+			v4l2_info(&isp_dev->v4l2_dev,
3898
+				  "tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
3899
+				  tmp->cfg.module_en_update,
3900
+				  tmp->cfg.module_ens,
3901
+				  tmp->cfg.module_cfg_update);
3902
+		}
3903
+		if (param)
3904
+			params_vdev->ops->save_first_param(params_vdev, param);
3905
+	} else if (size > isp_dev->resmem_size) {
3906
+		v4l2_err(&isp_dev->v4l2_dev,
3907
+			 "resmem size:%zu no enough for head:%d\n",
3908
+			 isp_dev->resmem_size, size);
3909
+		head->complete = RKISP_TB_NG;
3910
+	}
3911
+	memcpy(&isp_dev->tb_head, head, sizeof(*head));
3912
+}
3913
+
3808
3914
 void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
3809
3915
 {
3916
+	struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3810
3917
 	struct rkisp_hw_dev *hw = isp_dev->hw_dev;
3811
3918
 	struct rkisp_thunderboot_resmem_head *head;
3812
3919
 	enum rkisp_tb_state tb_state;
..
..
@@ -3815,19 +3922,20 @@
3815
3922
 	if (!isp_dev->is_thunderboot)
3816
3923
 		return;
3817
3924
 
3925
+	if (isp_dev->isp_ver == ISP_V32 && params_vdev->is_first_cfg)
3926
+		goto end;
3927
+
3818
3928
 	resmem_va = phys_to_virt(isp_dev->resmem_pa);
3819
3929
 	head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
3820
3930
 	dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr,
3821
3931
 				sizeof(struct rkisp_thunderboot_resmem_head),
3822
3932
 				DMA_FROM_DEVICE);
3823
3933
 
3824
-	shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 200 * USEC_PER_MSEC);
3934
+	shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 400 * USEC_PER_MSEC);
3825
3935
 	if (head->complete != RKISP_TB_OK) {
3826
3936
 		v4l2_err(&isp_dev->v4l2_dev, "wait thunderboot over timeout\n");
3827
3937
 	} else {
3828
-		struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3829
-		void *param = NULL;
3830
-		u32 size = 0, offset = 0, timeout = 50;
3938
+		int i, timeout = 50;
3831
3939
 
3832
3940
 		/* wait for all isp dev to register */
3833
3941
 		if (head->camera_num > 1) {
..
..
@@ -3837,42 +3945,18 @@
3837
3945
 					break;
3838
3946
 				usleep_range(200, 210);
3839
3947
 			}
3840
-		}
3841
-
3842
-		switch (isp_dev->isp_ver) {
3843
-		case ISP_V32:
3844
-			size = sizeof(struct rkisp32_thunderboot_resmem_head);
3845
-			offset = size * isp_dev->dev_id;
3846
-			break;
3847
-		default:
3848
-			break;
3849
-		}
3850
-
3851
-		if (size && size < isp_dev->resmem_size) {
3852
-			dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
3853
-						size, DMA_FROM_DEVICE);
3854
-			params_vdev->is_first_cfg = true;
3855
-			if (isp_dev->isp_ver == ISP_V32) {
3856
-				struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
3857
-
3858
-				param = &tmp->cfg;
3859
-				head = &tmp->head;
3860
-				v4l2_info(&isp_dev->v4l2_dev,
3861
-					  "tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
3862
-					  tmp->cfg.module_en_update,
3863
-					  tmp->cfg.module_ens,
3864
-					  tmp->cfg.module_cfg_update);
3948
+			if (head->camera_num > hw->dev_num) {
3949
+				v4l2_err(&isp_dev->v4l2_dev,
3950
+					 "thunderboot invalid camera num:%d, dev num:%d\n",
3951
+					 head->camera_num, hw->dev_num);
3952
+				goto end;
3865
3953
 			}
3866
-			if (param)
3867
-				params_vdev->ops->save_first_param(params_vdev, param);
3868
-		} else if (size > isp_dev->resmem_size) {
3869
-			v4l2_err(&isp_dev->v4l2_dev,
3870
-				 "resmem size:%zu no enough for head:%d\n",
3871
-				 isp_dev->resmem_size, size);
3872
-			head->complete = RKISP_TB_NG;
3873
3954
 		}
3955
+		for (i = 0; i < head->camera_num; i++)
3956
+			rkisp_save_tb_info(hw->isp[i]);
3874
3957
 	}
3875
-	memcpy(&isp_dev->tb_head, head, sizeof(*head));
3958
+end:
3959
+	head = &isp_dev->tb_head;
3876
3960
 	v4l2_info(&isp_dev->v4l2_dev,
3877
3961
 		  "thunderboot info: %d, %d, %d, %d, %d, %d | %d %d\n",
3878
3962
 		  head->enable,
..
..
@@ -4005,7 +4089,7 @@
4005
4089
 		   struct rkisp_device *dev)
4006
4090
 {
4007
4091
 	struct rkisp_hw_dev *hw = dev->hw_dev;
4008
-	void __iomem *base = !hw->is_unite ?
4092
+	void __iomem *base = hw->unite != ISP_UNITE_TWO ?
4009
4093
 		hw->base_addr : hw->base_next_addr;
4010
4094
 	unsigned int isp_mis_tmp = 0;
4011
4095
 	unsigned int isp_err = 0;
..
..
@@ -4026,7 +4110,7 @@
4026
4110
 	if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0)
4027
4111
 		writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL);
4028
4112
 
4029
-	if (hw->is_unite) {
4113
+	if (hw->unite == ISP_UNITE_TWO) {
4030
4114
 		u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true);
4031
4115
 
4032
4116
 		if (val) {
..
..
@@ -4057,9 +4141,14 @@
4057
4141
 		}
4058
4142
 
4059
4143
 		if (IS_HDR_RDBK(dev->hdr.op_mode)) {
4060
-			/* read 3d lut at isp readback */
4061
-			if (!dev->hw_dev->is_single)
4062
-				rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
4144
+			/* disabled frame end to read 3dlut for multi sensor
4145
+			 * 3dlut will update at isp readback
4146
+			 */
4147
+			if (!dev->hw_dev->is_single) {
4148
+				writel(0, hw->base_addr + ISP_3DLUT_UPDATE);
4149
+				if (hw->unite == ISP_UNITE_TWO)
4150
+					writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE);
4151
+			}
4063
4152
 			rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
4064
4153
 			goto vs_skip;
4065
4154
 		}