~hc/RK356X_SDK_RELEASE.git

..	..	@@ -9,13 +9,14 @@
9	9	#include <linux/mfd/syscon.h>
10	10	#include <linux/module.h>
11	11	#include <linux/of.h>
	12	+#include <linux/of_address.h>
12	13	#include <linux/of_graph.h>
13	14	#include <linux/of_platform.h>
14	15	#include <linux/of_reserved_mem.h>
15	16	#include <linux/pinctrl/consumer.h>
16	17	#include <linux/pm_runtime.h>
17	18	#include <linux/reset.h>
18		-#include <media/videobuf2-dma-contig.h>
	19	+#include <media/videobuf2-cma-sg.h>
19	20	#include <media/videobuf2-dma-sg.h>
20	21	#include <soc/rockchip/rockchip_iommu.h>
21	22
..	..	@@ -72,6 +73,38 @@
72	73	ISP_RAWHIST_BIG3_BASE, ISP_YUVAE_CTRL, ISP_RAWAF_CTRL,
73	74	ISP21_RAWAWB_CTRL,
74	75	};
	76	+ u32 v30_reg[] = {
	77	+ ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
	78	+ ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
	79	+ ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
	80	+ ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
	81	+ ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
	82	+ ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
	83	+ ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
	84	+ ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
	85	+ ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
	86	+ ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
	87	+ ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
	88	+ ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
	89	+ ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
	90	+ };
	91	+ u32 v32_reg[] = {
	92	+ ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
	93	+ ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
	94	+ ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
	95	+ ISP32_BP_RESIZE_BASE, ISP3X_MI_BP_WR_CTRL, ISP32_MI_MPDS_WR_CTRL,
	96	+ ISP32_MI_BPDS_WR_CTRL, ISP32_MI_WR_WRAP_CTRL,
	97	+ ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
	98	+ ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
	99	+ ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
	100	+ ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
	101	+ ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
	102	+ ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
	103	+ ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
	104	+ ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
	105	+ ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
	106	+ ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
	107	+ };
75	108	u32 i, flag, reg, size;
76	109
77	110	switch (dev->isp_ver) {
..	..	@@ -83,6 +116,15 @@
83	116	reg = v21_reg;
84	117	size = ARRAY_SIZE(v21_reg);
85	118	break;
	119	+ case ISP_V30:
	120	+ reg = v30_reg;
	121	+ size = ARRAY_SIZE(v30_reg);
	122	+ break;
	123	+ case ISP_V32:
	124	+ case ISP_V32_L:
	125	+ reg = v32_reg;
	126	+ size = ARRAY_SIZE(v32_reg);
	127	+ break;
86	128	default:
87	129	return;
88	130	}
..	..	@@ -90,6 +132,10 @@
90	132	for (i = 0; i < size; i++) {
91	133	flag = dev->sw_base_addr + reg[i] + RKISP_ISP_SW_REG_SIZE;
92	134	*flag = SW_REG_CACHE;
	135	+ if (dev->hw_dev->unite) {
	136	+ flag += RKISP_ISP_SW_MAX_SIZE / 4;
	137	+ *flag = SW_REG_CACHE;
	138	+ }
93	139	}
94	140	}
95	141
..	..	@@ -98,39 +144,55 @@
98	144	struct device *dev = ctx;
99	145	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
100	146	struct rkisp_device *isp = hw_dev->isp[hw_dev->mipi_dev_id];
	147	+ void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
	148	+ hw_dev->base_addr : hw_dev->base_next_addr;
	149	+ ktime_t t = 0;
	150	+ s64 us;
101	151
102	152	if (hw_dev->is_thunderboot)
103	153	return IRQ_HANDLED;
104	154
	155	+ if (rkisp_irq_dbg)
	156	+ t = ktime_get();
	157	+
105	158	if (hw_dev->isp_ver == ISP_V13 \|\| hw_dev->isp_ver == ISP_V12) {
106	159	u32 err1, err2, err3;
107	160
108		- err1 = readl(hw_dev->base_addr + CIF_ISP_CSI0_ERR1);
109		- err2 = readl(hw_dev->base_addr + CIF_ISP_CSI0_ERR2);
110		- err3 = readl(hw_dev->base_addr + CIF_ISP_CSI0_ERR3);
	161	+ err1 = readl(base + CIF_ISP_CSI0_ERR1);
	162	+ err2 = readl(base + CIF_ISP_CSI0_ERR2);
	163	+ err3 = readl(base + CIF_ISP_CSI0_ERR3);
111	164
112	165	if (err1 \|\| err2 \|\| err3)
113	166	rkisp_mipi_v13_isr(err1, err2, err3, isp);
114		- } else if (hw_dev->isp_ver == ISP_V20 \|\| hw_dev->isp_ver == ISP_V21) {
	167	+ } else if (hw_dev->isp_ver >= ISP_V20) {
115	168	u32 phy, packet, overflow, state;
116	169
117		- state = readl(hw_dev->base_addr + CSI2RX_ERR_STAT);
118		- phy = readl(hw_dev->base_addr + CSI2RX_ERR_PHY);
119		- packet = readl(hw_dev->base_addr + CSI2RX_ERR_PACKET);
120		- overflow = readl(hw_dev->base_addr + CSI2RX_ERR_OVERFLOW);
	170	+ state = readl(base + CSI2RX_ERR_STAT);
	171	+ phy = readl(base + CSI2RX_ERR_PHY);
	172	+ packet = readl(base + CSI2RX_ERR_PACKET);
	173	+ overflow = readl(base + CSI2RX_ERR_OVERFLOW);
121	174	if (phy \| packet \| overflow \| state) {
122	175	if (hw_dev->isp_ver == ISP_V20)
123	176	rkisp_mipi_v20_isr(phy, packet, overflow, state, isp);
124		- else
	177	+ else if (hw_dev->isp_ver == ISP_V21)
125	178	rkisp_mipi_v21_isr(phy, packet, overflow, state, isp);
	179	+ else if (hw_dev->isp_ver == ISP_V30)
	180	+ rkisp_mipi_v30_isr(phy, packet, overflow, state, isp);
	181	+ else
	182	+ rkisp_mipi_v32_isr(phy, packet, overflow, state, isp);
126	183	}
127	184	} else {
128		- u32 mis_val = readl(hw_dev->base_addr + CIF_MIPI_MIS);
	185	+ u32 mis_val = readl(base + CIF_MIPI_MIS);
129	186
130	187	if (mis_val)
131	188	rkisp_mipi_isr(mis_val, isp);
132	189	}
133	190
	191	+ if (rkisp_irq_dbg) {
	192	+ us = ktime_us_delta(ktime_get(), t);
	193	+ v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
	194	+ "%s %lldus\n", __func__, us);
	195	+ }
134	196	return IRQ_HANDLED;
135	197	}
136	198
..	..	@@ -139,13 +201,20 @@
139	201	struct device *dev = ctx;
140	202	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
141	203	struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
	204	+ void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
	205	+ hw_dev->base_addr : hw_dev->base_next_addr;
142	206	u32 mis_val, tx_isr = MI_RAW0_WR_FRAME \| MI_RAW1_WR_FRAME \|
143	207	MI_RAW2_WR_FRAME \| MI_RAW3_WR_FRAME;
	208	+ ktime_t t = 0;
	209	+ s64 us;
144	210
145	211	if (hw_dev->is_thunderboot)
146	212	return IRQ_HANDLED;
147	213
148		- mis_val = readl(hw_dev->base_addr + CIF_MI_MIS);
	214	+ if (rkisp_irq_dbg)
	215	+ t = ktime_get();
	216	+
	217	+ mis_val = readl(base + CIF_MI_MIS);
149	218	if (mis_val) {
150	219	if (mis_val & ~tx_isr)
151	220	rkisp_mi_isr(mis_val & ~tx_isr, isp);
..	..	@@ -153,6 +222,12 @@
153	222	isp = hw_dev->isp[hw_dev->mipi_dev_id];
154	223	rkisp_mi_isr(mis_val & tx_isr, isp);
155	224	}
	225	+ }
	226	+
	227	+ if (rkisp_irq_dbg) {
	228	+ us = ktime_us_delta(ktime_get(), t);
	229	+ v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
	230	+ "%s:0x%x %lldus\n", __func__, mis_val, us);
156	231	}
157	232	return IRQ_HANDLED;
158	233	}
..	..	@@ -162,17 +237,29 @@
162	237	struct device *dev = ctx;
163	238	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
164	239	struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
	240	+ void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
	241	+ hw_dev->base_addr : hw_dev->base_next_addr;
165	242	unsigned int mis_val, mis_3a = 0;
	243	+ ktime_t t = 0;
	244	+ s64 us;
166	245
167	246	if (hw_dev->is_thunderboot)
168	247	return IRQ_HANDLED;
169	248
170		- mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS);
171		- if (hw_dev->isp_ver == ISP_V20 \|\| hw_dev->isp_ver == ISP_V21)
172		- mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS);
	249	+ if (rkisp_irq_dbg)
	250	+ t = ktime_get();
	251	+
	252	+ mis_val = readl(base + CIF_ISP_MIS);
	253	+ if (hw_dev->isp_ver >= ISP_V20)
	254	+ mis_3a = readl(base + ISP_ISP3A_MIS);
173	255	if (mis_val \|\| mis_3a)
174	256	rkisp_isp_isr(mis_val, mis_3a, isp);
175	257
	258	+ if (rkisp_irq_dbg) {
	259	+ us = ktime_us_delta(ktime_get(), t);
	260	+ v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
	261	+ "%s:0x%x %lldus\n", __func__, mis_val, us);
	262	+ }
176	263	return IRQ_HANDLED;
177	264	}
178	265
..	..	@@ -184,7 +271,7 @@
184	271	unsigned int mis_val, mis_3a = 0;
185	272
186	273	mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS);
187		- if (hw_dev->isp_ver == ISP_V20 \|\| hw_dev->isp_ver == ISP_V21)
	274	+ if (hw_dev->isp_ver >= ISP_V20)
188	275	mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS);
189	276	if (mis_val \|\| mis_3a)
190	277	rkisp_isp_isr(mis_val, mis_3a, isp);
..	..	@@ -261,42 +348,10 @@
261	348	return 0;
262	349	}
263	350
264		-static const char * const rk1808_isp_clks[] = {
265		- "clk_isp",
	351	+static const char * const rk3562_isp_clks[] = {
	352	+ "clk_isp_core",
266	353	"aclk_isp",
267	354	"hclk_isp",
268		- "pclk_isp",
269		-};
270		-
271		-static const char * const rk3288_isp_clks[] = {
272		- "clk_isp",
273		- "aclk_isp",
274		- "hclk_isp",
275		- "pclk_isp_in",
276		- "sclk_isp_jpe",
277		-};
278		-
279		-static const char * const rk3326_isp_clks[] = {
280		- "clk_isp",
281		- "aclk_isp",
282		- "hclk_isp",
283		- "pclk_isp",
284		-};
285		-
286		-static const char * const rk3368_isp_clks[] = {
287		- "clk_isp",
288		- "aclk_isp",
289		- "hclk_isp",
290		- "pclk_isp",
291		-};
292		-
293		-static const char * const rk3399_isp_clks[] = {
294		- "clk_isp",
295		- "aclk_isp",
296		- "hclk_isp",
297		- "aclk_isp_wrap",
298		- "hclk_isp_wrap",
299		- "pclk_isp_wrap"
300	355	};
301	356
302	357	static const char * const rk3568_isp_clks[] = {
..	..	@@ -305,35 +360,54 @@
305	360	"hclk_isp",
306	361	};
307	362
	363	+static const char * const rk3588_isp_clks[] = {
	364	+ "clk_isp_core",
	365	+ "aclk_isp",
	366	+ "hclk_isp",
	367	+ "clk_isp_core_marvin",
	368	+ "clk_isp_core_vicap",
	369	+};
	370	+
	371	+static const char * const rk3588_isp_unite_clks[] = {
	372	+ "clk_isp_core0",
	373	+ "aclk_isp0",
	374	+ "hclk_isp0",
	375	+ "clk_isp_core_marvin0",
	376	+ "clk_isp_core_vicap0",
	377	+ "clk_isp_core1",
	378	+ "aclk_isp1",
	379	+ "hclk_isp1",
	380	+ "clk_isp_core_marvin1",
	381	+ "clk_isp_core_vicap1",
	382	+};
	383	+
	384	+static const char * const rv1106_isp_clks[] = {
	385	+ "clk_isp_core",
	386	+ "aclk_isp",
	387	+ "hclk_isp",
	388	+ "clk_isp_core_vicap",
	389	+};
	390	+
308	391	static const char * const rv1126_isp_clks[] = {
309	392	"clk_isp",
310	393	"aclk_isp",
311	394	"hclk_isp",
312	395	};
313	396
314		-/* isp clock adjustment table (MHz) */
315		-static const struct isp_clk_info rk1808_isp_clk_rate[] = {
316		- {300, }, {400, }, {500, }, {600, }
317		-};
318		-
319		-/* isp clock adjustment table (MHz) */
320		-static const struct isp_clk_info rk3288_isp_clk_rate[] = {
321		- {150, }, {384, }, {500, }, {594, }
322		-};
323		-
324		-/* isp clock adjustment table (MHz) */
325		-static const struct isp_clk_info rk3326_isp_clk_rate[] = {
326		- {300, }, {347, }, {400, }, {520, }, {600, }
327		-};
328		-
329		-/* isp clock adjustment table (MHz) */
330		-static const struct isp_clk_info rk3368_isp_clk_rate[] = {
331		- {300, }, {400, }, {600, }
332		-};
333		-
334		-/* isp clock adjustment table (MHz) */
335		-static const struct isp_clk_info rk3399_isp_clk_rate[] = {
336		- {300, }, {400, }, {600, }
	397	+static const struct isp_clk_info rk3562_isp_clk_rate[] = {
	398	+ {
	399	+ .clk_rate = 300,
	400	+ .refer_data = 1920, //width
	401	+ }, {
	402	+ .clk_rate = 400,
	403	+ .refer_data = 2688,
	404	+ }, {
	405	+ .clk_rate = 500,
	406	+ .refer_data = 3072,
	407	+ }, {
	408	+ .clk_rate = 600,
	409	+ .refer_data = 3840,
	410	+ }
337	411	};
338	412
339	413	static const struct isp_clk_info rk3568_isp_clk_rate[] = {
..	..	@@ -348,6 +422,41 @@
348	422	.refer_data = 3072,
349	423	}, {
350	424	.clk_rate = 600,
	425	+ .refer_data = 3840,
	426	+ }
	427	+};
	428	+
	429	+static const struct isp_clk_info rk3588_isp_clk_rate[] = {
	430	+ {
	431	+ .clk_rate = 300,
	432	+ .refer_data = 1920, //width
	433	+ }, {
	434	+ .clk_rate = 400,
	435	+ .refer_data = 2688,
	436	+ }, {
	437	+ .clk_rate = 500,
	438	+ .refer_data = 3072,
	439	+ }, {
	440	+ .clk_rate = 600,
	441	+ .refer_data = 3840,
	442	+ }, {
	443	+ .clk_rate = 702,
	444	+ .refer_data = 4672,
	445	+ }
	446	+};
	447	+
	448	+static const struct isp_clk_info rv1106_isp_clk_rate[] = {
	449	+ {
	450	+ .clk_rate = 200,
	451	+ .refer_data = 1920, //width
	452	+ }, {
	453	+ .clk_rate = 200,
	454	+ .refer_data = 2688,
	455	+ }, {
	456	+ .clk_rate = 350,
	457	+ .refer_data = 3072,
	458	+ }, {
	459	+ .clk_rate = 440,
351	460	.refer_data = 3840,
352	461	}
353	462	};
..	..	@@ -371,31 +480,25 @@
371	480	}
372	481	};
373	482
374		-static struct isp_irqs_data rk1808_isp_irqs[] = {
	483	+static struct isp_irqs_data rk3562_isp_irqs[] = {
375	484	{"isp_irq", isp_irq_hdl},
376	485	{"mi_irq", mi_irq_hdl},
377	486	{"mipi_irq", mipi_irq_hdl}
378		-};
379		-
380		-static struct isp_irqs_data rk3288_isp_irqs[] = {
381		- {"isp_irq", irq_handler}
382		-};
383		-
384		-static struct isp_irqs_data rk3326_isp_irqs[] = {
385		- {"isp_irq", isp_irq_hdl},
386		- {"mi_irq", mi_irq_hdl},
387		- {"mipi_irq", mipi_irq_hdl}
388		-};
389		-
390		-static struct isp_irqs_data rk3368_isp_irqs[] = {
391		- {"isp_irq", irq_handler}
392		-};
393		-
394		-static struct isp_irqs_data rk3399_isp_irqs[] = {
395		- {"isp_irq", irq_handler}
396	487	};
397	488
398	489	static struct isp_irqs_data rk3568_isp_irqs[] = {
	490	+ {"isp_irq", isp_irq_hdl},
	491	+ {"mi_irq", mi_irq_hdl},
	492	+ {"mipi_irq", mipi_irq_hdl}
	493	+};
	494	+
	495	+static struct isp_irqs_data rk3588_isp_irqs[] = {
	496	+ {"isp_irq", isp_irq_hdl},
	497	+ {"mi_irq", mi_irq_hdl},
	498	+ {"mipi_irq", mipi_irq_hdl}
	499	+};
	500	+
	501	+static struct isp_irqs_data rv1106_isp_irqs[] = {
399	502	{"isp_irq", isp_irq_hdl},
400	503	{"mi_irq", mi_irq_hdl},
401	504	{"mipi_irq", mipi_irq_hdl}
..	..	@@ -407,6 +510,17 @@
407	510	{"mipi_irq", mipi_irq_hdl}
408	511	};
409	512
	513	+static const struct isp_match_data rv1106_isp_match_data = {
	514	+ .clks = rv1106_isp_clks,
	515	+ .num_clks = ARRAY_SIZE(rv1106_isp_clks),
	516	+ .isp_ver = ISP_V32,
	517	+ .clk_rate_tbl = rv1106_isp_clk_rate,
	518	+ .num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate),
	519	+ .irqs = rv1106_isp_irqs,
	520	+ .num_irqs = ARRAY_SIZE(rv1106_isp_irqs),
	521	+ .unite = false,
	522	+};
	523	+
410	524	static const struct isp_match_data rv1126_isp_match_data = {
411	525	.clks = rv1126_isp_clks,
412	526	.num_clks = ARRAY_SIZE(rv1126_isp_clks),
..	..	@@ -414,57 +528,19 @@
414	528	.clk_rate_tbl = rv1126_isp_clk_rate,
415	529	.num_clk_rate_tbl = ARRAY_SIZE(rv1126_isp_clk_rate),
416	530	.irqs = rv1126_isp_irqs,
417		- .num_irqs = ARRAY_SIZE(rv1126_isp_irqs)
	531	+ .num_irqs = ARRAY_SIZE(rv1126_isp_irqs),
	532	+ .unite = false,
418	533	};
419	534
420		-static const struct isp_match_data rk1808_isp_match_data = {
421		- .clks = rk1808_isp_clks,
422		- .num_clks = ARRAY_SIZE(rk1808_isp_clks),
423		- .isp_ver = ISP_V13,
424		- .clk_rate_tbl = rk1808_isp_clk_rate,
425		- .num_clk_rate_tbl = ARRAY_SIZE(rk1808_isp_clk_rate),
426		- .irqs = rk1808_isp_irqs,
427		- .num_irqs = ARRAY_SIZE(rk1808_isp_irqs)
428		-};
429		-
430		-static const struct isp_match_data rk3288_isp_match_data = {
431		- .clks = rk3288_isp_clks,
432		- .num_clks = ARRAY_SIZE(rk3288_isp_clks),
433		- .isp_ver = ISP_V10,
434		- .clk_rate_tbl = rk3288_isp_clk_rate,
435		- .num_clk_rate_tbl = ARRAY_SIZE(rk3288_isp_clk_rate),
436		- .irqs = rk3288_isp_irqs,
437		- .num_irqs = ARRAY_SIZE(rk3288_isp_irqs)
438		-};
439		-
440		-static const struct isp_match_data rk3326_isp_match_data = {
441		- .clks = rk3326_isp_clks,
442		- .num_clks = ARRAY_SIZE(rk3326_isp_clks),
443		- .isp_ver = ISP_V12,
444		- .clk_rate_tbl = rk3326_isp_clk_rate,
445		- .num_clk_rate_tbl = ARRAY_SIZE(rk3326_isp_clk_rate),
446		- .irqs = rk3326_isp_irqs,
447		- .num_irqs = ARRAY_SIZE(rk3326_isp_irqs)
448		-};
449		-
450		-static const struct isp_match_data rk3368_isp_match_data = {
451		- .clks = rk3368_isp_clks,
452		- .num_clks = ARRAY_SIZE(rk3368_isp_clks),
453		- .isp_ver = ISP_V10_1,
454		- .clk_rate_tbl = rk3368_isp_clk_rate,
455		- .num_clk_rate_tbl = ARRAY_SIZE(rk3368_isp_clk_rate),
456		- .irqs = rk3368_isp_irqs,
457		- .num_irqs = ARRAY_SIZE(rk3368_isp_irqs)
458		-};
459		-
460		-static const struct isp_match_data rk3399_isp_match_data = {
461		- .clks = rk3399_isp_clks,
462		- .num_clks = ARRAY_SIZE(rk3399_isp_clks),
463		- .isp_ver = ISP_V10,
464		- .clk_rate_tbl = rk3399_isp_clk_rate,
465		- .num_clk_rate_tbl = ARRAY_SIZE(rk3399_isp_clk_rate),
466		- .irqs = rk3399_isp_irqs,
467		- .num_irqs = ARRAY_SIZE(rk3399_isp_irqs)
	535	+static const struct isp_match_data rk3562_isp_match_data = {
	536	+ .clks = rk3562_isp_clks,
	537	+ .num_clks = ARRAY_SIZE(rk3562_isp_clks),
	538	+ .isp_ver = ISP_V32_L,
	539	+ .clk_rate_tbl = rk3562_isp_clk_rate,
	540	+ .num_clk_rate_tbl = ARRAY_SIZE(rk3562_isp_clk_rate),
	541	+ .irqs = rk3562_isp_irqs,
	542	+ .num_irqs = ARRAY_SIZE(rk3562_isp_irqs),
	543	+ .unite = false,
468	544	};
469	545
470	546	static const struct isp_match_data rk3568_isp_match_data = {
..	..	@@ -474,32 +550,66 @@
474	550	.clk_rate_tbl = rk3568_isp_clk_rate,
475	551	.num_clk_rate_tbl = ARRAY_SIZE(rk3568_isp_clk_rate),
476	552	.irqs = rk3568_isp_irqs,
477		- .num_irqs = ARRAY_SIZE(rk3568_isp_irqs)
	553	+ .num_irqs = ARRAY_SIZE(rk3568_isp_irqs),
	554	+ .unite = false,
	555	+};
	556	+
	557	+static const struct isp_match_data rk3588_isp_match_data = {
	558	+ .clks = rk3588_isp_clks,
	559	+ .num_clks = ARRAY_SIZE(rk3588_isp_clks),
	560	+ .isp_ver = ISP_V30,
	561	+ .clk_rate_tbl = rk3588_isp_clk_rate,
	562	+ .num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
	563	+ .irqs = rk3588_isp_irqs,
	564	+ .num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
	565	+ .unite = false,
	566	+};
	567	+
	568	+static const struct isp_match_data rk3588_isp_unite_match_data = {
	569	+ .clks = rk3588_isp_unite_clks,
	570	+ .num_clks = ARRAY_SIZE(rk3588_isp_unite_clks),
	571	+ .isp_ver = ISP_V30,
	572	+ .clk_rate_tbl = rk3588_isp_clk_rate,
	573	+ .num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
	574	+ .irqs = rk3588_isp_irqs,
	575	+ .num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
	576	+ .unite = true,
478	577	};
479	578
480	579	static const struct of_device_id rkisp_hw_of_match[] = {
	580	+#ifdef CONFIG_CPU_RK3562
481	581	{
482		- .compatible = "rockchip,rk1808-rkisp1",
483		- .data = &rk1808_isp_match_data,
484		- }, {
485		- .compatible = "rockchip,rk3288-rkisp1",
486		- .data = &rk3288_isp_match_data,
487		- }, {
488		- .compatible = "rockchip,rk3326-rkisp1",
489		- .data = &rk3326_isp_match_data,
490		- }, {
491		- .compatible = "rockchip,rk3368-rkisp1",
492		- .data = &rk3368_isp_match_data,
493		- }, {
494		- .compatible = "rockchip,rk3399-rkisp1",
495		- .data = &rk3399_isp_match_data,
496		- }, {
	582	+ .compatible = "rockchip,rk3562-rkisp",
	583	+ .data = &rk3562_isp_match_data,
	584	+ },
	585	+#endif
	586	+#ifdef CONFIG_CPU_RK3568
	587	+ {
497	588	.compatible = "rockchip,rk3568-rkisp",
498	589	.data = &rk3568_isp_match_data,
	590	+ },
	591	+#endif
	592	+#ifdef CONFIG_CPU_RK3588
	593	+ {
	594	+ .compatible = "rockchip,rk3588-rkisp",
	595	+ .data = &rk3588_isp_match_data,
499	596	}, {
	597	+ .compatible = "rockchip,rk3588-rkisp-unite",
	598	+ .data = &rk3588_isp_unite_match_data,
	599	+ },
	600	+#endif
	601	+#ifdef CONFIG_CPU_RV1106
	602	+ {
	603	+ .compatible = "rockchip,rv1106-rkisp",
	604	+ .data = &rv1106_isp_match_data,
	605	+ },
	606	+#endif
	607	+#ifdef CONFIG_CPU_RV1126
	608	+ {
500	609	.compatible = "rockchip,rv1126-rkisp",
501	610	.data = &rv1126_isp_match_data,
502	611	},
	612	+#endif
503	613	{},
504	614	};
505	615
..	..	@@ -524,12 +634,23 @@
524	634	void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
525	635	{
526	636	void __iomem *base = dev->base_addr;
	637	+ u32 val, iccl0, iccl1, clk_ctrl0, clk_ctrl1;
	638	+
	639	+ /* record clk config and recover */
	640	+ iccl0 = readl(base + CIF_ICCL);
	641	+ clk_ctrl0 = readl(base + CTRL_VI_ISP_CLK_CTRL);
	642	+ if (dev->unite == ISP_UNITE_TWO) {
	643	+ iccl1 = readl(dev->base_next_addr + CIF_ICCL);
	644	+ clk_ctrl1 = readl(dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
	645	+ }
527	646
528	647	if (is_secure) {
529	648	/* if isp working, cru reset isn't secure.
530	649	* isp soft reset first to protect isp reset.
531	650	*/
532	651	writel(0xffff, base + CIF_IRCL);
	652	+ if (dev->unite == ISP_UNITE_TWO)
	653	+ writel(0xffff, dev->base_next_addr + CIF_IRCL);
533	654	udelay(10);
534	655	}
535	656
..	..	@@ -543,13 +664,47 @@
543	664	/* reset for Dehaze */
544	665	if (dev->isp_ver == ISP_V20)
545	666	writel(CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601, base + CIF_ISP_CTRL);
546		- writel(0xffff, base + CIF_IRCL);
	667	+ val = 0xffff;
	668	+ if (dev->isp_ver == ISP_V32) {
	669	+ val = 0x3fffffff;
	670	+ rv1106_sdmmc_get_lock();
	671	+ }
	672	+ writel(val, base + CIF_IRCL);
	673	+ if (dev->isp_ver == ISP_V32)
	674	+ rv1106_sdmmc_put_lock();
	675	+ if (dev->unite == ISP_UNITE_TWO)
	676	+ writel(0xffff, dev->base_next_addr + CIF_IRCL);
547	677	udelay(10);
548	678
549	679	/* refresh iommu after reset */
550	680	if (dev->is_mmu) {
551	681	rockchip_iommu_disable(dev->dev);
552	682	rockchip_iommu_enable(dev->dev);
	683	+ }
	684	+
	685	+ writel(iccl0, base + CIF_ICCL);
	686	+ writel(clk_ctrl0, base + CTRL_VI_ISP_CLK_CTRL);
	687	+ if (dev->unite == ISP_UNITE_TWO) {
	688	+ writel(iccl1, dev->base_next_addr + CIF_ICCL);
	689	+ writel(clk_ctrl1, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
	690	+ }
	691	+
	692	+ /* default config */
	693	+ if (dev->isp_ver == ISP_V12 \|\| dev->isp_ver == ISP_V13) {
	694	+ /* disable csi_rx interrupt */
	695	+ writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
	696	+ writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
	697	+ writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
	698	+ writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
	699	+ } else if (dev->isp_ver == ISP_V32) {
	700	+ /* disable down samplling default */
	701	+ writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_MPDS_WR_CTRL);
	702	+ writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_BPDS_WR_CTRL);
	703	+
	704	+ writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
	705	+ writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL);
	706	+ } else if (dev->isp_ver == ISP_V32_L) {
	707	+ writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
553	708	}
554	709	}
555	710
..	..	@@ -560,10 +715,18 @@
560	715	CIF_ICCL_SRSZ_CLK \| CIF_ICCL_JPEG_CLK \| CIF_ICCL_MI_CLK \|
561	716	CIF_ICCL_IE_CLK \| CIF_ICCL_MIPI_CLK \| CIF_ICCL_DCROP_CLK;
562	717
563		- if (dev->isp_ver == ISP_V20 && on)
	718	+ if ((dev->isp_ver == ISP_V20 \|\| dev->isp_ver >= ISP_V30) && on)
564	719	val \|= ICCL_MPFBC_CLK;
565		-
	720	+ if (dev->isp_ver >= ISP_V32) {
	721	+ val \|= ISP32_BRSZ_CLK_ENABLE \| BIT(0) \| BIT(16);
	722	+ if (dev->isp_ver == ISP_V32)
	723	+ rv1106_sdmmc_get_lock();
	724	+ }
566	725	writel(val, dev->base_addr + CIF_ICCL);
	726	+ if (dev->isp_ver == ISP_V32)
	727	+ rv1106_sdmmc_put_lock();
	728	+ if (dev->unite == ISP_UNITE_TWO)
	729	+ writel(val, dev->base_next_addr + CIF_ICCL);
567	730
568	731	if (dev->isp_ver == ISP_V12 \|\| dev->isp_ver == ISP_V13) {
569	732	val = !on ? 0 :
..	..	@@ -573,7 +736,7 @@
573	736	CIF_CLK_CTRL_CP \| CIF_CLK_CTRL_IE;
574	737
575	738	writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12);
576		- } else if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21) {
	739	+ } else if (dev->isp_ver >= ISP_V20) {
577	740	val = !on ? 0 :
578	741	CLK_CTRL_MI_LDC \| CLK_CTRL_MI_MP \|
579	742	CLK_CTRL_MI_JPEG \| CLK_CTRL_MI_DP \|
..	..	@@ -582,9 +745,18 @@
582	745	CLK_CTRL_MI_READ \| CLK_CTRL_MI_RAWRD \|
583	746	CLK_CTRL_ISP_RAW;
584	747
585		- if (dev->isp_ver == ISP_V20 && on)
	748	+ if (dev->isp_ver >= ISP_V30)
	749	+ val = 0;
	750	+
	751	+ if ((dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V30) && on)
586	752	val \|= CLK_CTRL_ISP_3A;
	753	+ if (dev->isp_ver == ISP_V32)
	754	+ rv1106_sdmmc_get_lock();
587	755	writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL);
	756	+ if (dev->isp_ver == ISP_V32)
	757	+ rv1106_sdmmc_put_lock();
	758	+ if (dev->unite == ISP_UNITE_TWO)
	759	+ writel(val, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
588	760	}
589	761	}
590	762
..	..	@@ -607,6 +779,7 @@
607	779	static int enable_sys_clk(struct rkisp_hw_dev *dev)
608	780	{
609	781	int i, ret = -EINVAL;
	782	+ unsigned long rate;
610	783
611	784	for (i = 0; i < dev->num_clks; i++) {
612	785	if (!IS_ERR(dev->clks[i])) {
..	..	@@ -616,25 +789,58 @@
616	789	}
617	790	}
618	791
619		- rkisp_set_clk_rate(dev->clks[0],
620		- dev->clk_rate_tbl[0].clk_rate * 1000000UL);
	792	+ if (!dev->is_assigned_clk) {
	793	+ rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL;
	794	+ rkisp_set_clk_rate(dev->clks[0], rate);
	795	+ if (dev->unite == ISP_UNITE_TWO)
	796	+ rkisp_set_clk_rate(dev->clks[5], rate);
	797	+ }
621	798	rkisp_soft_reset(dev, false);
622	799	isp_config_clk(dev, true);
623		-
624		- if (dev->isp_ver == ISP_V12 \|\| dev->isp_ver == ISP_V13) {
625		- /* disable csi_rx interrupt */
626		- writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
627		- writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
628		- writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
629		- writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
630		- }
631		-
632	800	return 0;
633	801	err:
634	802	for (--i; i >= 0; --i)
635	803	if (!IS_ERR(dev->clks[i]))
636	804	clk_disable_unprepare(dev->clks[i]);
637	805	return ret;
	806	+}
	807	+
	808	+static int rkisp_get_sram(struct rkisp_hw_dev *hw_dev)
	809	+{
	810	+ struct device *dev = hw_dev->dev;
	811	+ struct rkisp_sram *sram = &hw_dev->sram;
	812	+ struct device_node *np;
	813	+ struct resource res;
	814	+ int ret, size;
	815	+
	816	+ sram->size = 0;
	817	+ np = of_parse_phandle(dev->of_node, "rockchip,sram", 0);
	818	+ if (!np) {
	819	+ dev_warn(dev, "no find phandle sram\n");
	820	+ return -ENODEV;
	821	+ }
	822	+
	823	+ ret = of_address_to_resource(np, 0, &res);
	824	+ of_node_put(np);
	825	+ if (ret) {
	826	+ dev_err(dev, "get sram res error\n");
	827	+ return ret;
	828	+ }
	829	+ size = resource_size(&res);
	830	+ sram->dma_addr = dma_map_resource(dev, res.start, size, DMA_BIDIRECTIONAL, 0);
	831	+ if (dma_mapping_error(dev, sram->dma_addr))
	832	+ return -ENOMEM;
	833	+ sram->size = size;
	834	+ dev_info(dev, "get sram size:%d\n", size);
	835	+ return 0;
	836	+}
	837	+
	838	+static void rkisp_put_sram(struct rkisp_hw_dev *hw_dev)
	839	+{
	840	+ if (hw_dev->sram.size)
	841	+ dma_unmap_resource(hw_dev->dev, hw_dev->sram.dma_addr,
	842	+ hw_dev->sram.size, DMA_BIDIRECTIONAL, 0);
	843	+ hw_dev->sram.size = 0;
638	844	}
639	845
640	846	static int rkisp_hw_probe(struct platform_device *pdev)
..	..	@@ -647,6 +853,7 @@
647	853	struct resource *res;
648	854	int i, ret;
649	855	bool is_mem_reserved = true;
	856	+ u32 clk_rate = 0;
650	857
651	858	match = of_match_node(rkisp_hw_of_match, node);
652	859	if (IS_ERR(match))
..	..	@@ -656,16 +863,12 @@
656	863	if (!hw_dev)
657	864	return -ENOMEM;
658	865
	866	+ match_data = match->data;
659	867	dev_set_drvdata(dev, hw_dev);
660	868	hw_dev->dev = dev;
661	869	hw_dev->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
662	870	dev_info(dev, "is_thunderboot: %d\n", hw_dev->is_thunderboot);
663		- hw_dev->max_in.w = 0;
664		- hw_dev->max_in.h = 0;
665		- hw_dev->max_in.fps = 0;
666		- of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3);
667		- dev_info(dev, "max input:%dx%d@%dfps\n",
668		- hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
	871	+
669	872	hw_dev->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
670	873	if (IS_ERR(hw_dev->grf))
671	874	dev_warn(dev, "Missing rockchip,grf property\n");
..	..	@@ -689,9 +892,51 @@
689	892	goto err;
690	893	}
691	894
692		- rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
	895	+ hw_dev->base_next_addr = NULL;
	896	+ if (match_data->unite) {
	897	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	898	+ if (!res) {
	899	+ dev_err(dev, "get next resource failed\n");
	900	+ ret = -EINVAL;
	901	+ goto err;
	902	+ }
	903	+ hw_dev->base_next_addr = devm_ioremap_resource(dev, res);
	904	+ if (PTR_ERR(hw_dev->base_next_addr) == -EBUSY) {
	905	+ resource_size_t offset = res->start;
	906	+ resource_size_t size = resource_size(res);
693	907
694		- match_data = match->data;
	908	+ hw_dev->base_next_addr = devm_ioremap(dev, offset, size);
	909	+ }
	910	+
	911	+ if (IS_ERR(hw_dev->base_next_addr)) {
	912	+ dev_err(dev, "ioremap next failed\n");
	913	+ ret = PTR_ERR(hw_dev->base_next_addr);
	914	+ goto err;
	915	+ }
	916	+ }
	917	+
	918	+ hw_dev->isp_ver = match_data->isp_ver;
	919	+ if (match_data->unite) {
	920	+ hw_dev->unite = ISP_UNITE_TWO;
	921	+ } else if (device_property_read_bool(dev, "rockchip,unite-en")) {
	922	+ hw_dev->unite = ISP_UNITE_ONE;
	923	+ hw_dev->base_next_addr = hw_dev->base_addr;
	924	+ } else {
	925	+ hw_dev->unite = ISP_UNITE_NONE;
	926	+ }
	927	+
	928	+ memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in));
	929	+ if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) {
	930	+ hw_dev->max_in.is_fix = true;
	931	+ if (hw_dev->unite) {
	932	+ hw_dev->max_in.w /= 2;
	933	+ hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL;
	934	+ }
	935	+ }
	936	+ dev_info(dev, "max input:%dx%d@%dfps\n",
	937	+ hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
	938	+
	939	+ rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
695	940	hw_dev->mipi_irq = -1;
696	941
697	942	hw_dev->pdev = pdev;
..	..	@@ -702,13 +947,21 @@
702	947	for (i = 0; i < match_data->num_clks; i++) {
703	948	struct clk *clk = devm_clk_get(dev, match_data->clks[i]);
704	949
705		- if (IS_ERR(clk))
706		- dev_dbg(dev, "failed to get %s\n", match_data->clks[i]);
	950	+ if (IS_ERR(clk)) {
	951	+ dev_err(dev, "failed to get %s\n", match_data->clks[i]);
	952	+ ret = PTR_ERR(clk);
	953	+ goto err;
	954	+ }
707	955	hw_dev->clks[i] = clk;
708	956	}
709	957	hw_dev->num_clks = match_data->num_clks;
710	958	hw_dev->clk_rate_tbl = match_data->clk_rate_tbl;
711	959	hw_dev->num_clk_rate_tbl = match_data->num_clk_rate_tbl;
	960	+
	961	+ hw_dev->is_assigned_clk = false;
	962	+ ret = of_property_read_u32(node, "assigned-clock-rates", &clk_rate);
	963	+ if (!ret && clk_rate)
	964	+ hw_dev->is_assigned_clk = true;
712	965
713	966	hw_dev->reset = devm_reset_control_array_get(dev, false, false);
714	967	if (IS_ERR(hw_dev->reset)) {
..	..	@@ -722,14 +975,17 @@
722	975	else
723	976	hw_dev->is_feature_on = false;
724	977
	978	+ rkisp_get_sram(hw_dev);
	979	+
725	980	hw_dev->dev_num = 0;
	981	+ hw_dev->dev_link_num = 0;
726	982	hw_dev->cur_dev_id = 0;
727	983	hw_dev->mipi_dev_id = 0;
728		- hw_dev->isp_ver = match_data->isp_ver;
	984	+ hw_dev->pre_dev_id = -1;
	985	+ hw_dev->is_multi_overflow = false;
729	986	mutex_init(&hw_dev->dev_lock);
730	987	spin_lock_init(&hw_dev->rdbk_lock);
731	988	atomic_set(&hw_dev->refcnt, 0);
732		- atomic_set(&hw_dev->tb_ref, 0);
733	989	spin_lock_init(&hw_dev->buf_lock);
734	990	INIT_LIST_HEAD(&hw_dev->list);
735	991	INIT_LIST_HEAD(&hw_dev->rpt_list);
..	..	@@ -738,29 +994,19 @@
738	994	hw_dev->is_single = true;
739	995	hw_dev->is_mi_update = false;
740	996	hw_dev->is_dma_contig = true;
741		- hw_dev->is_dma_sg_ops = false;
	997	+ hw_dev->is_dma_sg_ops = true;
742	998	hw_dev->is_buf_init = false;
743	999	hw_dev->is_shutdown = false;
744	1000	hw_dev->is_mmu = is_iommu_enable(dev);
745	1001	ret = of_reserved_mem_device_init(dev);
746	1002	if (ret) {
747	1003	is_mem_reserved = false;
748		-
749	1004	if (!hw_dev->is_mmu)
750	1005	dev_info(dev, "No reserved memory region. default cma area!\n");
751		- else
752		- hw_dev->is_dma_contig = false;
753	1006	}
754		- if (is_mem_reserved) {
755		- /* reserved memory using rdma_sg */
756		- hw_dev->mem_ops = &vb2_rdma_sg_memops;
757		- hw_dev->is_dma_sg_ops = true;
758		- } else if (hw_dev->is_mmu) {
759		- hw_dev->mem_ops = &vb2_dma_sg_memops;
760		- hw_dev->is_dma_sg_ops = true;
761		- } else {
762		- hw_dev->mem_ops = &vb2_dma_contig_memops;
763		- }
	1007	+ if (hw_dev->is_mmu && !is_mem_reserved)
	1008	+ hw_dev->is_dma_contig = false;
	1009	+ hw_dev->mem_ops = &vb2_cma_sg_memops;
764	1010
765	1011	pm_runtime_enable(dev);
766	1012
..	..	@@ -773,6 +1019,7 @@
773	1019	{
774	1020	struct rkisp_hw_dev *hw_dev = platform_get_drvdata(pdev);
775	1021
	1022	+ rkisp_put_sram(hw_dev);
776	1023	pm_runtime_disable(&pdev->dev);
777	1024	mutex_destroy(&hw_dev->dev_lock);
778	1025	return 0;
..	..	@@ -783,8 +1030,11 @@
783	1030	struct rkisp_hw_dev *hw_dev = platform_get_drvdata(pdev);
784	1031
785	1032	hw_dev->is_shutdown = true;
786		- if (pm_runtime_active(&pdev->dev))
	1033	+ if (pm_runtime_active(&pdev->dev)) {
787	1034	writel(0xffff, hw_dev->base_addr + CIF_IRCL);
	1035	+ if (hw_dev->unite == ISP_UNITE_TWO)
	1036	+ writel(0xffff, hw_dev->base_next_addr + CIF_IRCL);
	1037	+ }
788	1038	dev_info(&pdev->dev, "%s\n", __func__);
789	1039	}
790	1040
..	..	@@ -792,36 +1042,92 @@
792	1042	{
793	1043	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
794	1044
	1045	+ hw_dev->dev_link_num = 0;
	1046	+ hw_dev->is_single = true;
	1047	+ hw_dev->is_multi_overflow = false;
	1048	+ hw_dev->is_frm_buf = false;
795	1049	disable_sys_clk(hw_dev);
796	1050	return pinctrl_pm_select_sleep_state(dev);
	1051	+}
	1052	+
	1053	+void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev)
	1054	+{
	1055	+ struct rkisp_device *isp;
	1056	+ u32 w, h, i;
	1057	+
	1058	+ memset(hw_dev->isp_size, 0, sizeof(hw_dev->isp_size));
	1059	+ if (!hw_dev->max_in.is_fix) {
	1060	+ hw_dev->max_in.w = 0;
	1061	+ hw_dev->max_in.h = 0;
	1062	+ }
	1063	+ hw_dev->dev_link_num = 0;
	1064	+ hw_dev->is_single = true;
	1065	+ hw_dev->is_multi_overflow = false;
	1066	+ hw_dev->is_frm_buf = false;
	1067	+ for (i = 0; i < hw_dev->dev_num; i++) {
	1068	+ isp = hw_dev->isp[i];
	1069	+ if (!isp \|\| (isp && !isp->is_hw_link))
	1070	+ continue;
	1071	+ if (hw_dev->dev_link_num++)
	1072	+ hw_dev->is_single = false;
	1073	+ w = isp->isp_sdev.in_crop.width;
	1074	+ h = isp->isp_sdev.in_crop.height;
	1075	+ if (hw_dev->unite)
	1076	+ w = w / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
	1077	+ hw_dev->isp_size[i].w = w;
	1078	+ hw_dev->isp_size[i].h = h;
	1079	+ hw_dev->isp_size[i].size = w * h;
	1080	+ if (!hw_dev->max_in.is_fix) {
	1081	+ if (hw_dev->max_in.w < w)
	1082	+ hw_dev->max_in.w = w;
	1083	+ if (hw_dev->max_in.h < h)
	1084	+ hw_dev->max_in.h = h;
	1085	+ }
	1086	+ }
	1087	+ if (hw_dev->unite == ISP_UNITE_ONE)
	1088	+ hw_dev->is_single = false;
	1089	+ for (i = 0; i < hw_dev->dev_num; i++) {
	1090	+ isp = hw_dev->isp[i];
	1091	+ if (!isp \|\| (isp && !isp->is_hw_link))
	1092	+ continue;
	1093	+ rkisp_params_check_bigmode(&isp->params_vdev);
	1094	+ }
797	1095	}
798	1096
799	1097	static int __maybe_unused rkisp_runtime_resume(struct device *dev)
800	1098	{
801	1099	struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
802	1100	void __iomem *base = hw_dev->base_addr;
	1101	+ struct rkisp_device *isp;
	1102	+ int mult = hw_dev->unite ? 2 : 1;
803	1103	int ret, i;
	1104	+ void *buf;
804	1105
805	1106	ret = pinctrl_pm_select_default_state(dev);
806	1107	if (ret < 0)
807	1108	return ret;
808	1109
809	1110	enable_sys_clk(hw_dev);
810		-
811	1111	for (i = 0; i < hw_dev->dev_num; i++) {
812		- void *buf = hw_dev->isp[i]->sw_base_addr;
813		-
814		- memset(buf, 0, RKISP_ISP_SW_MAX_SIZE);
	1112	+ isp = hw_dev->isp[i];
	1113	+ if (!isp \|\| !isp->sw_base_addr)
	1114	+ continue;
	1115	+ buf = isp->sw_base_addr;
	1116	+ memset(buf, 0, RKISP_ISP_SW_MAX_SIZE * mult);
815	1117	memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
	1118	+ if (hw_dev->unite) {
	1119	+ buf += RKISP_ISP_SW_MAX_SIZE;
	1120	+ base = hw_dev->base_next_addr;
	1121	+ memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
	1122	+ }
816	1123	default_sw_reg_flag(hw_dev->isp[i]);
817	1124	}
	1125	+ rkisp_hw_enum_isp_size(hw_dev);
818	1126	hw_dev->monitor.is_en = rkisp_monitor;
819	1127	return 0;
820	1128	}
821	1129
822	1130	static const struct dev_pm_ops rkisp_hw_pm_ops = {
823		- SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
824		- pm_runtime_force_resume)
825	1131	SET_RUNTIME_PM_OPS(rkisp_runtime_suspend,
826	1132	rkisp_runtime_resume, NULL)
827	1133	};
..	..	@@ -851,4 +1157,15 @@
851	1157	return ret;
852	1158	}
853	1159
	1160	+static void __exit rkisp_hw_drv_exit(void)
	1161	+{
	1162	+ platform_driver_unregister(&rkisp_plat_drv);
	1163	+ platform_driver_unregister(&rkisp_hw_drv);
	1164	+}
	1165	+
	1166	+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
	1167	+subsys_initcall(rkisp_hw_drv_init);
	1168	+#else
854	1169	module_init(rkisp_hw_drv_init);
	1170	+#endif
	1171	+module_exit(rkisp_hw_drv_exit);