~hc/RK356X_SDK_RELEASE.git

..	..	@@ -15,9 +15,337 @@
15	15
16	16	#define CIF_ISP_REQ_BUFS_MIN 0
17	17
18		-static int mi_frame_end(struct rkisp_stream *stream);
	18	+static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19	19	static void rkisp_buf_queue(struct vb2_buffer *vb);
20	20
	21	+static const struct capture_fmt mp_fmts[] = {
	22	+ /* yuv422 */
	23	+ {
	24	+ .fourcc = V4L2_PIX_FMT_UYVY,
	25	+ .fmt_type = FMT_YUV,
	26	+ .bpp = { 16 },
	27	+ .cplanes = 1,
	28	+ .mplanes = 1,
	29	+ .uv_swap = 0,
	30	+ .write_format = MI_CTRL_MP_WRITE_YUVINT,
	31	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	32	+ }, {
	33	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	34	+ .fmt_type = FMT_YUV,
	35	+ .bpp = { 8, 4, 4 },
	36	+ .cplanes = 3,
	37	+ .mplanes = 1,
	38	+ .uv_swap = 0,
	39	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	40	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	41	+ }, {
	42	+ .fourcc = V4L2_PIX_FMT_NV16,
	43	+ .fmt_type = FMT_YUV,
	44	+ .bpp = { 8, 16 },
	45	+ .cplanes = 2,
	46	+ .mplanes = 1,
	47	+ .uv_swap = 0,
	48	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	49	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	50	+ }, {
	51	+ .fourcc = V4L2_PIX_FMT_NV61,
	52	+ .fmt_type = FMT_YUV,
	53	+ .bpp = { 8, 16 },
	54	+ .cplanes = 2,
	55	+ .mplanes = 1,
	56	+ .uv_swap = 1,
	57	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	58	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	59	+ }, {
	60	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	61	+ .fmt_type = FMT_YUV,
	62	+ .bpp = { 8, 8, 8 },
	63	+ .cplanes = 3,
	64	+ .mplanes = 3,
	65	+ .uv_swap = 0,
	66	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	67	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	68	+ },
	69	+ /* yuv420 */
	70	+ {
	71	+ .fourcc = V4L2_PIX_FMT_NV21,
	72	+ .fmt_type = FMT_YUV,
	73	+ .bpp = { 8, 16 },
	74	+ .cplanes = 2,
	75	+ .mplanes = 1,
	76	+ .uv_swap = 1,
	77	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	78	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	79	+ }, {
	80	+ .fourcc = V4L2_PIX_FMT_NV12,
	81	+ .fmt_type = FMT_YUV,
	82	+ .bpp = { 8, 16 },
	83	+ .cplanes = 2,
	84	+ .mplanes = 1,
	85	+ .uv_swap = 0,
	86	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	87	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	88	+ }, {
	89	+ .fourcc = V4L2_PIX_FMT_NV21M,
	90	+ .fmt_type = FMT_YUV,
	91	+ .bpp = { 8, 16 },
	92	+ .cplanes = 2,
	93	+ .mplanes = 2,
	94	+ .uv_swap = 1,
	95	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	96	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	97	+ }, {
	98	+ .fourcc = V4L2_PIX_FMT_NV12M,
	99	+ .fmt_type = FMT_YUV,
	100	+ .bpp = { 8, 16 },
	101	+ .cplanes = 2,
	102	+ .mplanes = 2,
	103	+ .uv_swap = 0,
	104	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	105	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	106	+ }, {
	107	+ .fourcc = V4L2_PIX_FMT_YUV420,
	108	+ .fmt_type = FMT_YUV,
	109	+ .bpp = { 8, 8, 8 },
	110	+ .cplanes = 3,
	111	+ .mplanes = 1,
	112	+ .uv_swap = 0,
	113	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	114	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	115	+ },
	116	+ /* yuv444 */
	117	+ {
	118	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	119	+ .fmt_type = FMT_YUV,
	120	+ .bpp = { 8, 8, 8 },
	121	+ .cplanes = 3,
	122	+ .mplanes = 3,
	123	+ .uv_swap = 0,
	124	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	125	+ .output_format = 0,
	126	+ },
	127	+ /* raw */
	128	+ {
	129	+ .fourcc = V4L2_PIX_FMT_SRGGB8,
	130	+ .fmt_type = FMT_BAYER,
	131	+ .bpp = { 8 },
	132	+ .mplanes = 1,
	133	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	134	+ .output_format = 0,
	135	+ }, {
	136	+ .fourcc = V4L2_PIX_FMT_SGRBG8,
	137	+ .fmt_type = FMT_BAYER,
	138	+ .bpp = { 8 },
	139	+ .mplanes = 1,
	140	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	141	+ .output_format = 0,
	142	+ }, {
	143	+ .fourcc = V4L2_PIX_FMT_SGBRG8,
	144	+ .fmt_type = FMT_BAYER,
	145	+ .bpp = { 8 },
	146	+ .mplanes = 1,
	147	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	148	+ .output_format = 0,
	149	+ }, {
	150	+ .fourcc = V4L2_PIX_FMT_SBGGR8,
	151	+ .fmt_type = FMT_BAYER,
	152	+ .bpp = { 8 },
	153	+ .mplanes = 1,
	154	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	155	+ .output_format = 0,
	156	+ }, {
	157	+ .fourcc = V4L2_PIX_FMT_SRGGB10,
	158	+ .fmt_type = FMT_BAYER,
	159	+ .bpp = { 10 },
	160	+ .mplanes = 1,
	161	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	162	+ .output_format = 0,
	163	+ }, {
	164	+ .fourcc = V4L2_PIX_FMT_SGRBG10,
	165	+ .fmt_type = FMT_BAYER,
	166	+ .bpp = { 10 },
	167	+ .mplanes = 1,
	168	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	169	+ .output_format = 0,
	170	+ }, {
	171	+ .fourcc = V4L2_PIX_FMT_SGBRG10,
	172	+ .fmt_type = FMT_BAYER,
	173	+ .bpp = { 10 },
	174	+ .mplanes = 1,
	175	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	176	+ .output_format = 0,
	177	+ }, {
	178	+ .fourcc = V4L2_PIX_FMT_SBGGR10,
	179	+ .fmt_type = FMT_BAYER,
	180	+ .bpp = { 10 },
	181	+ .mplanes = 1,
	182	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	183	+ .output_format = 0,
	184	+ }, {
	185	+ .fourcc = V4L2_PIX_FMT_SRGGB12,
	186	+ .fmt_type = FMT_BAYER,
	187	+ .bpp = { 12 },
	188	+ .mplanes = 1,
	189	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	190	+ .output_format = 0,
	191	+ }, {
	192	+ .fourcc = V4L2_PIX_FMT_SGRBG12,
	193	+ .fmt_type = FMT_BAYER,
	194	+ .bpp = { 12 },
	195	+ .mplanes = 1,
	196	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	197	+ .output_format = 0,
	198	+ }, {
	199	+ .fourcc = V4L2_PIX_FMT_SGBRG12,
	200	+ .fmt_type = FMT_BAYER,
	201	+ .bpp = { 12 },
	202	+ .mplanes = 1,
	203	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	204	+ .output_format = 0,
	205	+ }, {
	206	+ .fourcc = V4L2_PIX_FMT_SBGGR12,
	207	+ .fmt_type = FMT_BAYER,
	208	+ .bpp = { 12 },
	209	+ .mplanes = 1,
	210	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	211	+ .output_format = 0,
	212	+ },
	213	+};
	214	+
	215	+static const struct capture_fmt sp_fmts[] = {
	216	+ /* yuv422 */
	217	+ {
	218	+ .fourcc = V4L2_PIX_FMT_UYVY,
	219	+ .fmt_type = FMT_YUV,
	220	+ .bpp = { 16 },
	221	+ .cplanes = 1,
	222	+ .mplanes = 1,
	223	+ .uv_swap = 0,
	224	+ .write_format = MI_CTRL_SP_WRITE_INT,
	225	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	226	+ }, {
	227	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	228	+ .fmt_type = FMT_YUV,
	229	+ .bpp = { 8, 8, 8 },
	230	+ .cplanes = 3,
	231	+ .mplanes = 1,
	232	+ .uv_swap = 0,
	233	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	234	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	235	+ }, {
	236	+ .fourcc = V4L2_PIX_FMT_NV16,
	237	+ .fmt_type = FMT_YUV,
	238	+ .bpp = { 8, 16 },
	239	+ .cplanes = 2,
	240	+ .mplanes = 1,
	241	+ .uv_swap = 0,
	242	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	243	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	244	+ }, {
	245	+ .fourcc = V4L2_PIX_FMT_NV61,
	246	+ .fmt_type = FMT_YUV,
	247	+ .bpp = { 8, 16 },
	248	+ .cplanes = 2,
	249	+ .mplanes = 1,
	250	+ .uv_swap = 1,
	251	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	252	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	253	+ }, {
	254	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	255	+ .fmt_type = FMT_YUV,
	256	+ .bpp = { 8, 8, 8 },
	257	+ .cplanes = 3,
	258	+ .mplanes = 3,
	259	+ .uv_swap = 0,
	260	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	261	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	262	+ },
	263	+ /* yuv420 */
	264	+ {
	265	+ .fourcc = V4L2_PIX_FMT_NV21,
	266	+ .fmt_type = FMT_YUV,
	267	+ .bpp = { 8, 16 },
	268	+ .cplanes = 2,
	269	+ .mplanes = 1,
	270	+ .uv_swap = 1,
	271	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	272	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	273	+ }, {
	274	+ .fourcc = V4L2_PIX_FMT_NV12,
	275	+ .fmt_type = FMT_YUV,
	276	+ .bpp = { 8, 16 },
	277	+ .cplanes = 2,
	278	+ .mplanes = 1,
	279	+ .uv_swap = 0,
	280	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	281	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	282	+ }, {
	283	+ .fourcc = V4L2_PIX_FMT_NV21M,
	284	+ .fmt_type = FMT_YUV,
	285	+ .bpp = { 8, 16 },
	286	+ .cplanes = 2,
	287	+ .mplanes = 2,
	288	+ .uv_swap = 1,
	289	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	290	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	291	+ }, {
	292	+ .fourcc = V4L2_PIX_FMT_NV12M,
	293	+ .fmt_type = FMT_YUV,
	294	+ .bpp = { 8, 16 },
	295	+ .cplanes = 2,
	296	+ .mplanes = 2,
	297	+ .uv_swap = 0,
	298	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	299	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	300	+ }, {
	301	+ .fourcc = V4L2_PIX_FMT_YUV420,
	302	+ .fmt_type = FMT_YUV,
	303	+ .bpp = { 8, 8, 8 },
	304	+ .cplanes = 3,
	305	+ .mplanes = 1,
	306	+ .uv_swap = 0,
	307	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	308	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	309	+ },
	310	+ /* yuv444 */
	311	+ {
	312	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	313	+ .fmt_type = FMT_YUV,
	314	+ .bpp = { 8, 8, 8 },
	315	+ .cplanes = 3,
	316	+ .mplanes = 3,
	317	+ .uv_swap = 0,
	318	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	319	+ .output_format = MI_CTRL_SP_OUTPUT_YUV444,
	320	+ },
	321	+ /* yuv400 */
	322	+ {
	323	+ .fourcc = V4L2_PIX_FMT_GREY,
	324	+ .fmt_type = FMT_YUV,
	325	+ .bpp = { 8 },
	326	+ .cplanes = 1,
	327	+ .mplanes = 1,
	328	+ .uv_swap = 0,
	329	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	330	+ .output_format = MI_CTRL_SP_OUTPUT_YUV400,
	331	+ },
	332	+ /* rgb */
	333	+ {
	334	+ .fourcc = V4L2_PIX_FMT_XBGR32,
	335	+ .fmt_type = FMT_RGB,
	336	+ .bpp = { 32 },
	337	+ .mplanes = 1,
	338	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	339	+ .output_format = MI_CTRL_SP_OUTPUT_RGB888,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_RGB565,
	342	+ .fmt_type = FMT_RGB,
	343	+ .bpp = { 16 },
	344	+ .mplanes = 1,
	345	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	346	+ .output_format = MI_CTRL_SP_OUTPUT_RGB565,
	347	+ },
	348	+};
21	349	static const struct capture_fmt dmatx_fmts[] = {
22	350	/* raw */
23	351	{
..	..	@@ -392,7 +720,7 @@
392	720	stream->out_isp_fmt.write_format, false);
393	721	mi_frame_end_int_enable(stream);
394	722	/* set up first buffer */
395		- mi_frame_end(stream);
	723	+ mi_frame_end(stream, FRAME_INIT);
396	724	return 0;
397	725	}
398	726
..	..	@@ -466,7 +794,7 @@
466	794	CIF_MI_SP_AUTOUPDATE_ENABLE, false);
467	795	mi_frame_end_int_enable(stream);
468	796	/* set up first buffer */
469		- mi_frame_end(stream);
	797	+ mi_frame_end(stream, FRAME_INIT);
470	798	return 0;
471	799	}
472	800
..	..	@@ -483,7 +811,7 @@
483	811
484	812	if (!dev->active_sensor \|\|
485	813	(dev->active_sensor &&
486		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	814	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
487	815	v4l2_err(&dev->v4l2_dev,
488	816	"only mipi sensor support rawwr3\n");
489	817	return -EINVAL;
..	..	@@ -495,7 +823,7 @@
495	823	stream->out_fmt.height);
496	824	raw_wr_set_pic_offs(stream, 0);
497	825	mi_set_y_size(stream, in_size);
498		- mi_frame_end(stream);
	826	+ mi_frame_end(stream, FRAME_INIT);
499	827	mi_frame_end_int_enable(stream);
500	828	mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD);
501	829	mi_raw_length(stream);
..	..	@@ -526,7 +854,7 @@
526	854
527	855	if (!dev->active_sensor \|\|
528	856	(dev->active_sensor &&
529		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	857	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
530	858	v4l2_err(&dev->v4l2_dev,
531	859	"only mipi sensor support rawwr2 path\n");
532	860	return -EINVAL;
..	..	@@ -541,7 +869,7 @@
541	869	stream->out_fmt.height);
542	870	raw_wr_set_pic_offs(stream, 0);
543	871	mi_set_y_size(stream, in_size);
544		- mi_frame_end(stream);
	872	+ mi_frame_end(stream, FRAME_INIT);
545	873	mi_frame_end_int_enable(stream);
546	874	mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD);
547	875	mi_raw_length(stream);
..	..	@@ -571,7 +899,7 @@
571	899
572	900	if (!dev->active_sensor \|\|
573	901	(dev->active_sensor &&
574		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	902	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
575	903	if (stream->id == RKISP_STREAM_DMATX0)
576	904	v4l2_err(&dev->v4l2_dev,
577	905	"only mipi sensor support rawwr0 path\n");
..	..	@@ -587,7 +915,7 @@
587	915	stream->out_fmt.height);
588	916	raw_wr_set_pic_offs(stream, 0);
589	917	mi_set_y_size(stream, in_size);
590		- mi_frame_end(stream);
	918	+ mi_frame_end(stream, FRAME_INIT);
591	919	mi_frame_end_int_enable(stream);
592	920	mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD);
593	921	mi_raw_length(stream);
..	..	@@ -618,8 +946,15 @@
618	946
619	947	static void sp_enable_mi(struct rkisp_stream *stream)
620	948	{
621		- rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, 0,
622		- CIF_MI_CTRL_SP_ENABLE, false);
	949	+ struct rkisp_device *dev = stream->ispdev;
	950	+ struct capture_fmt *fmt = &stream->out_isp_fmt;
	951	+ u32 val = CIF_MI_CTRL_SP_ENABLE;
	952	+ u32 mask = CIF_MI_SP_Y_FULL_YUV2RGB \| CIF_MI_SP_CBCR_FULL_YUV2RGB;
	953	+
	954	+ if (fmt->fmt_type == FMT_RGB &&
	955	+ dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
	956	+ val \|= mask;
	957	+ rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, mask, val, false);
623	958	}
624	959
625	960	static void dmatx_enable_mi(struct rkisp_stream *stream)
..	..	@@ -739,7 +1074,7 @@
739	1074	.enable_mi = mp_enable_mi,
740	1075	.disable_mi = mp_disable_mi,
741	1076	.stop_mi = mp_stop_mi,
742		- .set_data_path = mp_set_data_path,
	1077	+ .set_data_path = stream_data_path,
743	1078	.is_stream_stopped = mp_is_stream_stopped,
744	1079	.update_mi = update_mi,
745	1080	.frame_end = mi_frame_end,
..	..	@@ -750,7 +1085,7 @@
750	1085	.enable_mi = sp_enable_mi,
751	1086	.disable_mi = sp_disable_mi,
752	1087	.stop_mi = sp_stop_mi,
753		- .set_data_path = sp_set_data_path,
	1088	+ .set_data_path = stream_data_path,
754	1089	.is_stream_stopped = sp_is_stream_stopped,
755	1090	.update_mi = update_mi,
756	1091	.frame_end = mi_frame_end,
..	..	@@ -797,7 +1132,7 @@
797	1132	return;
798	1133
799	1134	if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME1) {
800		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1135	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
801	1136	cap->rdbk_buf[RDBK_S] = NULL;
802	1137	return;
803	1138	}
..	..	@@ -834,12 +1169,9 @@
834	1169	goto RDBK_FRM_UNMATCH;
835	1170	}
836	1171
837		- cap->rdbk_buf[RDBK_S]->vb.sequence =
838		- cap->rdbk_buf[RDBK_L]->vb.sequence;
839		- vb2_buffer_done(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf,
840		- VB2_BUF_STATE_DONE);
841		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf,
842		- VB2_BUF_STATE_DONE);
	1172	+ cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
	1173	+ rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
	1174	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
843	1175	} else {
844	1176	v4l2_err(&isp_dev->v4l2_dev, "lost long frames\n");
845	1177	goto RDBK_FRM_UNMATCH;
..	..	@@ -865,7 +1197,7 @@
865	1197	* is processing and we should set up buffer for next-next frame,
866	1198	* otherwise it will overflow.
867	1199	*/
868		-static int mi_frame_end(struct rkisp_stream *stream)
	1200	+static int mi_frame_end(struct rkisp_stream *stream, u32 state)
869	1201	{
870	1202	struct rkisp_device *dev = stream->ispdev;
871	1203	struct rkisp_capture_device *cap = &dev->cap_dev;
..	..	@@ -873,6 +1205,9 @@
873	1205	bool interlaced = stream->interlaced;
874	1206	unsigned long lock_flags = 0;
875	1207	int i = 0;
	1208	+
	1209	+ if (stream->id == RKISP_STREAM_VIR)
	1210	+ return 0;
876	1211
877	1212	if (!stream->next_buf && stream->streaming &&
878	1213	dev->dmarx_dev.trigger == T_MANUAL &&
..	..	@@ -886,6 +1221,7 @@
886	1221	(!interlaced \|\|
887	1222	(stream->u.sp.field_rec == RKISP_FIELD_ODD &&
888	1223	stream->u.sp.field == RKISP_FIELD_EVEN))) {
	1224	+ struct rkisp_stream *vir = &dev->cap_dev.stream[RKISP_STREAM_VIR];
889	1225	struct vb2_buffer *vb2_buf = &stream->curr_buf->vb.vb2_buf;
890	1226	u64 ns = 0;
891	1227
..	..	@@ -936,7 +1272,16 @@
936	1272	rdbk_frame_end(stream);
937	1273	}
938	1274	} else {
939		- vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
	1275	+ if (vir->streaming && vir->conn_id == stream->id) {
	1276	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1277	+ list_add_tail(&stream->curr_buf->queue,
	1278	+ &dev->cap_dev.vir_cpy.queue);
	1279	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1280	+ if (!completion_done(&dev->cap_dev.vir_cpy.cmpl))
	1281	+ complete(&dev->cap_dev.vir_cpy.cmpl);
	1282	+ } else {
	1283	+ rkisp_stream_buf_done(stream, stream->curr_buf);
	1284	+ }
940	1285	}
941	1286
942	1287	stream->curr_buf = NULL;
..	..	@@ -993,7 +1338,9 @@
993	1338	{
994	1339	struct rkisp_device *dev = stream->ispdev;
995	1340	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
	1341	+ unsigned long lock_flags = 0;
996	1342	int ret = 0;
	1343	+ bool is_wait = dev->hw_dev->is_shutdown ? false : true;
997	1344
998	1345	if (!dev->dmarx_dev.trigger &&
999	1346	(is_rdbk_stream(stream) \|\| is_hdr_stream(stream))) {
..	..	@@ -1006,11 +1353,20 @@
1006	1353	stream->id != RKISP_STREAM_SP) \|\| dev->hw_dev->is_single)
1007	1354	stream->ops->stop_mi(stream);
1008	1355
1009		- if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP)
	1356	+ if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP) {
1010	1357	hdr_stop_dmatx(dev);
1011		-
1012		- if (dev->isp_state & ISP_START &&
1013		- !stream->ops->is_stream_stopped(dev->base_addr)) {
	1358	+ if (IS_HDR_RDBK(dev->rd_mode) && !dev->hw_dev->is_single) {
	1359	+ spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
	1360	+ if (dev->hw_dev->cur_dev_id != dev->dev_id \|\| dev->hw_dev->is_idle) {
	1361	+ is_wait = false;
	1362	+ stream->ops->disable_mi(stream);
	1363	+ }
	1364	+ if (atomic_read(&dev->cap_dev.refcnt) == 1 && !is_wait)
	1365	+ dev->isp_state = ISP_STOP;
	1366	+ spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
	1367	+ }
	1368	+ }
	1369	+ if (is_wait && !stream->ops->is_stream_stopped(stream)) {
1014	1370	ret = wait_event_timeout(stream->done,
1015	1371	!stream->streaming,
1016	1372	msecs_to_jiffies(500));
..	..	@@ -1036,6 +1392,98 @@
1036	1392	stream->interlaced = false;
1037	1393	}
1038	1394
	1395	+static void vir_cpy_image(struct work_struct *work)
	1396	+{
	1397	+ struct rkisp_vir_cpy *cpy =
	1398	+ container_of(work, struct rkisp_vir_cpy, work);
	1399	+ struct rkisp_stream *vir = cpy->stream;
	1400	+ struct rkisp_buffer *src_buf = NULL;
	1401	+ unsigned long lock_flags = 0;
	1402	+ u32 i;
	1403	+
	1404	+ v4l2_dbg(1, rkisp_debug, &vir->ispdev->v4l2_dev,
	1405	+ "%s enter\n", __func__);
	1406	+
	1407	+ vir->streaming = true;
	1408	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1409	+ if (!list_empty(&cpy->queue)) {
	1410	+ src_buf = list_first_entry(&cpy->queue,
	1411	+ struct rkisp_buffer, queue);
	1412	+ list_del(&src_buf->queue);
	1413	+ }
	1414	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1415	+
	1416	+ while (src_buf \|\| vir->streaming) {
	1417	+ if (vir->stopping \|\| !vir->streaming)
	1418	+ goto end;
	1419	+
	1420	+ if (!src_buf)
	1421	+ wait_for_completion(&cpy->cmpl);
	1422	+
	1423	+ vir->frame_end = false;
	1424	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1425	+
	1426	+ if (!src_buf && !list_empty(&cpy->queue)) {
	1427	+ src_buf = list_first_entry(&cpy->queue,
	1428	+ struct rkisp_buffer, queue);
	1429	+ list_del(&src_buf->queue);
	1430	+ }
	1431	+
	1432	+ if (src_buf && !vir->curr_buf && !list_empty(&vir->buf_queue)) {
	1433	+ vir->curr_buf = list_first_entry(&vir->buf_queue,
	1434	+ struct rkisp_buffer, queue);
	1435	+ list_del(&vir->curr_buf->queue);
	1436	+ }
	1437	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1438	+
	1439	+ if (!vir->curr_buf \|\| !src_buf)
	1440	+ goto end;
	1441	+
	1442	+ for (i = 0; i < vir->out_isp_fmt.mplanes; i++) {
	1443	+ u32 payload_size = vir->out_fmt.plane_fmt[i].sizeimage;
	1444	+ void *src = vb2_plane_vaddr(&src_buf->vb.vb2_buf, i);
	1445	+ void *dst = vb2_plane_vaddr(&vir->curr_buf->vb.vb2_buf, i);
	1446	+
	1447	+ if (!src \|\| !dst)
	1448	+ break;
	1449	+ vb2_set_plane_payload(&vir->curr_buf->vb.vb2_buf, i, payload_size);
	1450	+ memcpy(dst, src, payload_size);
	1451	+ }
	1452	+
	1453	+ vir->curr_buf->vb.sequence = src_buf->vb.sequence;
	1454	+ vir->curr_buf->vb.vb2_buf.timestamp = src_buf->vb.vb2_buf.timestamp;
	1455	+ vb2_buffer_done(&vir->curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1456	+ vir->curr_buf = NULL;
	1457	+end:
	1458	+ if (src_buf)
	1459	+ vb2_buffer_done(&src_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1460	+ src_buf = NULL;
	1461	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1462	+
	1463	+ if (!list_empty(&cpy->queue)) {
	1464	+ src_buf = list_first_entry(&cpy->queue,
	1465	+ struct rkisp_buffer, queue);
	1466	+ list_del(&src_buf->queue);
	1467	+ } else if (vir->stopping) {
	1468	+ vir->streaming = false;
	1469	+ }
	1470	+
	1471	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1472	+ }
	1473	+
	1474	+ vir->frame_end = true;
	1475	+
	1476	+ if (vir->stopping) {
	1477	+ vir->stopping = false;
	1478	+ vir->streaming = false;
	1479	+ wake_up(&vir->done);
	1480	+ }
	1481	+
	1482	+ v4l2_dbg(1, rkisp_debug, &vir->ispdev->v4l2_dev,
	1483	+ "%s exit\n", __func__);
	1484	+}
	1485	+
	1486	+
1039	1487	/*
1040	1488	* Most of registers inside rockchip isp1 have shadow register since
1041	1489	* they must be not changed during processing a frame.
..	..	@@ -1044,12 +1492,11 @@
1044	1492	*/
1045	1493	static int rkisp_start(struct rkisp_stream *stream)
1046	1494	{
1047		- void __iomem *base = stream->ispdev->base_addr;
1048	1495	struct rkisp_device *dev = stream->ispdev;
1049	1496	int ret;
1050	1497
1051	1498	if (stream->ops->set_data_path)
1052		- stream->ops->set_data_path(base);
	1499	+ stream->ops->set_data_path(stream);
1053	1500	ret = stream->ops->config_mi(stream);
1054	1501	if (ret)
1055	1502	return ret;
..	..	@@ -1204,23 +1651,13 @@
1204	1651	list_del(&buf->queue);
1205	1652	vb2_buffer_done(&buf->vb.vb2_buf, state);
1206	1653	}
1207		- spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1208		-}
1209		-
1210		-static void rkisp_stop_streaming_tx(struct rkisp_stream *stream)
1211		-{
1212		- struct rkisp_device *dev = stream->ispdev;
1213		-
1214		- stream->stopping = true;
1215		- if (dev->isp_state & ISP_START &&
1216		- !stream->ops->is_stream_stopped(dev->base_addr)) {
1217		- stream->ops->stop_mi(stream);
1218		- wait_event_timeout(stream->done, !stream->streaming,
1219		- msecs_to_jiffies(300));
	1654	+ while (!list_empty(&stream->buf_done_list)) {
	1655	+ buf = list_first_entry(&stream->buf_done_list,
	1656	+ struct rkisp_buffer, queue);
	1657	+ list_del(&buf->queue);
	1658	+ vb2_buffer_done(&buf->vb.vb2_buf, state);
1220	1659	}
1221		- stream->stopping = false;
1222		- stream->streaming = false;
1223		- destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
	1660	+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1224	1661	}
1225	1662
1226	1663	static void rkisp_stop_streaming(struct vb2_queue *queue)
..	..	@@ -1231,23 +1668,39 @@
1231	1668	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1232	1669	int ret;
1233	1670
1234		- v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1235		- "%s %d\n", __func__, stream->id);
1236		- if (!stream->streaming)
1237		- return;
1238		-
1239		- if (stream->id != RKISP_STREAM_MP && stream->id != RKISP_STREAM_SP)
1240		- return rkisp_stop_streaming_tx(stream);
1241		-
1242	1671	mutex_lock(&dev->hw_dev->dev_lock);
1243	1672
	1673	+ v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
	1674	+ "%s %d\n", __func__, stream->id);
	1675	+
	1676	+ if (!stream->streaming)
	1677	+ goto end;
	1678	+
	1679	+ if (stream->id == RKISP_STREAM_VIR) {
	1680	+ stream->stopping = true;
	1681	+ wait_event_timeout(stream->done,
	1682	+ stream->frame_end,
	1683	+ msecs_to_jiffies(500));
	1684	+ stream->streaming = false;
	1685	+ stream->stopping = false;
	1686	+ destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
	1687	+
	1688	+ if (!completion_done(&dev->cap_dev.vir_cpy.cmpl))
	1689	+ complete(&dev->cap_dev.vir_cpy.cmpl);
	1690	+ stream->conn_id = -1;
	1691	+ goto end;
	1692	+ }
	1693	+
1244	1694	rkisp_stream_stop(stream);
1245		- /* call to the other devices */
1246		- media_pipeline_stop(&node->vdev.entity);
1247		- ret = dev->pipe.set_stream(&dev->pipe, false);
1248		- if (ret < 0)
1249		- v4l2_err(v4l2_dev,
1250		- "pipeline stream-off failed:%d\n", ret);
	1695	+ if (stream->id == RKISP_STREAM_MP \|\|
	1696	+ stream->id == RKISP_STREAM_SP) {
	1697	+ /* call to the other devices */
	1698	+ media_pipeline_stop(&node->vdev.entity);
	1699	+ ret = dev->pipe.set_stream(&dev->pipe, false);
	1700	+ if (ret < 0)
	1701	+ v4l2_err(v4l2_dev,
	1702	+ "pipeline stream-off failed:%d\n", ret);
	1703	+ }
1251	1704
1252	1705	/* release buffers */
1253	1706	destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
..	..	@@ -1257,7 +1710,8 @@
1257	1710	v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
1258	1711	rkisp_destroy_dummy_buf(stream);
1259	1712	atomic_dec(&dev->cap_dev.refcnt);
1260		-
	1713	+ tasklet_disable(&stream->buf_done_tasklet);
	1714	+end:
1261	1715	mutex_unlock(&dev->hw_dev->dev_lock);
1262	1716	}
1263	1717
..	..	@@ -1300,25 +1754,6 @@
1300	1754	}
1301	1755
1302	1756	static int
1303		-rkisp_start_streaming_tx(struct rkisp_stream *stream)
1304		-{
1305		- struct rkisp_device *dev = stream->ispdev;
1306		- int ret = -1;
1307		-
1308		- if (!dev->isp_inp \|\| !stream->linked)
1309		- goto buffer_done;
1310		-
1311		- ret = rkisp_stream_start(stream);
1312		- if (ret < 0)
1313		- goto buffer_done;
1314		- return 0;
1315		-buffer_done:
1316		- destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
1317		- stream->streaming = false;
1318		- return ret;
1319		-}
1320		-
1321		-static int
1322	1757	rkisp_start_streaming(struct vb2_queue *queue, unsigned int count)
1323	1758	{
1324	1759	struct rkisp_stream *stream = queue->drv_priv;
..	..	@@ -1327,16 +1762,39 @@
1327	1762	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1328	1763	int ret = -1;
1329	1764
	1765	+ mutex_lock(&dev->hw_dev->dev_lock);
	1766	+
1330	1767	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1331	1768	"%s %d\n", __func__, stream->id);
1332		- if (WARN_ON(stream->streaming))
	1769	+
	1770	+ if (WARN_ON(stream->streaming)) {
	1771	+ mutex_unlock(&dev->hw_dev->dev_lock);
1333	1772	return -EBUSY;
	1773	+ }
	1774	+
	1775	+ if (stream->id == RKISP_STREAM_VIR) {
	1776	+ struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
	1777	+
	1778	+ if (t->streaming) {
	1779	+ INIT_WORK(&dev->cap_dev.vir_cpy.work, vir_cpy_image);
	1780	+ init_completion(&dev->cap_dev.vir_cpy.cmpl);
	1781	+ INIT_LIST_HEAD(&dev->cap_dev.vir_cpy.queue);
	1782	+ dev->cap_dev.vir_cpy.stream = stream;
	1783	+ schedule_work(&dev->cap_dev.vir_cpy.work);
	1784	+ ret = 0;
	1785	+ } else {
	1786	+ v4l2_err(&dev->v4l2_dev,
	1787	+ "no stream enable for iqtool\n");
	1788	+ destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
	1789	+ ret = -EINVAL;
	1790	+ }
	1791	+
	1792	+ mutex_unlock(&dev->hw_dev->dev_lock);
	1793	+
	1794	+ return ret;
	1795	+ }
	1796	+
1334	1797	memset(&stream->dbg, 0, sizeof(stream->dbg));
1335		-
1336		- if (stream->id != RKISP_STREAM_MP && stream->id != RKISP_STREAM_SP)
1337		- return rkisp_start_streaming_tx(stream);
1338		-
1339		- mutex_lock(&dev->hw_dev->dev_lock);
1340	1798	atomic_inc(&dev->cap_dev.refcnt);
1341	1799	if (!dev->isp_inp \|\| !stream->linked) {
1342	1800	v4l2_err(v4l2_dev, "check video link or isp input\n");
..	..	@@ -1386,18 +1844,21 @@
1386	1844	goto close_pipe;
1387	1845	}
1388	1846
1389		- /* start sub-devices */
1390		- ret = dev->pipe.set_stream(&dev->pipe, true);
1391		- if (ret < 0)
1392		- goto stop_stream;
	1847	+ if (stream->id == RKISP_STREAM_MP \|\|
	1848	+ stream->id == RKISP_STREAM_SP) {
	1849	+ /* start sub-devices */
	1850	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	1851	+ if (ret < 0)
	1852	+ goto stop_stream;
1393	1853
1394		- ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
1395		- if (ret < 0) {
1396		- v4l2_err(&dev->v4l2_dev,
1397		- "start pipeline failed %d\n", ret);
1398		- goto pipe_stream_off;
	1854	+ ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
	1855	+ if (ret < 0) {
	1856	+ v4l2_err(&dev->v4l2_dev,
	1857	+ "start pipeline failed %d\n", ret);
	1858	+ goto pipe_stream_off;
	1859	+ }
1399	1860	}
1400		-
	1861	+ tasklet_enable(&stream->buf_done_tasklet);
1401	1862	mutex_unlock(&dev->hw_dev->dev_lock);
1402	1863	return 0;
1403	1864
..	..	@@ -1464,38 +1925,49 @@
1464	1925	INIT_LIST_HEAD(&stream->buf_queue);
1465	1926	init_waitqueue_head(&stream->done);
1466	1927	spin_lock_init(&stream->vbq_lock);
1467		- stream->linked = MEDIA_LNK_FL_ENABLED;
	1928	+ stream->linked = true;
1468	1929
1469	1930	switch (id) {
1470	1931	case RKISP_STREAM_SP:
1471		- strlcpy(vdev->name, SP_VDEV_NAME,
	1932	+ strscpy(vdev->name, SP_VDEV_NAME,
1472	1933	sizeof(vdev->name));
1473	1934	stream->ops = &rkisp_sp_streams_ops;
1474	1935	stream->config = &rkisp_sp_stream_config;
	1936	+ stream->config->fmts = sp_fmts;
	1937	+ stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
1475	1938	break;
1476	1939	case RKISP_STREAM_DMATX0:
1477		- strlcpy(vdev->name, DMATX0_VDEV_NAME,
	1940	+ strscpy(vdev->name, DMATX0_VDEV_NAME,
1478	1941	sizeof(vdev->name));
1479	1942	stream->ops = &rkisp2_dmatx0_streams_ops;
1480	1943	stream->config = &rkisp2_dmatx0_stream_config;
1481	1944	break;
1482	1945	case RKISP_STREAM_DMATX2:
1483		- strlcpy(vdev->name, DMATX2_VDEV_NAME,
	1946	+ strscpy(vdev->name, DMATX2_VDEV_NAME,
1484	1947	sizeof(vdev->name));
1485	1948	stream->ops = &rkisp2_dmatx2_streams_ops;
1486	1949	stream->config = &rkisp2_dmatx1_stream_config;
1487	1950	break;
1488	1951	case RKISP_STREAM_DMATX3:
1489		- strlcpy(vdev->name, DMATX3_VDEV_NAME,
	1952	+ strscpy(vdev->name, DMATX3_VDEV_NAME,
1490	1953	sizeof(vdev->name));
1491	1954	stream->ops = &rkisp2_dmatx3_streams_ops;
1492	1955	stream->config = &rkisp2_dmatx3_stream_config;
1493	1956	break;
	1957	+ case RKISP_STREAM_VIR:
	1958	+ strscpy(vdev->name, VIR_VDEV_NAME,
	1959	+ sizeof(vdev->name));
	1960	+ stream->ops = NULL;
	1961	+ stream->config = &rkisp_mp_stream_config;
	1962	+ stream->conn_id = -1;
	1963	+ break;
1494	1964	default:
1495		- strlcpy(vdev->name, MP_VDEV_NAME,
	1965	+ strscpy(vdev->name, MP_VDEV_NAME,
1496	1966	sizeof(vdev->name));
1497	1967	stream->ops = &rkisp_mp_streams_ops;
1498	1968	stream->config = &rkisp_mp_stream_config;
	1969	+ stream->config->fmts = mp_fmts;
	1970	+ stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
1499	1971	}
1500	1972
1501	1973	node = vdev_to_node(vdev);
..	..	@@ -1534,8 +2006,13 @@
1534	2006	ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX3);
1535	2007	if (ret < 0)
1536	2008	goto err_free_tx2;
	2009	+ ret = rkisp_stream_init(dev, RKISP_STREAM_VIR);
	2010	+ if (ret < 0)
	2011	+ goto err_free_tx3;
1537	2012
1538	2013	return 0;
	2014	+err_free_tx3:
	2015	+ rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX3]);
1539	2016	err_free_tx2:
1540	2017	rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX2]);
1541	2018	err_free_tx0:
..	..	@@ -1563,6 +2040,8 @@
1563	2040	rkisp_unregister_stream_vdev(stream);
1564	2041	stream = &cap_dev->stream[RKISP_STREAM_DMATX3];
1565	2042	rkisp_unregister_stream_vdev(stream);
	2043	+ stream = &cap_dev->stream[RKISP_STREAM_VIR];
	2044	+ rkisp_unregister_stream_vdev(stream);
1566	2045	}
1567	2046
1568	2047	/************** Interrupter Handler **************/
..	..	@@ -1582,7 +2061,7 @@
1582	2061	for (i = 0; i < RKISP_MAX_STREAM; ++i) {
1583	2062	stream = &dev->cap_dev.stream[i];
1584	2063
1585		- if (!(mis_val & CIF_MI_FRAME(stream)))
	2064	+ if (!(mis_val & CIF_MI_FRAME(stream)) \|\| stream->id == RKISP_STREAM_VIR)
1586	2065	continue;
1587	2066
1588	2067	if (i == RKISP_STREAM_DMATX0)
..	..	@@ -1607,7 +2086,7 @@
1607	2086	stream->streaming = false;
1608	2087	stream->ops->disable_mi(stream);
1609	2088	wake_up(&stream->done);
1610		- } else if (stream->ops->is_stream_stopped(dev->base_addr)) {
	2089	+ } else if (stream->ops->is_stream_stopped(stream)) {
1611	2090	stream->stopping = false;
1612	2091	stream->streaming = false;
1613	2092	wake_up(&stream->done);
..	..	@@ -1617,7 +2096,7 @@
1617	2096	end_tx2 = false;
1618	2097	}
1619	2098	} else {
1620		- mi_frame_end(stream);
	2099	+ mi_frame_end(stream, FRAME_IRQ);
1621	2100	if (dev->dmarx_dev.trigger == T_AUTO &&
1622	2101	((dev->hdr.op_mode == HDR_RDBK_FRAME1 && end_tx2) \|\|
1623	2102	(dev->hdr.op_mode == HDR_RDBK_FRAME2 && end_tx2 && end_tx0))) {
..	..	@@ -1632,13 +2111,13 @@
1632	2111	stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
1633	2112	if (!stream->streaming)
1634	2113	dev->irq_ends_mask &= ~ISP_FRAME_MP;
1635		- rkisp_check_idle(dev, ISP_FRAME_MP & dev->irq_ends_mask);
	2114	+ rkisp_check_idle(dev, ISP_FRAME_MP);
1636	2115	}
1637	2116	if (mis_val & CIF_MI_SP_FRAME) {
1638	2117	stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
1639	2118	if (!stream->streaming)
1640	2119	dev->irq_ends_mask &= ~ISP_FRAME_SP;
1641		- rkisp_check_idle(dev, ISP_FRAME_SP & dev->irq_ends_mask);
	2120	+ rkisp_check_idle(dev, ISP_FRAME_SP);
1642	2121	}
1643	2122	}
1644	2123