~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8	#include <linux/delay.h>
9	9	#include <linux/interrupt.h>
10	10	#include <linux/module.h>
	11	+#include <linux/nvmem-consumer.h>
11	12	#include <linux/of.h>
12	13	#include <linux/of_gpio.h>
13	14	#include <linux/of_graph.h>
..	..	@@ -17,14 +18,17 @@
17	18	#include <linux/pm_runtime.h>
18	19	#include <linux/pinctrl/consumer.h>
19	20	#include <linux/regmap.h>
	21	+#include <media/videobuf2-cma-sg.h>
20	22	#include <media/videobuf2-dma-contig.h>
	23	+#include <media/videobuf2-dma-sg.h>
21	24	#include <media/v4l2-fwnode.h>
22	25	#include <linux/iommu.h>
23	26	#include <dt-bindings/soc/rockchip-system-status.h>
24	27	#include <soc/rockchip/rockchip-system-status.h>
25	28	#include <linux/io.h>
26	29	#include <linux/mfd/syscon.h>
27		-#include "dev.h"
	30	+#include <soc/rockchip/rockchip_iommu.h>
	31	+#include "common.h"
28	32
29	33	static const struct cif_reg px30_cif_regs[] = {
30	34	[CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
..	..	@@ -597,6 +601,365 @@
597	601	[CIF_REG_GRF_CIFIO_CON1] = CIF_REG(CIF_GRF_VI_CON1),
598	602	};
599	603
	604	+static const char * const rk3588_cif_clks[] = {
	605	+ "aclk_cif",
	606	+ "hclk_cif",
	607	+ "dclk_cif",
	608	+ "iclk_host0",
	609	+ "iclk_host1",
	610	+};
	611	+
	612	+static const char * const rk3588_cif_rsts[] = {
	613	+ "rst_cif_a",
	614	+ "rst_cif_h",
	615	+ "rst_cif_d",
	616	+ "rst_cif_host0",
	617	+ "rst_cif_host1",
	618	+ "rst_cif_host2",
	619	+ "rst_cif_host3",
	620	+ "rst_cif_host4",
	621	+ "rst_cif_host5",
	622	+};
	623	+
	624	+static const struct cif_reg rk3588_cif_regs[] = {
	625	+ [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
	626	+ [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
	627	+ [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
	628	+ [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
	629	+ [CIF_REG_DVP_MULTI_ID] = CIF_REG(DVP_MULTI_ID),
	630	+ [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
	631	+ [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
	632	+ [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
	633	+ [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
	634	+ [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
	635	+ [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(DVP_FRM0_ADDR_Y_ID1),
	636	+ [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(DVP_FRM0_ADDR_UV_ID1),
	637	+ [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(DVP_FRM1_ADDR_Y_ID1),
	638	+ [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(DVP_FRM1_ADDR_UV_ID1),
	639	+ [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(DVP_FRM0_ADDR_Y_ID2),
	640	+ [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(DVP_FRM0_ADDR_UV_ID2),
	641	+ [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(DVP_FRM1_ADDR_Y_ID2),
	642	+ [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(DVP_FRM1_ADDR_UV_ID2),
	643	+ [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(DVP_FRM0_ADDR_Y_ID3),
	644	+ [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(DVP_FRM0_ADDR_UV_ID3),
	645	+ [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(DVP_FRM1_ADDR_Y_ID3),
	646	+ [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(DVP_FRM1_ADDR_UV_ID3),
	647	+ [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
	648	+ [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
	649	+ [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
	650	+ [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
	651	+ [CIF_REG_DVP_LINE_INT_NUM1] = CIF_REG(DVP_LINE_INT_NUM_23),
	652	+ [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_INT_NUM_01),
	653	+ [CIF_REG_DVP_LINE_CNT1] = CIF_REG(DVP_LINE_INT_NUM_23),
	654	+
	655	+ [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
	656	+ [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
	657	+ [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
	658	+ [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
	659	+ [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
	660	+ [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
	661	+ [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
	662	+ [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
	663	+ [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
	664	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
	665	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
	666	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
	667	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
	668	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
	669	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
	670	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
	671	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
	672	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
	673	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
	674	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
	675	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
	676	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
	677	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
	678	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
	679	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
	680	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
	681	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
	682	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
	683	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
	684	+ [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
	685	+ [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
	686	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
	687	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
	688	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
	689	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
	690	+ [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
	691	+ [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
	692	+ [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
	693	+ [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
	694	+ [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
	695	+ [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
	696	+ [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
	697	+ [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
	698	+ [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
	699	+ [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
	700	+ [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
	701	+ [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
	702	+ [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
	703	+
	704	+ [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
	705	+ [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
	706	+ [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
	707	+
	708	+ [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
	709	+ [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
	710	+ [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
	711	+ [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
	712	+ [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
	713	+ [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
	714	+ [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
	715	+ [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
	716	+ [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
	717	+ [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
	718	+ [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
	719	+ [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
	720	+ [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
	721	+ [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
	722	+ [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
	723	+ [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
	724	+ [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
	725	+ [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
	726	+ [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
	727	+ [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
	728	+ [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
	729	+ [CIF_REG_TOISP1_CTRL] = CIF_REG(TOISP1_CH_CTRL),
	730	+ [CIF_REG_TOISP1_SIZE] = CIF_REG(TOISP1_CROP_SIZE),
	731	+ [CIF_REG_TOISP1_CROP] = CIF_REG(TOISP1_CROP),
	732	+ [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_SOC_CON2),
	733	+};
	734	+
	735	+static const char * const rv1106_cif_clks[] = {
	736	+ "aclk_cif",
	737	+ "hclk_cif",
	738	+ "dclk_cif",
	739	+ "pclk_cif",
	740	+ "i0clk_cif",
	741	+ "i1clk_cif",
	742	+ "rx0clk_cif",
	743	+ "rx1clk_cif",
	744	+ "isp0clk_cif",
	745	+ "sclk_m0_cif",
	746	+ "sclk_m1_cif",
	747	+ "pclk_vepu_cif",
	748	+};
	749	+
	750	+static const char * const rv1106_cif_rsts[] = {
	751	+ "rst_cif_a",
	752	+ "rst_cif_h",
	753	+ "rst_cif_d",
	754	+ "rst_cif_p",
	755	+ "rst_cif_i0",
	756	+ "rst_cif_i1",
	757	+ "rst_cif_rx0",
	758	+ "rst_cif_rx1",
	759	+ "rst_cif_isp0",
	760	+ "rst_cif_pclk_vepu",
	761	+};
	762	+
	763	+static const struct cif_reg rv1106_cif_regs[] = {
	764	+ [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
	765	+ [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
	766	+ [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
	767	+ [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
	768	+ [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
	769	+ [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
	770	+ [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
	771	+ [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
	772	+ [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
	773	+ [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
	774	+ [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
	775	+ [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
	776	+ [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
	777	+ [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_CNT_01),
	778	+
	779	+ [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
	780	+ [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
	781	+ [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
	782	+ [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
	783	+ [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
	784	+ [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
	785	+ [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
	786	+ [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
	787	+ [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
	788	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
	789	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
	790	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
	791	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
	792	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
	793	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
	794	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
	795	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
	796	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
	797	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
	798	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
	799	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
	800	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
	801	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
	802	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
	803	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
	804	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
	805	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
	806	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
	807	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
	808	+ [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
	809	+ [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
	810	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
	811	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
	812	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
	813	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
	814	+ [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
	815	+ [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
	816	+ [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
	817	+ [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
	818	+ [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
	819	+ [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
	820	+ [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
	821	+ [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
	822	+ [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
	823	+ [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
	824	+ [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
	825	+ [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
	826	+ [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
	827	+ [CIF_REG_LVDS_ID0_CTRL0] = CIF_REG(CIF_LVDS0_ID0_CTRL0),
	828	+ [CIF_REG_LVDS_ID1_CTRL0] = CIF_REG(CIF_LVDS0_ID1_CTRL0),
	829	+ [CIF_REG_LVDS_ID2_CTRL0] = CIF_REG(CIF_LVDS0_ID2_CTRL0),
	830	+ [CIF_REG_LVDS_ID3_CTRL0] = CIF_REG(CIF_LVDS0_ID3_CTRL0),
	831	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106),
	832	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106),
	833	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106),
	834	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106),
	835	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106),
	836	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106),
	837	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106),
	838	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106),
	839	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106),
	840	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106),
	841	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106),
	842	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106),
	843	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106),
	844	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106),
	845	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106),
	846	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106),
	847	+ [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
	848	+ [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
	849	+ [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
	850	+
	851	+ [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
	852	+ [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
	853	+ [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
	854	+ [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
	855	+ [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
	856	+ [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
	857	+ [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
	858	+ [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
	859	+ [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
	860	+ [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
	861	+ [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
	862	+ [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
	863	+ [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
	864	+ [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
	865	+ [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
	866	+ [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
	867	+ [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
	868	+ [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
	869	+
	870	+ [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
	871	+ [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
	872	+ [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
	873	+ [CIF_REG_GRF_CIFIO_CON] = CIF_REG(RV1106_CIF_GRF_VI_CON),
	874	+ [CIF_REG_GRF_CIFIO_VENC] = CIF_REG(RV1106_CIF_GRF_VENC_WRAPPER),
	875	+};
	876	+
	877	+static const char * const rk3562_cif_clks[] = {
	878	+ "aclk_cif",
	879	+ "hclk_cif",
	880	+ "dclk_cif",
	881	+ "csirx0_data",
	882	+ "csirx1_data",
	883	+ "csirx2_data",
	884	+ "csirx3_data",
	885	+};
	886	+
	887	+static const char * const rk3562_cif_rsts[] = {
	888	+ "rst_cif_a",
	889	+ "rst_cif_h",
	890	+ "rst_cif_d",
	891	+ "rst_cif_i0",
	892	+ "rst_cif_i1",
	893	+ "rst_cif_i2",
	894	+ "rst_cif_i3",
	895	+};
	896	+
	897	+static const struct cif_reg rk3562_cif_regs[] = {
	898	+ [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
	899	+ [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
	900	+ [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
	901	+ [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
	902	+ [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
	903	+ [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
	904	+ [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
	905	+ [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
	906	+ [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
	907	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
	908	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
	909	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
	910	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
	911	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
	912	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
	913	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
	914	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
	915	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
	916	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
	917	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
	918	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
	919	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
	920	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
	921	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
	922	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
	923	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
	924	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
	925	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
	926	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
	927	+ [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
	928	+ [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
	929	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
	930	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
	931	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
	932	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
	933	+ [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
	934	+ [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
	935	+ [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
	936	+ [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
	937	+ [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
	938	+ [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
	939	+ [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
	940	+ [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
	941	+ [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
	942	+ [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
	943	+ [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
	944	+ [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
	945	+ [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
	946	+
	947	+ [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
	948	+ [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
	949	+ [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
	950	+
	951	+ [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
	952	+ [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
	953	+ [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
	954	+ [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
	955	+ [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
	956	+ [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
	957	+
	958	+ [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
	959	+ [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
	960	+ [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
	961	+};
	962	+
600	963	static const struct rkcif_hw_match_data px30_cif_match_data = {
601	964	.chip_id = CHIP_PX30_CIF,
602	965	.clks = px30_cif_clks,
..	..	@@ -678,6 +1041,32 @@
678	1041	.cif_regs = rk3568_cif_regs,
679	1042	};
680	1043
	1044	+static const struct rkcif_hw_match_data rk3588_cif_match_data = {
	1045	+ .chip_id = CHIP_RK3588_CIF,
	1046	+ .clks = rk3588_cif_clks,
	1047	+ .clks_num = ARRAY_SIZE(rk3588_cif_clks),
	1048	+ .rsts = rk3588_cif_rsts,
	1049	+ .rsts_num = ARRAY_SIZE(rk3588_cif_rsts),
	1050	+ .cif_regs = rk3588_cif_regs,
	1051	+};
	1052	+
	1053	+static const struct rkcif_hw_match_data rv1106_cif_match_data = {
	1054	+ .chip_id = CHIP_RV1106_CIF,
	1055	+ .clks = rv1106_cif_clks,
	1056	+ .clks_num = ARRAY_SIZE(rv1106_cif_clks),
	1057	+ .rsts = rv1106_cif_rsts,
	1058	+ .rsts_num = ARRAY_SIZE(rv1106_cif_rsts),
	1059	+ .cif_regs = rv1106_cif_regs,
	1060	+};
	1061	+
	1062	+static const struct rkcif_hw_match_data rk3562_cif_match_data = {
	1063	+ .chip_id = CHIP_RK3562_CIF,
	1064	+ .clks = rk3562_cif_clks,
	1065	+ .clks_num = ARRAY_SIZE(rk3562_cif_clks),
	1066	+ .rsts = rk3562_cif_rsts,
	1067	+ .rsts_num = ARRAY_SIZE(rk3562_cif_rsts),
	1068	+ .cif_regs = rk3562_cif_regs,
	1069	+};
681	1070
682	1071	static const struct of_device_id rkcif_plat_of_match[] = {
683	1072	#ifdef CONFIG_CPU_PX30
..	..	@@ -722,6 +1111,12 @@
722	1111	.data = &rk3568_cif_match_data,
723	1112	},
724	1113	#endif
	1114	+#ifdef CONFIG_CPU_RK3588
	1115	+ {
	1116	+ .compatible = "rockchip,rk3588-cif",
	1117	+ .data = &rk3588_cif_match_data,
	1118	+ },
	1119	+#endif
725	1120	#ifdef CONFIG_CPU_RV1126
726	1121	{
727	1122	.compatible = "rockchip,rv1126-cif",
..	..	@@ -732,6 +1127,18 @@
732	1127	.data = &rv1126_cif_lite_match_data,
733	1128	},
734	1129	#endif
	1130	+#ifdef CONFIG_CPU_RV1106
	1131	+ {
	1132	+ .compatible = "rockchip,rv1106-cif",
	1133	+ .data = &rv1106_cif_match_data,
	1134	+ },
	1135	+#endif
	1136	+#ifdef CONFIG_CPU_RK3562
	1137	+ {
	1138	+ .compatible = "rockchip,rk3562-cif",
	1139	+ .data = &rk3562_cif_match_data,
	1140	+ },
	1141	+#endif
735	1142	{},
736	1143	};
737	1144
..	..	@@ -739,16 +1146,32 @@
739	1146	{
740	1147	struct device *dev = ctx;
741	1148	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
	1149	+ unsigned int intstat_glb = 0;
	1150	+ u64 irq_start, irq_stop;
742	1151	int i;
743		- struct rkcif_device *tmp_dev = NULL;
744	1152
745		- for (i = 0; i < cif_hw->dev_num; i++) {
746		- tmp_dev = cif_hw->cif_dev[i];
747		- if (tmp_dev->isr_hdl &&
748		- (atomic_read(&tmp_dev->pipe.stream_cnt) != 0))
749		- tmp_dev->isr_hdl(irq, tmp_dev);
	1153	+ irq_start = ktime_get_ns();
	1154	+ if (cif_hw->chip_id >= CHIP_RK3588_CIF) {
	1155	+ intstat_glb = rkcif_irq_global(cif_hw->cif_dev[0]);
	1156	+ if (intstat_glb)
	1157	+ rkcif_write_register(cif_hw->cif_dev[0], CIF_REG_GLB_INTST, intstat_glb);
750	1158	}
751	1159
	1160	+ for (i = 0; i < cif_hw->dev_num; i++) {
	1161	+ if (cif_hw->cif_dev[i]->isr_hdl) {
	1162	+ cif_hw->cif_dev[i]->isr_hdl(irq, cif_hw->cif_dev[i]);
	1163	+ if (cif_hw->cif_dev[i]->err_state &&
	1164	+ (!work_busy(&cif_hw->cif_dev[i]->err_state_work.work))) {
	1165	+ cif_hw->cif_dev[i]->err_state_work.err_state = cif_hw->cif_dev[i]->err_state;
	1166	+ cif_hw->cif_dev[i]->err_state = 0;
	1167	+ schedule_work(&cif_hw->cif_dev[i]->err_state_work.work);
	1168	+ }
	1169	+ if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb)
	1170	+ rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb);
	1171	+ }
	1172	+ }
	1173	+ irq_stop = ktime_get_ns();
	1174	+ cif_hw->irq_time = irq_stop - irq_start;
752	1175	return IRQ_HANDLED;
753	1176	}
754	1177
..	..	@@ -783,17 +1206,14 @@
783	1206
784	1207	static void rkcif_iommu_cleanup(struct rkcif_hw *cif_hw)
785	1208	{
786		- if (cif_hw->domain)
787		- iommu_detach_device(cif_hw->domain, cif_hw->dev);
	1209	+ if (cif_hw->iommu_en)
	1210	+ rockchip_iommu_disable(cif_hw->dev);
788	1211	}
789	1212
790	1213	static void rkcif_iommu_enable(struct rkcif_hw *cif_hw)
791	1214	{
792		- if (!cif_hw->domain)
793		- cif_hw->domain = iommu_get_domain_for_dev(cif_hw->dev);
794		-
795		- if (cif_hw->domain)
796		- iommu_attach_device(cif_hw->domain, cif_hw->dev);
	1215	+ if (cif_hw->iommu_en)
	1216	+ rockchip_iommu_enable(cif_hw->dev);
797	1217	}
798	1218
799	1219	static inline bool is_iommu_enable(struct device *dev)
..	..	@@ -833,81 +1253,49 @@
833	1253	rkcif_iommu_enable(cif_hw);
834	1254	}
835	1255
836		-static char *rkcif_get_monitor_mode(enum rkcif_monitor_mode mode)
	1256	+static int rkcif_get_efuse_value(struct device_node np, char porp_name,
	1257	+ u8 *value)
837	1258	{
838		- switch (mode) {
839		- case RKCIF_MONITOR_MODE_IDLE:
840		- return "idle";
841		- case RKCIF_MONITOR_MODE_CONTINUE:
842		- return "continue";
843		- case RKCIF_MONITOR_MODE_TRIGGER:
844		- return "trigger";
845		- case RKCIF_MONITOR_MODE_HOTPLUG:
846		- return "hotplug";
847		- default:
848		- return "unknown";
849		- }
	1259	+ struct nvmem_cell *cell;
	1260	+ unsigned char *buf;
	1261	+ size_t len;
	1262	+
	1263	+ cell = of_nvmem_cell_get(np, porp_name);
	1264	+ if (IS_ERR(cell))
	1265	+ return PTR_ERR(cell);
	1266	+
	1267	+ buf = (unsigned char *)nvmem_cell_read(cell, &len);
	1268	+
	1269	+ nvmem_cell_put(cell);
	1270	+
	1271	+ if (IS_ERR(buf))
	1272	+ return PTR_ERR(buf);
	1273	+
	1274	+ *value = buf[0];
	1275	+
	1276	+ kfree(buf);
	1277	+
	1278	+ return 0;
850	1279	}
851	1280
852		-static void rkcif_init_reset_timer(struct rkcif_hw *hw)
	1281	+static int rkcif_get_speciand_package_number(struct device_node *np)
853	1282	{
854		- struct device_node *node = hw->dev->of_node;
855		- struct rkcif_hw_timer *hw_timer = &hw->hw_timer;
856		- u32 para[8];
857		- int i;
	1283	+ u8 spec = 0, package = 0, low = 0, high = 0;
858	1284
859		- if (!of_property_read_u32_array(node,
860		- OF_CIF_MONITOR_PARA,
861		- para,
862		- CIF_MONITOR_PARA_NUM)) {
863		- for (i = 0; i < CIF_MONITOR_PARA_NUM; i++) {
864		- if (i == 0) {
865		- hw_timer->monitor_mode = para[0];
866		- dev_info(hw->dev,
867		- "%s: timer monitor mode:%s\n",
868		- __func__, rkcif_get_monitor_mode(hw_timer->monitor_mode));
869		- }
	1285	+ if (rkcif_get_efuse_value(np, "specification", &spec))
	1286	+ return -EINVAL;
	1287	+ if (rkcif_get_efuse_value(np, "package_low", &low))
	1288	+ return -EINVAL;
	1289	+ if (rkcif_get_efuse_value(np, "package_high", &high))
	1290	+ return -EINVAL;
870	1291
871		- if (i == 1) {
872		- hw_timer->monitor_cycle = para[1];
873		- dev_info(hw->dev,
874		- "timer of monitor cycle:%d\n",
875		- hw_timer->monitor_cycle);
876		- }
	1292	+ package = ((high & 0x1) << 3) \| low;
877	1293
878		- if (i == 2) {
879		- hw_timer->err_time_interval = para[2];
880		- dev_info(hw->dev,
881		- "timer err time for keeping:%d ms\n",
882		- hw_timer->err_time_interval);
883		- }
	1294	+ /* RK3588S */
	1295	+ if (spec == 0x13)
	1296	+ return package;
884	1297
885		- if (i == 3) {
886		- hw_timer->err_ref_cnt = para[3];
887		- dev_info(hw->dev,
888		- "timer err ref val for resetting:%d\n",
889		- hw_timer->err_ref_cnt);
890		- }
891		-
892		- if (i == 4) {
893		- hw_timer->is_reset_by_user = para[4];
894		- dev_info(hw->dev,
895		- "reset by user:%d\n",
896		- hw_timer->is_reset_by_user);
897		- }
898		- }
899		- } else {
900		- hw_timer->monitor_mode = RKCIF_MONITOR_MODE_IDLE;
901		- hw_timer->err_time_interval = 0xffffffff;
902		- hw_timer->monitor_cycle = 0xffffffff;
903		- hw_timer->err_ref_cnt = 0xffffffff;
904		- hw_timer->is_reset_by_user = 0;
905		- }
906		-
907		- hw_timer->is_running = false;
908		- spin_lock_init(&hw_timer->timer_lock);
909		- hw->reset_info.is_need_reset = 0;
910		- timer_setup(&hw_timer->timer, rkcif_reset_watchdog_timer_handler, 0);
	1298	+ return -EINVAL;
911	1299	}
912	1300
913	1301	static int rkcif_plat_hw_probe(struct platform_device *pdev)
..	..	@@ -921,6 +1309,9 @@
921	1309	const struct rkcif_hw_match_data *data;
922	1310	struct resource *res;
923	1311	int i, ret, irq;
	1312	+ bool is_mem_reserved = false;
	1313	+ struct notifier_block *notifier;
	1314	+ int package = 0;
924	1315
925	1316	match = of_match_node(rkcif_plat_of_match, node);
926	1317	if (IS_ERR(match))
..	..	@@ -934,6 +1325,13 @@
934	1325	dev_set_drvdata(dev, cif_hw);
935	1326	cif_hw->dev = dev;
936	1327
	1328	+ package = rkcif_get_speciand_package_number(node);
	1329	+ if (package == 0x2) {
	1330	+ cif_hw->is_rk3588s2 = true;
	1331	+ dev_info(dev, "attach rk3588s2\n");
	1332	+ } else {
	1333	+ cif_hw->is_rk3588s2 = false;
	1334	+ }
937	1335	irq = platform_get_irq(pdev, 0);
938	1336	if (irq < 0)
939	1337	return irq;
..	..	@@ -949,10 +1347,7 @@
949	1347	cif_hw->irq = irq;
950	1348	cif_hw->match_data = data;
951	1349	cif_hw->chip_id = data->chip_id;
952		- if (data->chip_id == CHIP_RK1808_CIF \|\|
953		- data->chip_id == CHIP_RV1126_CIF \|\|
954		- data->chip_id == CHIP_RV1126_CIF_LITE \|\|
955		- data->chip_id == CHIP_RK3568_CIF) {
	1350	+ if (data->chip_id >= CHIP_RK1808_CIF) {
956	1351	res = platform_get_resource_byname(pdev,
957	1352	IORESOURCE_MEM,
958	1353	"cif_regs");
..	..	@@ -972,6 +1367,11 @@
972	1367	cif_hw->base_addr = devm_ioremap_resource(dev, res);
973	1368	if (IS_ERR(cif_hw->base_addr))
974	1369	return PTR_ERR(cif_hw->base_addr);
	1370	+ }
	1371	+
	1372	+ if (of_property_read_bool(np, "rockchip,android-usb-camerahal-enable")) {
	1373	+ dev_info(dev, "config cif adapt to android usb camera hal!\n");
	1374	+ cif_hw->adapt_to_usbcamerahal = true;
975	1375	}
976	1376
977	1377	cif_hw->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
..	..	@@ -1003,25 +1403,32 @@
1003	1403	if (data->rsts[i])
1004	1404	rst = devm_reset_control_get(dev, data->rsts[i]);
1005	1405	if (IS_ERR(rst)) {
	1406	+ cif_hw->cif_rst[i] = NULL;
1006	1407	dev_err(dev, "failed to get %s\n", data->rsts[i]);
1007		- return PTR_ERR(rst);
	1408	+ } else {
	1409	+ cif_hw->cif_rst[i] = rst;
1008	1410	}
1009		- cif_hw->cif_rst[i] = rst;
1010	1411	}
1011	1412
1012	1413	cif_hw->cif_regs = data->cif_regs;
1013	1414
1014		- cif_hw->iommu_en = is_iommu_enable(dev);
1015		- if (!cif_hw->iommu_en) {
1016		- ret = of_reserved_mem_device_init(dev);
1017		- if (ret)
1018		- dev_info(dev, "No reserved memory region assign to CIF\n");
1019		- }
	1415	+ cif_hw->is_dma_sg_ops = true;
	1416	+ cif_hw->is_dma_contig = true;
	1417	+ mutex_init(&cif_hw->dev_lock);
	1418	+ spin_lock_init(&cif_hw->group_lock);
	1419	+ atomic_set(&cif_hw->power_cnt, 0);
1020	1420
1021		- if (data->chip_id != CHIP_RK1808_CIF &&
1022		- data->chip_id != CHIP_RV1126_CIF &&
1023		- data->chip_id != CHIP_RV1126_CIF_LITE &&
1024		- data->chip_id != CHIP_RK3568_CIF) {
	1421	+ cif_hw->iommu_en = is_iommu_enable(dev);
	1422	+ ret = of_reserved_mem_device_init(dev);
	1423	+ if (ret) {
	1424	+ is_mem_reserved = false;
	1425	+ dev_info(dev, "No reserved memory region assign to CIF\n");
	1426	+ }
	1427	+ if (cif_hw->iommu_en && !is_mem_reserved)
	1428	+ cif_hw->is_dma_contig = false;
	1429	+ cif_hw->mem_ops = &vb2_cma_sg_memops;
	1430	+
	1431	+ if (data->chip_id < CHIP_RK1808_CIF) {
1025	1432	cif_dev = devm_kzalloc(dev, sizeof(*cif_dev), GFP_KERNEL);
1026	1433	if (!cif_dev)
1027	1434	return -ENOMEM;
..	..	@@ -1036,19 +1443,20 @@
1036	1443	return ret;
1037	1444	}
1038	1445
1039		- rkcif_hw_soft_reset(cif_hw, true);
1040		-
1041	1446	mutex_init(&cif_hw->dev_lock);
1042	1447
1043	1448	pm_runtime_enable(&pdev->dev);
1044		- rkcif_init_reset_timer(cif_hw);
1045	1449
1046		- if (data->chip_id == CHIP_RK1808_CIF \|\|
1047		- data->chip_id == CHIP_RV1126_CIF \|\|
1048		- data->chip_id == CHIP_RK3568_CIF) {
	1450	+ if (data->chip_id >= CHIP_RK1808_CIF &&
	1451	+ data->chip_id != CHIP_RV1126_CIF_LITE) {
1049	1452	platform_driver_register(&rkcif_plat_drv);
1050	1453	platform_driver_register(&rkcif_subdev_driver);
1051	1454	}
	1455	+
	1456	+ notifier = &cif_hw->reset_notifier;
	1457	+ notifier->priority = 1;
	1458	+ notifier->notifier_call = rkcif_reset_notifier;
	1459	+ rkcif_csi2_register_notifier(notifier);
1052	1460
1053	1461	return 0;
1054	1462	}
..	..	@@ -1062,19 +1470,53 @@
1062	1470	rkcif_iommu_cleanup(cif_hw);
1063	1471
1064	1472	mutex_destroy(&cif_hw->dev_lock);
1065		- if (cif_hw->chip_id != CHIP_RK1808_CIF &&
1066		- cif_hw->chip_id != CHIP_RV1126_CIF &&
1067		- cif_hw->chip_id != CHIP_RV1126_CIF_LITE &&
1068		- cif_hw->chip_id != CHIP_RK3568_CIF)
	1473	+ if (cif_hw->chip_id < CHIP_RK1808_CIF)
1069	1474	rkcif_plat_uninit(cif_hw->cif_dev[0]);
1070		- del_timer_sync(&cif_hw->hw_timer.timer);
	1475	+
	1476	+ rkcif_csi2_unregister_notifier(&cif_hw->reset_notifier);
	1477	+
1071	1478	return 0;
	1479	+}
	1480	+
	1481	+static void rkcif_hw_shutdown(struct platform_device *pdev)
	1482	+{
	1483	+ struct rkcif_hw *cif_hw = platform_get_drvdata(pdev);
	1484	+ struct rkcif_device *cif_dev = NULL;
	1485	+ int i = 0;
	1486	+
	1487	+ if (pm_runtime_get_if_in_use(&pdev->dev) <= 0)
	1488	+ return;
	1489	+
	1490	+ if (cif_hw->chip_id == CHIP_RK3588_CIF \|\|
	1491	+ cif_hw->chip_id == CHIP_RV1106_CIF \|\|
	1492	+ cif_hw->chip_id == CHIP_RK3562_CIF) {
	1493	+ write_cif_reg(cif_hw->base_addr, 0, 0);
	1494	+ } else {
	1495	+ for (i = 0; i < cif_hw->dev_num; i++) {
	1496	+ cif_dev = cif_hw->cif_dev[i];
	1497	+ if (atomic_read(&cif_dev->pipe.stream_cnt)) {
	1498	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	1499	+ rkcif_write_register(cif_dev,
	1500	+ CIF_REG_MIPI_LVDS_CTRL,
	1501	+ 0);
	1502	+ else
	1503	+ rkcif_write_register(cif_dev,
	1504	+ CIF_REG_DVP_CTRL,
	1505	+ 0);
	1506	+ }
	1507	+ }
	1508	+ }
	1509	+ if (cif_hw->irq > 0)
	1510	+ disable_irq(cif_hw->irq);
	1511	+ pm_runtime_put(&pdev->dev);
1072	1512	}
1073	1513
1074	1514	static int __maybe_unused rkcif_runtime_suspend(struct device *dev)
1075	1515	{
1076	1516	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1077	1517
	1518	+ if (atomic_dec_return(&cif_hw->power_cnt))
	1519	+ return 0;
1078	1520	rkcif_disable_sys_clk(cif_hw);
1079	1521
1080	1522	return pinctrl_pm_select_sleep_state(dev);
..	..	@@ -1085,17 +1527,18 @@
1085	1527	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1086	1528	int ret;
1087	1529
	1530	+ if (atomic_inc_return(&cif_hw->power_cnt) > 1)
	1531	+ return 0;
1088	1532	ret = pinctrl_pm_select_default_state(dev);
1089	1533	if (ret < 0)
1090	1534	return ret;
1091	1535	rkcif_enable_sys_clk(cif_hw);
	1536	+ rkcif_hw_soft_reset(cif_hw, true);
1092	1537
1093	1538	return 0;
1094	1539	}
1095	1540
1096	1541	static const struct dev_pm_ops rkcif_plat_pm_ops = {
1097		- SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1098		- pm_runtime_force_resume)
1099	1542	SET_RUNTIME_PM_OPS(rkcif_runtime_suspend, rkcif_runtime_resume, NULL)
1100	1543	};
1101	1544
..	..	@@ -1107,15 +1550,17 @@
1107	1550	},
1108	1551	.probe = rkcif_plat_hw_probe,
1109	1552	.remove = rkcif_plat_remove,
	1553	+ .shutdown = rkcif_hw_shutdown,
1110	1554	};
1111	1555
1112		-static int __init rk_cif_plat_drv_init(void)
	1556	+int rk_cif_plat_drv_init(void)
1113	1557	{
1114	1558	int ret;
1115	1559
1116	1560	ret = platform_driver_register(&rkcif_hw_plat_drv);
1117	1561	if (ret)
1118	1562	return ret;
	1563	+ rkcif_csi2_hw_plat_drv_init();
1119	1564	return rkcif_csi2_plat_drv_init();
1120	1565	}
1121	1566
..	..	@@ -1123,9 +1568,16 @@
1123	1568	{
1124	1569	platform_driver_unregister(&rkcif_hw_plat_drv);
1125	1570	rkcif_csi2_plat_drv_exit();
	1571	+ rkcif_csi2_hw_plat_drv_exit();
1126	1572	}
1127	1573
	1574	+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
	1575	+subsys_initcall(rk_cif_plat_drv_init);
	1576	+#else
	1577	+#if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
1128	1578	module_init(rk_cif_plat_drv_init);
	1579	+#endif
	1580	+#endif
1129	1581	module_exit(rk_cif_plat_drv_exit);
1130	1582
1131	1583	MODULE_AUTHOR("Rockchip Camera/ISP team");