~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,12 +4,18 @@
4	4	* Author: Andy Yan <andy.yan@rock-chips.com>
5	5	*/
6	6	#include <drm/drm.h>
7		-#include <drm/drmP.h>
8	7	#include <drm/drm_atomic.h>
	8	+#include <drm/drm_atomic_uapi.h>
9	9	#include <drm/drm_crtc.h>
10	10	#include <drm/drm_crtc_helper.h>
	11	+#include <drm/drm_debugfs.h>
11	12	#include <drm/drm_flip_work.h>
	13	+#include <drm/drm_fourcc.h>
	14	+#include <drm/drm_gem_framebuffer_helper.h>
12	15	#include <drm/drm_plane_helper.h>
	16	+#include <drm/drm_probe_helper.h>
	17	+#include <drm/drm_self_refresh_helper.h>
	18	+
13	19	#include <drm/drm_writeback.h>
14	20	#ifdef CONFIG_DRM_ANALOGIX_DP
15	21	#include <drm/bridge/analogix_dp.h>
..	..	@@ -23,6 +29,8 @@
23	29	#include <linux/module.h>
24	30	#include <linux/platform_device.h>
25	31	#include <linux/clk.h>
	32	+#include <linux/clk-provider.h>
	33	+#include <linux/clk/clk-conf.h>
26	34	#include <linux/iopoll.h>
27	35	#include <linux/of.h>
28	36	#include <linux/of_device.h>
..	..	@@ -30,23 +38,27 @@
30	38	#include <linux/pm_runtime.h>
31	39	#include <linux/component.h>
32	40	#include <linux/regmap.h>
	41	+#include <linux/reset.h>
33	42	#include <linux/mfd/syscon.h>
34	43	#include <linux/delay.h>
35	44	#include <linux/swab.h>
36	45	#include <linux/sort.h>
37	46	#include <linux/rockchip/cpu.h>
	47	+#include <linux/workqueue.h>
	48	+#include <linux/types.h>
38	49	#include <soc/rockchip/rockchip_dmc.h>
39	50	#include <soc/rockchip/rockchip-system-status.h>
40	51	#include <uapi/linux/videodev2.h>
41	52
	53	+#include "../drm_crtc_internal.h"
42	54	#include "../drm_internal.h"
43	55
44	56	#include "rockchip_drm_drv.h"
45	57	#include "rockchip_drm_gem.h"
46	58	#include "rockchip_drm_fb.h"
47		-#include "rockchip_drm_psr.h"
48	59	#include "rockchip_drm_vop.h"
49	60	#include "rockchip_vop_reg.h"
	61	+#include "rockchip_post_csc.h"
50	62
51	63	#define _REG_SET(vop2, name, off, reg, mask, v, relaxed) \
52	64	vop2_mask_write(vop2, off + reg.offset, mask, reg.shift, v, reg.write_mask, relaxed)
..	..	@@ -78,6 +90,8 @@
78	90
79	91	#define VOP_CTRL_SET(x, name, v) \
80	92	REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
	93	+
	94	+#define VOP_CTRL_GET(x, name) vop2_read_reg(x, 0, &(x)->data->ctrl->name)
81	95
82	96	#define VOP_INTR_GET(vop2, name) \
83	97	vop2_read_reg(vop2, 0, &vop2->data->ctrl->name)
..	..	@@ -112,27 +126,32 @@
112	126	#define VOP_WIN_GET(vop2, win, name) \
113	127	vop2_read_reg(vop2, win->offset, &VOP_WIN_NAME(win, name))
114	128
	129	+#define VOP_WIN_GET_REG_BAK(vop2, win, name) \
	130	+ vop2_read_reg_bak(vop2, win->offset, &VOP_WIN_NAME(win, name))
	131	+
115	132	#define VOP_WIN_NAME(win, name) \
116	133	(vop2_get_win_regs(win, &win->regs->name)->name)
117	134
118	135	#define VOP_WIN_TO_INDEX(vop2_win) \
119	136	((vop2_win) - (vop2_win)->vop2->win)
120	137
121		-#define VOP_GRF_SET(vop2, reg, v) \
	138	+#define VOP_GRF_SET(vop2, grf, reg, v) \
122	139	do { \
123		- if (vop2->data->grf_ctrl) { \
124		- vop2_grf_writel(vop2, vop2->data->grf_ctrl->reg, v); \
	140	+ if (vop2->data->grf) { \
	141	+ vop2_grf_writel(vop2->grf, vop2->data->grf->reg, v); \
125	142	} \
126	143	} while (0)
127	144
128		-#define to_vop2_video_port(c) container_of(c, struct vop2_video_port, crtc)
129	145	#define to_vop2_win(x) container_of(x, struct vop2_win, base)
130	146	#define to_vop2_plane_state(x) container_of(x, struct vop2_plane_state, base)
131	147	#define to_wb_state(x) container_of(x, struct vop2_wb_connector_state, base)
132		-
133		-#ifndef drm_is_afbc
134		-#define drm_is_afbc(modifier) (((modifier) >> 56) == DRM_FORMAT_MOD_VENDOR_ARM)
135		-#endif
	148	+#define output_if_is_hdmi(x) (x & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1))
	149	+#define output_if_is_dp(x) (x & (VOP_OUTPUT_IF_DP0 \| VOP_OUTPUT_IF_DP1))
	150	+#define output_if_is_edp(x) (x & (VOP_OUTPUT_IF_eDP0 \| VOP_OUTPUT_IF_eDP1))
	151	+#define output_if_is_mipi(x) (x & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_MIPI1))
	152	+#define output_if_is_lvds(x) (x & (VOP_OUTPUT_IF_LVDS0 \| VOP_OUTPUT_IF_LVDS1))
	153	+#define output_if_is_dpi(x) (x & (VOP_OUTPUT_IF_BT656 \| VOP_OUTPUT_IF_BT1120 \| \
	154	+ VOP_OUTPUT_IF_RGB))
136	155
137	156	/*
138	157	* max two jobs a time, one is running(writing back),
..	..	@@ -141,7 +160,11 @@
141	160	#define VOP2_WB_JOB_MAX 2
142	161	#define VOP2_SYS_AXI_BUS_NUM 2
143	162
144		-#define VOP2_CLUSTER_YUV444_10 0x12
	163	+#define VOP2_MAX_VP_OUTPUT_WIDTH 4096
	164	+/* KHZ */
	165	+#define VOP2_MAX_DCLK_RATE 600000
	166	+/* KHZ */
	167	+#define VOP2_COMMON_ACLK_RATE 500000
145	168
146	169	enum vop2_data_format {
147	170	VOP2_FMT_ARGB8888 = 0,
..	..	@@ -233,6 +256,36 @@
233	256	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
234	257	};
235	258
	259	+struct vop2_power_domain {
	260	+ struct vop2_power_domain *parent;
	261	+ struct vop2 *vop2;
	262	+ /*
	263	+ * @lock: protect power up/down procedure.
	264	+ * power on take effect immediately,
	265	+ * power down take effect by vsync.
	266	+ * we must check power_domain_status register
	267	+ * to make sure the power domain is down before
	268	+ * send a power on request.
	269	+ *
	270	+ */
	271	+ spinlock_t lock;
	272	+ unsigned int ref_count;
	273	+ bool on;
	274	+ /* @vp_mask: Bit mask of video port of the power domain's
	275	+ * module attached to.
	276	+ * For example: PD_CLUSTER0 belongs to module Cluster0, it's
	277	+ * bitmask is the VP which Cluster0 attached to. PD_ESMART is
	278	+ * shared between Esmart1/2/3, it's bitmask will be all the VP
	279	+ * which Esmart1/2/3 attached to.
	280	+ * This is used to check if we can power off a PD by vsync.
	281	+ */
	282	+ uint8_t vp_mask;
	283	+
	284	+ const struct vop2_power_domain_data *data;
	285	+ struct list_head list;
	286	+ struct delayed_work power_off_work;
	287	+};
	288	+
236	289	struct vop2_zpos {
237	290	struct drm_plane *plane;
238	291	int win_phys_id;
..	..	@@ -316,7 +369,6 @@
316	369	int global_alpha;
317	370	int blend_mode;
318	371	uint64_t color_key;
319		- void *yrgb_kvaddr;
320	372	unsigned long offset;
321	373	int pdaf_data_type;
322	374	bool async_commit;
..	..	@@ -338,11 +390,37 @@
338	390	bool two_win_mode;
339	391
340	392	/**
	393	+ * ---------------------------
	394	+ * \| \| \|
	395	+ * \| Left \| Right \|
	396	+ * \| \| \|
	397	+ * \| Cluster0 \| Cluster1 \|
	398	+ * ---------------------------
	399	+ */
	400	+
	401	+ /*
	402	+ * @splice_mode_right: As right part of the screen in splice mode.
	403	+ */
	404	+ bool splice_mode_right;
	405	+
	406	+ /**
	407	+ * @splice_win: splice win which used to splice for a plane
	408	+ * hdisplay > 4096
	409	+ */
	410	+ struct vop2_win *splice_win;
	411	+ struct vop2_win *left_win;
	412	+
	413	+ uint8_t splice_win_id;
	414	+
	415	+ struct vop2_power_domain *pd;
	416	+
	417	+ /**
341	418	* @phys_id: physical id for cluster0/1, esmart0/1, smart0/1
342	419	* Will be used as a identification for some register
343	420	* configuration such as OVL_LAYER_SEL/OVL_PORT_SEL.
344	421	*/
345	422	uint8_t phys_id;
	423	+
346	424	/**
347	425	* @win_id: graphic window id, a cluster maybe split into two
348	426	* graphics windows.
..	..	@@ -410,6 +488,7 @@
410	488	};
411	489
412	490	struct vop2_cluster {
	491	+ bool splice_mode;
413	492	struct vop2_win *main;
414	493	struct vop2_win *sub;
415	494	};
..	..	@@ -451,6 +530,17 @@
451	530
452	531	};
453	532
	533	+struct vop2_dsc {
	534	+ uint8_t id;
	535	+ uint8_t max_slice_num;
	536	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	537	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	538	+ bool enabled;
	539	+ char attach_vp_id;
	540	+ const struct vop2_dsc_regs *regs;
	541	+ struct vop2_power_domain *pd;
	542	+};
	543	+
454	544	enum vop2_wb_format {
455	545	VOP2_WB_ARGB8888,
456	546	VOP2_WB_BGR888,
..	..	@@ -471,12 +561,17 @@
471	561	};
472	562
473	563	struct vop2_video_port {
474		- struct drm_crtc crtc;
	564	+ struct rockchip_crtc rockchip_crtc;
	565	+ struct rockchip_mcu_timing mcu_timing;
475	566	struct vop2 *vop2;
	567	+ struct reset_control *dclk_rst;
476	568	struct clk *dclk;
	569	+ struct clk *dclk_parent;
477	570	uint8_t id;
478	571	bool layer_sel_update;
479	572	bool xmirror_en;
	573	+ bool need_reset_p2i_flag;
	574	+ atomic_t post_buf_empty_flag;
480	575	const struct vop2_video_port_regs *regs;
481	576
482	577	struct completion dsp_hold_completion;
..	..	@@ -524,15 +619,46 @@
524	619	int hdr_en;
525	620
526	621	/**
	622	+ * -----------------
	623	+ * \| \| \|
	624	+ * \| Left \| Right \|
	625	+ * \| \| \|
	626	+ * \| VP0 \| VP1 \|
	627	+ * -----------------
	628	+ * @splice_mode_right: As right part of the screen in splice mode.
	629	+ */
	630	+ bool splice_mode_right;
	631	+
	632	+ /**
	633	+ * @hdr10_at_splice_mode: enable hdr10 at splice mode on rk3588.
	634	+ */
	635	+ bool hdr10_at_splice_mode;
	636	+ /**
	637	+ * @left_vp: VP as left part of the screen in splice mode.
	638	+ */
	639	+ struct vop2_video_port *left_vp;
	640	+
	641	+ /**
527	642	* @win_mask: Bitmask of wins attached to the video port;
528	643	*/
529	644	uint32_t win_mask;
	645	+ /**
	646	+ * @enabled_win_mask: Bitmask of enabled wins attached to the video port;
	647	+ */
	648	+ uint32_t enabled_win_mask;
	649	+
530	650	/**
531	651	* @nr_layers: active layers attached to the video port;
532	652	*/
533	653	uint8_t nr_layers;
534	654
535	655	int cursor_win_id;
	656	+ /**
	657	+ * @output_if: output connector attached to the video port,
	658	+ * this flag is maintained in vop driver, updated in crtc_atomic_enable,
	659	+ * cleared in crtc_atomic_disable;
	660	+ */
	661	+ u32 output_if;
536	662
537	663	/**
538	664	* @active_tv_state: TV connector related states
..	..	@@ -555,6 +681,11 @@
555	681	bool gamma_lut_active;
556	682
557	683	/**
	684	+ * @lut_dma_rid: lut dma id
	685	+ */
	686	+ u16 lut_dma_rid;
	687	+
	688	+ /**
558	689	* @gamma_lut: atomic gamma look up table
559	690	*/
560	691	struct drm_color_lut *gamma_lut;
..	..	@@ -568,6 +699,11 @@
568	699	* @cubic_lut_gem_obj: gem obj to store cubic lut
569	700	*/
570	701	struct rockchip_gem_object *cubic_lut_gem_obj;
	702	+
	703	+ /**
	704	+ * @hdr_lut_gem_obj: gem obj to store hdr lut
	705	+ */
	706	+ struct rockchip_gem_object *hdr_lut_gem_obj;
571	707
572	708	/**
573	709	* @cubic_lut: cubic look up table
..	..	@@ -589,27 +725,81 @@
589	725	* @plane_mask_prop: plane mask interaction with userspace
590	726	*/
591	727	struct drm_property *plane_mask_prop;
	728	+ /**
	729	+ * @feature_prop: crtc feature interaction with userspace
	730	+ */
	731	+ struct drm_property *feature_prop;
	732	+
	733	+ /**
	734	+ * @variable_refresh_rate_prop: crtc variable refresh rate interaction with userspace
	735	+ */
	736	+ struct drm_property *variable_refresh_rate_prop;
	737	+
	738	+ /**
	739	+ * @max_refresh_rate_prop: crtc max refresh rate interaction with userspace
	740	+ */
	741	+ struct drm_property *max_refresh_rate_prop;
	742	+
	743	+ /**
	744	+ * @min_refresh_rate_prop: crtc min refresh rate interaction with userspace
	745	+ */
	746	+ struct drm_property *min_refresh_rate_prop;
	747	+
	748	+ /**
	749	+ * @hdr_ext_data_prop: hdr extend data interaction with userspace
	750	+ */
	751	+ struct drm_property *hdr_ext_data_prop;
	752	+
	753	+ int hdrvivid_mode;
	754	+
	755	+ /**
	756	+ * @acm_lut_data_prop: acm lut data interaction with userspace
	757	+ */
	758	+ struct drm_property *acm_lut_data_prop;
	759	+ /**
	760	+ * @post_csc_data_prop: post csc data interaction with userspace
	761	+ */
	762	+ struct drm_property *post_csc_data_prop;
	763	+ /**
	764	+ * @output_width_prop: vp max output width prop
	765	+ */
	766	+ struct drm_property *output_width_prop;
	767	+ /**
	768	+ * @output_dclk_prop: vp max output dclk prop
	769	+ */
	770	+ struct drm_property *output_dclk_prop;
592	771
593	772	/**
594	773	* @primary_plane_phy_id: vp primary plane phy id, the primary plane
595	774	* will be used to show uboot logo and kernel logo
596	775	*/
597	776	enum vop2_layer_phy_id primary_plane_phy_id;
	777	+
	778	+ struct post_acm acm_info;
	779	+ struct post_csc csc_info;
	780	+
	781	+ /**
	782	+ * @refresh_rate_change: indicate whether refresh rate change
	783	+ */
	784	+ bool refresh_rate_change;
	785	+};
	786	+
	787	+struct vop2_extend_pll {
	788	+ struct list_head list;
	789	+ struct clk *clk;
	790	+ char clk_name[32];
	791	+ u32 vp_mask;
598	792	};
599	793
600	794	struct vop2 {
601	795	u32 version;
602	796	struct device *dev;
603	797	struct drm_device *drm_dev;
	798	+ struct vop2_dsc dscs[ROCKCHIP_MAX_CRTC];
604	799	struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
605	800	struct vop2_wb wb;
606	801	struct dentry *debugfs;
607	802	struct drm_info_list *debugfs_files;
608		- struct drm_property *soc_id_prop;
609		- struct drm_property *vp_id_prop;
610		- struct drm_property *aclk_prop;
611		- struct drm_property *bg_prop;
612		- struct drm_property *line_flag_prop;
613	803	struct drm_prop_enum_list *plane_name_list;
614	804	bool is_iommu_enabled;
615	805	bool is_iommu_needed;
..	..	@@ -645,6 +835,9 @@
645	835
646	836	bool loader_protect;
647	837
	838	+ bool aclk_rate_reset;
	839	+ unsigned long aclk_rate;
	840	+
648	841	const struct vop2_data *data;
649	842	/* Number of win that registered as plane,
650	843	* maybe less than the total number of hardware
..	..	@@ -652,6 +845,7 @@
652	845	*/
653	846	uint32_t registered_num_wins;
654	847	uint8_t used_mixers;
	848	+ uint8_t esmart_lb_mode;
655	849	/**
656	850	* @active_vp_mask: Bitmask of active video ports;
657	851	*/
..	..	@@ -662,6 +856,10 @@
662	856	struct resource *res;
663	857	void __iomem *regs;
664	858	struct regmap *grf;
	859	+ struct regmap *sys_grf;
	860	+ struct regmap *vo0_grf;
	861	+ struct regmap *vo1_grf;
	862	+ struct regmap *sys_pmu;
665	863
666	864	/* physical map length of vop2 register */
667	865	uint32_t len;
..	..	@@ -684,11 +882,34 @@
684	882	unsigned int enable_count;
685	883	struct clk *hclk;
686	884	struct clk *aclk;
	885	+ struct clk *pclk;
	886	+ struct reset_control *ahb_rst;
	887	+ struct reset_control *axi_rst;
	888	+
	889	+ /* list_head of extend clk */
	890	+ struct list_head extend_clk_list_head;
	891	+ /* list_head of internal clk */
	892	+ struct list_head clk_list_head;
	893	+ struct list_head pd_list_head;
	894	+ struct work_struct post_buf_empty_work;
	895	+ struct workqueue_struct *workqueue;
687	896
688	897	struct vop2_layer layers[ROCKCHIP_MAX_LAYER];
689	898	/* must put at the end of the struct */
690	899	struct vop2_win win[];
691	900	};
	901	+
	902	+struct vop2_clk {
	903	+ struct vop2 *vop2;
	904	+ struct list_head list;
	905	+ unsigned long rate;
	906	+ struct clk_hw hw;
	907	+ struct clk_divider div;
	908	+ int div_val;
	909	+ u8 parent_index;
	910	+};
	911	+
	912	+#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw)
692	913
693	914	/*
694	915	* bus-format types.
..	..	@@ -704,22 +925,32 @@
704	925	{ MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
705	926	{ MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" },
706	927	{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
707		- { MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA, "RGB666_1X7X3_JEIDA" },
708	928	{ MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" },
709	929	{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
710	930	{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
711	931	{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
712		- { MEDIA_BUS_FMT_SRGB888_3X8, "SRGB888_3X8" },
713		- { MEDIA_BUS_FMT_SRGB888_DUMMY_4X8, "SRGB888_DUMMY_4X8" },
	932	+ { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
	933	+ { MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
714	934	{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
715	935	{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
716	936	{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
717	937	{ MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" },
718	938	{ MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" },
719	939	{ MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" },
	940	+ { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" },
	941	+ { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" },
720	942	};
721	943
722	944	static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list)
	945	+
	946	+static inline struct vop2_video_port to_vop2_video_port(struct drm_crtc crtc)
	947	+{
	948	+ struct rockchip_crtc *rockchip_crtc;
	949	+
	950	+ rockchip_crtc = container_of(crtc, struct rockchip_crtc, crtc);
	951	+
	952	+ return container_of(rockchip_crtc, struct vop2_video_port, rockchip_crtc);
	953	+}
723	954
724	955	static void vop2_lock(struct vop2 *vop2)
725	956	{
..	..	@@ -733,17 +964,26 @@
733	964	mutex_unlock(&vop2->vop2_lock);
734	965	}
735	966
736		-static inline void vop2_grf_writel(struct vop2 *vop2, struct vop_reg reg, u32 v)
	967	+static inline void vop2_grf_writel(struct regmap *regmap, struct vop_reg reg, u32 v)
737	968	{
738	969	u32 val = 0;
739	970
740		- if (IS_ERR_OR_NULL(vop2->grf))
	971	+ if (IS_ERR_OR_NULL(regmap))
741	972	return;
742	973
743	974	if (reg.mask) {
744	975	val = (v << reg.shift) \| (reg.mask << (reg.shift + 16));
745		- regmap_write(vop2->grf, reg.offset, val);
	976	+ regmap_write(regmap, reg.offset, val);
746	977	}
	978	+}
	979	+
	980	+static inline uint32_t vop2_grf_readl(struct regmap regmap, const struct vop_reg reg)
	981	+{
	982	+ uint32_t v;
	983	+
	984	+ regmap_read(regmap, reg->offset, &v);
	985	+
	986	+ return v;
747	987	}
748	988
749	989	static inline void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -761,6 +1001,26 @@
761	1001	const struct vop_reg *reg)
762	1002	{
763	1003	return (vop2_readl(vop2, base + reg->offset) >> reg->shift) & reg->mask;
	1004	+}
	1005	+
	1006	+static inline uint32_t vop2_read_reg_bak(struct vop2 *vop2, uint32_t base,
	1007	+ const struct vop_reg *reg)
	1008	+{
	1009	+ return (vop2->regsbak[(base + reg->offset) >> 2] >> reg->shift) & reg->mask;
	1010	+}
	1011	+
	1012	+static inline uint32_t vop2_read_grf_reg(struct regmap regmap, const struct vop_reg reg)
	1013	+{
	1014	+ return (vop2_grf_readl(regmap, reg) >> reg->shift) & reg->mask;
	1015	+}
	1016	+
	1017	+static inline void vop2_write_reg_uncached(struct vop2 vop2, const struct vop_reg reg, uint32_t v)
	1018	+{
	1019	+ uint32_t offset = reg->offset;
	1020	+ uint32_t cached_val = vop2->regsbak[offset >> 2];
	1021	+
	1022	+ v = (cached_val & ~(reg->mask << reg->shift)) \| ((v & reg->mask) << reg->shift);
	1023	+ writel(v, vop2->regs + offset);
764	1024	}
765	1025
766	1026	static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
..	..	@@ -841,7 +1101,7 @@
841	1101	}
842	1102	}
843	1103
844		-void vop2_standby(struct drm_crtc *crtc, bool standby)
	1104	+static void vop2_crtc_standby(struct drm_crtc *crtc, bool standby)
845	1105	{
846	1106	struct vop2_video_port *vp = to_vop2_video_port(crtc);
847	1107	struct vop2 *vop2 = vp->vop2;
..	..	@@ -853,7 +1113,6 @@
853	1113	VOP_MODULE_SET(vop2, vp, standby, 0);
854	1114	}
855	1115	}
856		-EXPORT_SYMBOL(vop2_standby);
857	1116
858	1117	static inline const struct vop2_win_regs vop2_get_win_regs(struct vop2_win win,
859	1118	const struct vop_reg *reg)
..	..	@@ -899,6 +1158,32 @@
899	1158	return NULL;
900	1159	}
901	1160
	1161	+static struct vop2_power_domain vop2_find_pd_by_id(struct vop2 vop2, uint8_t id)
	1162	+{
	1163	+ struct vop2_power_domain pd, n;
	1164	+
	1165	+ list_for_each_entry_safe(pd, n, &vop2->pd_list_head, list) {
	1166	+ if (pd->data->id == id)
	1167	+ return pd;
	1168	+ }
	1169	+
	1170	+ return NULL;
	1171	+}
	1172	+
	1173	+static const struct vop2_connector_if_data vop2_find_connector_if_data(struct vop2 vop2, int id)
	1174	+{
	1175	+ const struct vop2_connector_if_data *if_data;
	1176	+ int i;
	1177	+
	1178	+ for (i = 0; i < vop2->data->nr_conns; i++) {
	1179	+ if_data = &vop2->data->conn[i];
	1180	+ if (if_data->id == id)
	1181	+ return if_data;
	1182	+ }
	1183	+
	1184	+ return NULL;
	1185	+}
	1186	+
902	1187	static struct drm_crtc vop2_find_crtc_by_plane_mask(struct vop2 vop2, uint8_t phys_id)
903	1188	{
904	1189	struct vop2_video_port *vp;
..	..	@@ -907,10 +1192,28 @@
907	1192	for (i = 0; i < vop2->data->nr_vps; i++) {
908	1193	vp = &vop2->vps[i];
909	1194	if (vp->plane_mask & BIT(phys_id))
910		- return &vp->crtc;
	1195	+ return &vp->rockchip_crtc.crtc;
911	1196	}
912	1197
913	1198	return NULL;
	1199	+}
	1200	+
	1201	+static int vop2_clk_reset(struct reset_control *rstc)
	1202	+{
	1203	+ int ret;
	1204	+
	1205	+ if (!rstc)
	1206	+ return 0;
	1207	+
	1208	+ ret = reset_control_assert(rstc);
	1209	+ if (ret < 0)
	1210	+ DRM_WARN("failed to assert reset\n");
	1211	+ udelay(10);
	1212	+ ret = reset_control_deassert(rstc);
	1213	+ if (ret < 0)
	1214	+ DRM_WARN("failed to deassert reset\n");
	1215	+
	1216	+ return ret;
914	1217	}
915	1218
916	1219	static void vop2_load_hdr2sdr_table(struct vop2_video_port *vp)
..	..	@@ -991,8 +1294,23 @@
991	1294	static uint32_t vop2_read_vcnt(struct vop2_video_port *vp)
992	1295	{
993	1296	uint32_t offset = RK3568_SYS_STATUS0 + (vp->id << 2);
	1297	+ uint32_t vcnt0, vcnt1;
	1298	+ int i = 0;
994	1299
995		- return vop2_readl(vp->vop2, offset) >> 16;
	1300	+ for (i = 0; i < 10; i++) {
	1301	+ vcnt0 = vop2_readl(vp->vop2, offset) >> 16;
	1302	+ vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
	1303	+
	1304	+ if ((vcnt1 - vcnt0) <= 1)
	1305	+ break;
	1306	+ }
	1307	+
	1308	+ if (i == 10) {
	1309	+ DRM_DEV_ERROR(vp->vop2->dev, "read VP%d vcnt error: %d %d\n", vp->id, vcnt0, vcnt1);
	1310	+ vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
	1311	+ }
	1312	+
	1313	+ return vcnt1;
996	1314	}
997	1315
998	1316	static void vop2_wait_for_irq_handler(struct drm_crtc *crtc)
..	..	@@ -1112,7 +1430,7 @@
1112	1430	done_bits &= ~BIT(vp->id);
1113	1431	vp_id = ffs(done_bits) - 1;
1114	1432	done_vp = &vop2->vps[vp_id];
1115		- adjusted_mode = &done_vp->crtc.state->adjusted_mode;
	1433	+ adjusted_mode = &done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1116	1434	vcnt = vop2_read_vcnt(done_vp);
1117	1435	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1118	1436	vcnt >>= 1;
..	..	@@ -1133,7 +1451,7 @@
1133	1451
1134	1452	first_vp_id = ffs(done_bits) - 1;
1135	1453	first_done_vp = &vop2->vps[first_vp_id];
1136		- first_mode = &first_done_vp->crtc.state->adjusted_mode;
	1454	+ first_mode = &first_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1137	1455	/* set last 1/8 frame time as safe section */
1138	1456	vrefresh = drm_mode_vrefresh(first_mode);
1139	1457	if (!vrefresh) {
..	..	@@ -1145,7 +1463,7 @@
1145	1463	done_bits &= ~BIT(first_vp_id);
1146	1464	second_vp_id = ffs(done_bits) - 1;
1147	1465	second_done_vp = &vop2->vps[second_vp_id];
1148		- second_mode = &second_done_vp->crtc.state->adjusted_mode;
	1466	+ second_mode = &second_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1149	1467	/* set last 1/8 frame time as safe section */
1150	1468	vrefresh = drm_mode_vrefresh(second_mode);
1151	1469	if (!vrefresh) {
..	..	@@ -1190,6 +1508,26 @@
1190	1508	return done_bits;
1191	1509	}
1192	1510
	1511	+static inline void rk3588_vop2_dsc_cfg_done(struct drm_crtc *crtc)
	1512	+{
	1513	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1514	+ struct vop2 *vop2 = vp->vop2;
	1515	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1516	+ struct vop2_dsc *dsc = &vop2->dscs[vcstate->dsc_id];
	1517	+
	1518	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	1519	+ dsc = &vop2->dscs[0];
	1520	+ if (vcstate->dsc_enable)
	1521	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1522	+ dsc = &vop2->dscs[1];
	1523	+ if (vcstate->dsc_enable)
	1524	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1525	+ } else {
	1526	+ if (vcstate->dsc_enable)
	1527	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1528	+ }
	1529	+}
	1530	+
1193	1531	static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
1194	1532	{
1195	1533	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -1224,6 +1562,9 @@
1224	1562	* This is rather low probability for miss some done bit.
1225	1563	*/
1226	1564	val \|= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;
	1565	+
	1566	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
	1567	+
1227	1568	vop2_writel(vop2, 0, val);
1228	1569
1229	1570	/**
..	..	@@ -1240,10 +1581,16 @@
1240	1581	static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
1241	1582	{
1242	1583	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1584	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1585	+ const struct vop2_video_port_data *vp_data = &vp->vop2->data->vp[vp->id];
1243	1586	struct vop2 *vop2 = vp->vop2;
1244	1587	uint32_t val;
1245	1588
1246	1589	val = RK3568_VOP2_GLB_CFG_DONE_EN \| BIT(vp->id) \| (BIT(vp->id) << 16);
	1590	+ if (vcstate->splice_mode)
	1591	+ val \|= BIT(vp_data->splice_vp_id) \| (BIT(vp_data->splice_vp_id) << 16);
	1592	+
	1593	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
1247	1594
1248	1595	vop2_writel(vop2, 0, val);
1249	1596	}
..	..	@@ -1265,6 +1612,7 @@
1265	1612	} else {
1266	1613	vop2_writel(vop2, 0, val);
1267	1614	}
	1615	+
1268	1616	}
1269	1617
1270	1618	static inline void vop2_cfg_done(struct drm_crtc *crtc)
..	..	@@ -1276,6 +1624,178 @@
1276	1624	return rk3568_vop2_cfg_done(crtc);
1277	1625	else
1278	1626	return rk3588_vop2_cfg_done(crtc);
	1627	+}
	1628	+
	1629	+/*
	1630	+ * A PD can power off by vsync when it's module attached to
	1631	+ * a activated VP.
	1632	+ */
	1633	+static uint32_t vop2_power_domain_can_off_by_vsync(struct vop2_power_domain *pd)
	1634	+{
	1635	+ struct vop2 *vop2 = pd->vop2;
	1636	+
	1637	+ if (vop2->active_vp_mask & pd->vp_mask)
	1638	+ return true;
	1639	+ else
	1640	+ return false;
	1641	+}
	1642	+
	1643	+/*
	1644	+ * Read VOP internal power domain on/off status.
	1645	+ * We should query BISR_STS register in PMU for
	1646	+ * power up/down status when memory repair is enabled.
	1647	+ * Return value: 1 for power on, 0 for power off;
	1648	+ */
	1649	+static uint32_t vop2_power_domain_status(struct vop2_power_domain *pd)
	1650	+{
	1651	+ struct vop2 *vop2 = pd->vop2;
	1652	+
	1653	+ if (vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->bisr_en_status))
	1654	+ return vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->pmu_status);
	1655	+ else
	1656	+ return vop2_read_reg(vop2, 0, &pd->data->regs->status) ? 0 : 1;
	1657	+}
	1658	+
	1659	+static void vop2_wait_power_domain_off(struct vop2_power_domain *pd)
	1660	+{
	1661	+ struct vop2 *vop2 = pd->vop2;
	1662	+ int val;
	1663	+ int ret;
	1664	+
	1665	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, !val, 0, 50 * 1000);
	1666	+
	1667	+ if (ret)
	1668	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d off timeout power_ctrl: 0x%x\n",
	1669	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1670	+}
	1671	+
	1672	+static void vop2_wait_power_domain_on(struct vop2_power_domain *pd)
	1673	+{
	1674	+ struct vop2 *vop2 = pd->vop2;
	1675	+ int val;
	1676	+ int ret;
	1677	+
	1678	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, val, 0, 50 * 1000);
	1679	+ if (ret)
	1680	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d on timeout power_ctrl: 0x%x\n",
	1681	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1682	+}
	1683	+
	1684	+/*
	1685	+ * Power domain on take effect immediately
	1686	+ */
	1687	+static void vop2_power_domain_on(struct vop2_power_domain *pd)
	1688	+{
	1689	+ struct vop2 *vop2 = pd->vop2;
	1690	+
	1691	+ if (!pd->on) {
	1692	+ dev_dbg(vop2->dev, "pd%d on\n", ffs(pd->data->id) - 1);
	1693	+ vop2_wait_power_domain_off(pd);
	1694	+ VOP_MODULE_SET(vop2, pd->data, pd, 0);
	1695	+ vop2_wait_power_domain_on(pd);
	1696	+ pd->on = true;
	1697	+ }
	1698	+}
	1699	+
	1700	+/*
	1701	+ * Power domain off take effect by vsync.
	1702	+ */
	1703	+static void vop2_power_domain_off(struct vop2_power_domain *pd)
	1704	+{
	1705	+ struct vop2 *vop2 = pd->vop2;
	1706	+
	1707	+ dev_dbg(vop2->dev, "pd%d off\n", ffs(pd->data->id) - 1);
	1708	+ pd->on = false;
	1709	+ VOP_MODULE_SET(vop2, pd->data, pd, 1);
	1710	+}
	1711	+
	1712	+static void vop2_power_domain_get(struct vop2_power_domain *pd)
	1713	+{
	1714	+ if (pd->parent)
	1715	+ vop2_power_domain_get(pd->parent);
	1716	+
	1717	+ spin_lock(&pd->lock);
	1718	+ if (pd->ref_count == 0) {
	1719	+ if (pd->vop2->data->delayed_pd)
	1720	+ cancel_delayed_work(&pd->power_off_work);
	1721	+ vop2_power_domain_on(pd);
	1722	+ }
	1723	+ pd->ref_count++;
	1724	+ spin_unlock(&pd->lock);
	1725	+}
	1726	+
	1727	+static void vop2_power_domain_put(struct vop2_power_domain *pd)
	1728	+{
	1729	+ spin_lock(&pd->lock);
	1730	+
	1731	+ /*
	1732	+ * For a nested power domain(PD_Cluster0 is the parent of PD_CLuster1/2/3)
	1733	+ * the parent power domain must be enabled before child power domain
	1734	+ * is on.
	1735	+ *
	1736	+ * So we may met this condition: Cluster0 is not on a activated VP,
	1737	+ * but PD_Cluster0 must enabled as one of the child PD_CLUSTER1/2/3 is enabled.
	1738	+ * when all child PD is disabled, we want disable the parent
	1739	+ * PD(PD_CLUSTER0), but as module CLUSTER0 is not attcthed on a activated VP,
	1740	+ * the turn off operation(which is take effect by vsync) will never take effect.
	1741	+ * so we will see a "wait pd0 off timeout" log when we turn on PD_CLUSTER0 next time.
	1742	+ *
	1743	+ * So we have a check here
	1744	+ */
	1745	+ if (--pd->ref_count == 0 && vop2_power_domain_can_off_by_vsync(pd)) {
	1746	+ if (pd->vop2->data->delayed_pd)
	1747	+ schedule_delayed_work(&pd->power_off_work, msecs_to_jiffies(2500));
	1748	+ else
	1749	+ vop2_power_domain_off(pd);
	1750	+ }
	1751	+
	1752	+ spin_unlock(&pd->lock);
	1753	+ if (pd->parent)
	1754	+ vop2_power_domain_put(pd->parent);
	1755	+}
	1756	+
	1757	+/*
	1758	+ * Called if the pd ref_count reach 0 after 2.5
	1759	+ * seconds.
	1760	+ */
	1761	+static void vop2_power_domain_off_work(struct work_struct *work)
	1762	+{
	1763	+ struct vop2_power_domain *pd;
	1764	+
	1765	+ pd = container_of(to_delayed_work(work), struct vop2_power_domain, power_off_work);
	1766	+
	1767	+ spin_lock(&pd->lock);
	1768	+ if (pd->ref_count == 0)
	1769	+ vop2_power_domain_off(pd);
	1770	+ spin_unlock(&pd->lock);
	1771	+}
	1772	+
	1773	+static void vop2_win_enable(struct vop2_win *win)
	1774	+{
	1775	+ /*
	1776	+ * a win such as cursor update by async:
	1777	+ * first frame enable win pd, enable win, return without wait vsync
	1778	+ * second frame come, but the first frame may still not enabled
	1779	+ * in this case, the win pd is turn on by fist frame, so we don't
	1780	+ * need get pd again.
	1781	+ *
	1782	+ * another case:
	1783	+ * first frame: disable win, disable pd, return without wait vsync
	1784	+ * second frame come very soon, the previous win disable may still not
	1785	+ * take effect, but the pd is disable in progress, we should do pd_get
	1786	+ * at this situation.
	1787	+ *
	1788	+ * check the backup register for previous enable operation.
	1789	+ */
	1790	+ if (!VOP_WIN_GET_REG_BAK(win->vop2, win, enable)) {
	1791	+ if (win->pd) {
	1792	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1793	+ return;
	1794	+
	1795	+ vop2_power_domain_get(win->pd);
	1796	+ win->pd->vp_mask \|= win->vp_mask;
	1797	+ }
	1798	+ }
1279	1799	}
1280	1800
1281	1801	static void vop2_win_multi_area_disable(struct vop2_win *parent)
..	..	@@ -1291,31 +1811,63 @@
1291	1811	}
1292	1812	}
1293	1813
1294		-static void vop2_win_disable(struct vop2_win *win)
	1814	+static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
1295	1815	{
1296	1816	struct vop2 *vop2 = win->vop2;
1297	1817
1298		- VOP_WIN_SET(vop2, win, enable, 0);
1299		- if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
1300		- struct vop2_win *sub_win;
1301		- int i = 0;
1302		-
1303		- for (i = 0; i < vop2->registered_num_wins; i++) {
1304		- sub_win = &vop2->win[i];
1305		-
1306		- if ((sub_win->phys_id == win->phys_id) &&
1307		- (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
1308		- VOP_WIN_SET(vop2, sub_win, enable, 0);
1309		- }
1310		-
1311		- VOP_CLUSTER_SET(vop2, win, enable, 0);
	1818	+ /* Disable the right splice win */
	1819	+ if (win->splice_win && !skip_splice_win) {
	1820	+ vop2_win_disable(win->splice_win, false);
	1821	+ win->splice_win = NULL;
1312	1822	}
1313	1823
1314		- /*
1315		- * disable all other multi area win if we want disable area0 here
1316		- */
1317		- if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
1318		- vop2_win_multi_area_disable(win);
	1824	+ if (VOP_WIN_GET(vop2, win, enable) \|\| VOP_WIN_GET_REG_BAK(vop2, win, enable)) {
	1825	+ VOP_WIN_SET(vop2, win, enable, 0);
	1826	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
	1827	+ struct vop2_win *sub_win;
	1828	+ int i = 0;
	1829	+
	1830	+ for (i = 0; i < vop2->registered_num_wins; i++) {
	1831	+ sub_win = &vop2->win[i];
	1832	+
	1833	+ if ((sub_win->phys_id == win->phys_id) &&
	1834	+ (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
	1835	+ VOP_WIN_SET(vop2, sub_win, enable, 0);
	1836	+ }
	1837	+
	1838	+ VOP_CLUSTER_SET(vop2, win, enable, 0);
	1839	+ }
	1840	+
	1841	+ /*
	1842	+ * disable all other multi area win if we want disable area0 here
	1843	+ */
	1844	+ if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
	1845	+ vop2_win_multi_area_disable(win);
	1846	+
	1847	+ if (win->pd) {
	1848	+
	1849	+ /*
	1850	+ * Don't dynamic turn on/off PD_ESMART.
	1851	+ * (1) There is a design issue for PD_EMSART when attached
	1852	+ * on VP1/2/3, we found it will trigger POST_BUF_EMPTY irq at vp0
	1853	+ * in splice mode.
	1854	+ * (2) PD_ESMART will be closed at esmart layers attathed on VPs
	1855	+ * config done + FS, but different VP FS time is different, this
	1856	+ * maybe lead to PD_ESMART closed at wrong time and display error.
	1857	+ * (3) PD_ESMART power up maybe have 4 us delay, this will lead to POST_BUF_EMPTY.
	1858	+ */
	1859	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1860	+ return;
	1861	+
	1862	+ vop2_power_domain_put(win->pd);
	1863	+ win->pd->vp_mask &= ~win->vp_mask;
	1864	+ }
	1865	+ }
	1866	+
	1867	+ if (win->left_win && win->splice_mode_right) {
	1868	+ win->left_win = NULL;
	1869	+ win->splice_mode_right = false;
	1870	+ }
1319	1871	}
1320	1872
1321	1873	static inline void vop2_write_lut(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -1328,9 +1880,26 @@
1328	1880	return readl(vop2->lut_regs + offset);
1329	1881	}
1330	1882
	1883	+static bool is_linear_10bit_yuv(uint32_t format)
	1884	+{
	1885	+ switch (format) {
	1886	+ case DRM_FORMAT_NV15:
	1887	+ case DRM_FORMAT_NV20:
	1888	+ case DRM_FORMAT_NV30:
	1889	+ return true;
	1890	+ default:
	1891	+ return false;
	1892	+ }
	1893	+}
	1894	+
1331	1895	static enum vop2_data_format vop2_convert_format(uint32_t format)
1332	1896	{
1333	1897	switch (format) {
	1898	+ case DRM_FORMAT_XRGB2101010:
	1899	+ case DRM_FORMAT_ARGB2101010:
	1900	+ case DRM_FORMAT_XBGR2101010:
	1901	+ case DRM_FORMAT_ABGR2101010:
	1902	+ return VOP2_FMT_XRGB101010;
1334	1903	case DRM_FORMAT_XRGB8888:
1335	1904	case DRM_FORMAT_ARGB8888:
1336	1905	case DRM_FORMAT_XBGR8888:
..	..	@@ -1343,16 +1912,22 @@
1343	1912	case DRM_FORMAT_BGR565:
1344	1913	return VOP2_FMT_RGB565;
1345	1914	case DRM_FORMAT_NV12:
	1915	+ case DRM_FORMAT_NV21:
	1916	+ case DRM_FORMAT_YUV420_8BIT:
1346	1917	return VOP2_FMT_YUV420SP;
1347		- case DRM_FORMAT_NV12_10:
	1918	+ case DRM_FORMAT_NV15:
	1919	+ case DRM_FORMAT_YUV420_10BIT:
1348	1920	return VOP2_FMT_YUV420SP_10;
1349	1921	case DRM_FORMAT_NV16:
	1922	+ case DRM_FORMAT_NV61:
1350	1923	return VOP2_FMT_YUV422SP;
1351		- case DRM_FORMAT_NV16_10:
	1924	+ case DRM_FORMAT_NV20:
	1925	+ case DRM_FORMAT_Y210:
1352	1926	return VOP2_FMT_YUV422SP_10;
1353	1927	case DRM_FORMAT_NV24:
	1928	+ case DRM_FORMAT_NV42:
1354	1929	return VOP2_FMT_YUV444SP;
1355		- case DRM_FORMAT_NV24_10:
	1930	+ case DRM_FORMAT_NV30:
1356	1931	return VOP2_FMT_YUV444SP_10;
1357	1932	case DRM_FORMAT_YUYV:
1358	1933	case DRM_FORMAT_YVYU:
..	..	@@ -1369,6 +1944,11 @@
1369	1944	static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format)
1370	1945	{
1371	1946	switch (format) {
	1947	+ case DRM_FORMAT_XRGB2101010:
	1948	+ case DRM_FORMAT_ARGB2101010:
	1949	+ case DRM_FORMAT_XBGR2101010:
	1950	+ case DRM_FORMAT_ABGR2101010:
	1951	+ return VOP2_AFBC_FMT_ARGB2101010;
1372	1952	case DRM_FORMAT_XRGB8888:
1373	1953	case DRM_FORMAT_ARGB8888:
1374	1954	case DRM_FORMAT_XBGR8888:
..	..	@@ -1380,14 +1960,16 @@
1380	1960	case DRM_FORMAT_RGB565:
1381	1961	case DRM_FORMAT_BGR565:
1382	1962	return VOP2_AFBC_FMT_RGB565;
1383		- case DRM_FORMAT_NV12:
	1963	+ case DRM_FORMAT_YUV420_8BIT:
1384	1964	return VOP2_AFBC_FMT_YUV420;
1385		- case DRM_FORMAT_NV12_10:
	1965	+ case DRM_FORMAT_YUV420_10BIT:
1386	1966	return VOP2_AFBC_FMT_YUV420_10BIT;
1387		- case DRM_FORMAT_NV16:
	1967	+ case DRM_FORMAT_YVYU:
1388	1968	case DRM_FORMAT_YUYV:
	1969	+ case DRM_FORMAT_VYUY:
	1970	+ case DRM_FORMAT_UYVY:
1389	1971	return VOP2_AFBC_FMT_YUV422;
1390		- case DRM_FORMAT_NV16_10:
	1972	+ case DRM_FORMAT_Y210:
1391	1973	return VOP2_AFBC_FMT_YUV422_10BIT;
1392	1974
1393	1975	/* either of the below should not be reachable */
..	..	@@ -1411,11 +1993,11 @@
1411	1993	case DRM_FORMAT_NV24:
1412	1994	case DRM_FORMAT_NV42:
1413	1995	return VOP2_TILED_8X8_FMT_YUV444SP;
1414		- case DRM_FORMAT_NV12_10:
	1996	+ case DRM_FORMAT_NV15:
1415	1997	return VOP2_TILED_8X8_FMT_YUV420SP_10;
1416		- case DRM_FORMAT_NV16_10:
	1998	+ case DRM_FORMAT_NV20:
1417	1999	return VOP2_TILED_8X8_FMT_YUV422SP_10;
1418		- case DRM_FORMAT_NV24_10:
	2000	+ case DRM_FORMAT_NV30:
1419	2001	return VOP2_TILED_8X8_FMT_YUV444SP_10;
1420	2002	default:
1421	2003	DRM_WARN_ONCE("unsupported tiled format[%08x]\n", format);
..	..	@@ -1440,13 +2022,13 @@
1440	2022	case DRM_FORMAT_NV42:
1441	2023	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1442	2024	VOP3_TILED_8X8_FMT_YUV444SP : VOP3_TILED_4X4_FMT_YUV444SP;
1443		- case DRM_FORMAT_NV12_10:
	2025	+ case DRM_FORMAT_NV15:
1444	2026	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1445	2027	VOP3_TILED_8X8_FMT_YUV420SP_10 : VOP3_TILED_4X4_FMT_YUV420SP_10;
1446		- case DRM_FORMAT_NV16_10:
	2028	+ case DRM_FORMAT_NV20:
1447	2029	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1448	2030	VOP3_TILED_8X8_FMT_YUV422SP_10 : VOP3_TILED_4X4_FMT_YUV422SP_10;
1449		- case DRM_FORMAT_NV24_10:
	2031	+ case DRM_FORMAT_NV30:
1450	2032	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1451	2033	VOP3_TILED_8X8_FMT_YUV444SP_10 : VOP3_TILED_4X4_FMT_YUV444SP_10;
1452	2034	default:
..	..	@@ -1485,6 +2067,8 @@
1485	2067	static bool vop2_win_rb_swap(uint32_t format)
1486	2068	{
1487	2069	switch (format) {
	2070	+ case DRM_FORMAT_XBGR2101010:
	2071	+ case DRM_FORMAT_ABGR2101010:
1488	2072	case DRM_FORMAT_XBGR8888:
1489	2073	case DRM_FORMAT_ABGR8888:
1490	2074	case DRM_FORMAT_BGR888:
..	..	@@ -1499,7 +2083,7 @@
1499	2083	{
1500	2084	switch (format) {
1501	2085	case DRM_FORMAT_NV24:
1502		- case DRM_FORMAT_NV24_10:
	2086	+ case DRM_FORMAT_NV30:
1503	2087	return true;
1504	2088	default:
1505	2089	return false;
..	..	@@ -1512,8 +2096,9 @@
1512	2096	case DRM_FORMAT_NV12:
1513	2097	case DRM_FORMAT_NV16:
1514	2098	case DRM_FORMAT_YUYV:
1515		- case DRM_FORMAT_NV12_10:
1516		- case DRM_FORMAT_NV16_10:
	2099	+ case DRM_FORMAT_Y210:
	2100	+ case DRM_FORMAT_YUV420_8BIT:
	2101	+ case DRM_FORMAT_YUV420_10BIT:
1517	2102	return true;
1518	2103	default:
1519	2104	return false;
..	..	@@ -1526,9 +2111,9 @@
1526	2111	case DRM_FORMAT_NV12:
1527	2112	case DRM_FORMAT_NV16:
1528	2113	case DRM_FORMAT_NV24:
1529		- case DRM_FORMAT_NV12_10:
1530		- case DRM_FORMAT_NV16_10:
1531		- case DRM_FORMAT_NV24_10:
	2114	+ case DRM_FORMAT_NV15:
	2115	+ case DRM_FORMAT_NV20:
	2116	+ case DRM_FORMAT_NV30:
1532	2117	case DRM_FORMAT_YUYV:
1533	2118	case DRM_FORMAT_UYVY:
1534	2119	return true;
..	..	@@ -1572,6 +2157,19 @@
1572	2157	return false;
1573	2158	}
1574	2159
	2160	+static bool vop3_output_rb_swap(uint32_t bus_format, uint32_t output_mode)
	2161	+{
	2162	+ /*
	2163	+ * The default component order of serial rgb3x8 formats
	2164	+ * is BGR. So it is needed to enable RB swap.
	2165	+ */
	2166	+ if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 \|\|
	2167	+ bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
	2168	+ return true;
	2169	+ else
	2170	+ return false;
	2171	+}
	2172	+
1575	2173	static bool vop2_output_yc_swap(uint32_t bus_format)
1576	2174	{
1577	2175	switch (bus_format) {
..	..	@@ -1590,6 +2188,7 @@
1590	2188	switch (bus_format) {
1591	2189	case MEDIA_BUS_FMT_YUV8_1X24:
1592	2190	case MEDIA_BUS_FMT_YUV10_1X30:
	2191	+ case MEDIA_BUS_FMT_YUYV10_1X20:
1593	2192	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1594	2193	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1595	2194	case MEDIA_BUS_FMT_YUYV8_2X8:
..	..	@@ -1685,6 +2284,15 @@
1685	2284	return (win->feature & WIN_FEATURE_CLUSTER_SUB);
1686	2285	}
1687	2286
	2287	+static inline bool vop2_has_feature(struct vop2 *vop2, uint64_t feature)
	2288	+{
	2289	+ return (vop2->data->feature & feature);
	2290	+}
	2291	+
	2292	+/*
	2293	+ * 0: Full mode, 16 lines for one tail
	2294	+ * 1: half block mode
	2295	+ */
1688	2296	static int vop2_afbc_half_block_enable(struct vop2_plane_state *vpstate)
1689	2297	{
1690	2298	if (vpstate->rotate_270_en \|\| vpstate->rotate_90_en)
..	..	@@ -1693,11 +2301,15 @@
1693	2301	return 1;
1694	2302	}
1695	2303
1696		-static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate)
	2304	+/*
	2305	+ * @xoffset: the src x offset of the right win in splice mode, other wise it
	2306	+ * must be zero.
	2307	+ */
	2308	+static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate, int xoffset)
1697	2309	{
1698	2310	struct drm_rect *src = &vpstate->src;
1699	2311	struct drm_framebuffer *fb = vpstate->base.fb;
1700		- uint32_t bpp = fb->format->bpp[0];
	2312	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
1701	2313	uint32_t vir_width = (fb->pitches[0] << 3) / (bpp ? bpp : 1);
1702	2314	uint32_t width = drm_rect_width(src) >> 16;
1703	2315	uint32_t height = drm_rect_height(src) >> 16;
..	..	@@ -1713,6 +2325,7 @@
1713	2325	uint8_t top_crop_line_num = 0;
1714	2326	uint8_t bottom_crop_line_num = 0;
1715	2327
	2328	+ act_xoffset += xoffset;
1716	2329	/* 16 pixel align */
1717	2330	if (height & 0xf)
1718	2331	align16_crop = 16 - (height & 0xf);
..	..	@@ -1864,7 +2477,7 @@
1864	2477	#define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \
1865	2478	(fac * (dst - 1) >> 16 < (src - 1))
1866	2479	#define VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac) \
1867		- (fac * (dst - 1) >> 16 <= (src - 1))
	2480	+ (fac * (dst - 1) >> 16 < (src - 1))
1868	2481
1869	2482	static uint16_t vop2_scale_factor(enum scale_mode mode,
1870	2483	int32_t filter_mode,
..	..	@@ -1956,12 +2569,12 @@
1956	2569	{
1957	2570	const struct vop2_data *vop2_data = vop2->data;
1958	2571	const struct vop2_win_data *win_data = &vop2_data->win[win->win_id];
1959		- const struct drm_format_info *info;
1960	2572	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
1961	2573	struct drm_framebuffer *fb = pstate->fb;
1962	2574	uint32_t pixel_format = fb->format->format;
1963		- int hsub = drm_format_horz_chroma_subsampling(pixel_format);
1964		- int vsub = drm_format_vert_chroma_subsampling(pixel_format);
	2575	+ const struct drm_format_info *info = drm_format_info(pixel_format);
	2576	+ uint8_t hsub = info->hsub;
	2577	+ uint8_t vsub = info->vsub;
1965	2578	uint16_t cbcr_src_w = src_w / hsub;
1966	2579	uint16_t cbcr_src_h = src_h / vsub;
1967	2580	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
..	..	@@ -1970,8 +2583,6 @@
1970	2583	uint8_t xgt2 = 0, xgt4 = 0;
1971	2584	uint8_t ygt2 = 0, ygt4 = 0;
1972	2585	uint32_t val;
1973		-
1974		- info = drm_format_info(pixel_format);
1975	2586
1976	2587	if (is_vop3(vop2)) {
1977	2588	if (src_w >= (4 * dst_w)) {
..	..	@@ -1983,12 +2594,30 @@
1983	2594	}
1984	2595	}
1985	2596
1986		- if (src_h >= (4 * dst_h)) {
1987		- ygt4 = 1;
1988		- src_h >>= 2;
1989		- } else if (src_h >= (2 * dst_h)) {
1990		- ygt2 = 1;
1991		- src_h >>= 1;
	2597	+ /**
	2598	+ * The rk3528 is processed as 2 pixel/cycle,
	2599	+ * so ygt2/ygt4 needs to be triggered in advance to improve performance
	2600	+ * when src_w is bigger than 1920.
	2601	+ * dst_h / src_h is at [1, 0.65) ygt2=0; ygt4=0;
	2602	+ * dst_h / src_h is at [0.65, 0.35) ygt2=1; ygt4=0;
	2603	+ * dst_h / src_h is at [0.35, 0) ygt2=0; ygt4=1;
	2604	+ */
	2605	+ if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) {
	2606	+ if (src_h >= (100 * dst_h / 35)) {
	2607	+ ygt4 = 1;
	2608	+ src_h >>= 2;
	2609	+ } else if ((src_h >= 100 * dst_h / 65) && (src_h < 100 * dst_h / 35)) {
	2610	+ ygt2 = 1;
	2611	+ src_h >>= 1;
	2612	+ }
	2613	+ } else {
	2614	+ if (src_h >= (4 * dst_h)) {
	2615	+ ygt4 = 1;
	2616	+ src_h >>= 2;
	2617	+ } else if (src_h >= (2 * dst_h)) {
	2618	+ ygt2 = 1;
	2619	+ src_h >>= 1;
	2620	+ }
1992	2621	}
1993	2622
1994	2623	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
..	..	@@ -2065,10 +2694,17 @@
2065	2694	if (!is_vop3(vop2) \|\|
2066	2695	(!vpstate->afbc_en && !vpstate->tiled_en) \|\|
2067	2696	win_data->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) {
2068		- if (cbcr_src_h >= (4 * dst_h))
2069		- ygt4 = 1;
2070		- else if (cbcr_src_h >= (2 * dst_h))
2071		- ygt2 = 1;
	2697	+ if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) {
	2698	+ if (cbcr_src_h >= (100 * dst_h / 35))
	2699	+ ygt4 = 1;
	2700	+ else if ((cbcr_src_h >= 100 * dst_h / 65) && (cbcr_src_h < 100 * dst_h / 35))
	2701	+ ygt2 = 1;
	2702	+ } else {
	2703	+ if (cbcr_src_h >= (4 * dst_h))
	2704	+ ygt4 = 1;
	2705	+ else if (cbcr_src_h >= (2 * dst_h))
	2706	+ ygt2 = 1;
	2707	+ }
2072	2708
2073	2709	if (ygt4)
2074	2710	cbcr_src_h >>= 2;
..	..	@@ -2166,7 +2802,7 @@
2166	2802	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2167	2803	win = vop2_find_win_by_phys_id(vop2, phys_id);
2168	2804	need_wait_win_disabled \|= VOP_WIN_GET(vop2, win, enable);
2169		- vop2_win_disable(win);
	2805	+ vop2_win_disable(win, false);
2170	2806	}
2171	2807
2172	2808	if (need_wait_win_disabled) {
..	..	@@ -2215,7 +2851,7 @@
2215	2851	struct vop2_plane_state *vpstate)
2216	2852	{
2217	2853	struct drm_plane_state *pstate = &vpstate->base;
2218		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
	2854	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->rockchip_crtc.crtc.state);
2219	2855	int is_input_yuv = pstate->fb->format->is_yuv;
2220	2856	int is_output_yuv = vcstate->yuv_overlay;
2221	2857	int input_csc = vpstate->color_space;
..	..	@@ -2230,29 +2866,49 @@
2230	2866	vpstate->r2y_en = 0;
2231	2867	vpstate->csc_mode = 0;
2232	2868
2233		- /* hdr2sdr and sdr2hdr will do csc itself */
2234		- if (vpstate->hdr2sdr_en) {
2235		- /*
2236		- * This is hdr2sdr enabled plane
2237		- * If it's RGB layer do hdr2sdr, we need to do r2y before send to hdr2sdr,
2238		- * because hdr2sdr only support yuv input.
2239		- */
2240		- if (!is_input_yuv) {
2241		- vpstate->r2y_en = 1;
2242		- vpstate->csc_mode = vop2_convert_csc_mode(output_csc, CSC_10BIT_DEPTH);
	2869	+ if (is_vop3(vp->vop2)) {
	2870	+ if (vpstate->hdr_in) {
	2871	+ if (is_input_yuv) {
	2872	+ vpstate->y2r_en = 1;
	2873	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2874	+ CSC_13BIT_DEPTH);
	2875	+ }
	2876	+ return;
	2877	+ } else if (vp->sdr2hdr_en) {
	2878	+ if (is_input_yuv) {
	2879	+ vpstate->y2r_en = 1;
	2880	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2881	+ csc_y2r_bit_depth);
	2882	+ }
	2883	+ return;
2243	2884	}
2244		- return;
2245		- } else if (!vpstate->hdr_in && vp->sdr2hdr_en) {
2246		- /*
2247		- * This is sdr2hdr enabled plane
2248		- * If it's YUV layer do sdr2hdr, we need to do y2r before send to sdr2hdr,
2249		- * because sdr2hdr only support rgb input.
2250		- */
2251		- if (is_input_yuv) {
2252		- vpstate->y2r_en = 1;
2253		- vpstate->csc_mode = vop2_convert_csc_mode(input_csc, csc_y2r_bit_depth);
	2885	+ } else {
	2886	+ /* hdr2sdr and sdr2hdr will do csc itself */
	2887	+ if (vpstate->hdr2sdr_en) {
	2888	+ /*
	2889	+ * This is hdr2sdr enabled plane
	2890	+ * If it's RGB layer do hdr2sdr, we need to do r2y before send to hdr2sdr,
	2891	+ * because hdr2sdr only support yuv input.
	2892	+ */
	2893	+ if (!is_input_yuv) {
	2894	+ vpstate->r2y_en = 1;
	2895	+ vpstate->csc_mode = vop2_convert_csc_mode(output_csc,
	2896	+ CSC_10BIT_DEPTH);
	2897	+ }
	2898	+ return;
	2899	+ } else if (!vpstate->hdr_in && vp->sdr2hdr_en) {
	2900	+ /*
	2901	+ * This is sdr2hdr enabled plane
	2902	+ * If it's YUV layer do sdr2hdr, we need to do y2r before send to sdr2hdr,
	2903	+ * because sdr2hdr only support rgb input.
	2904	+ */
	2905	+ if (is_input_yuv) {
	2906	+ vpstate->y2r_en = 1;
	2907	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2908	+ csc_y2r_bit_depth);
	2909	+ }
	2910	+ return;
2254	2911	}
2255		- return;
2256	2912	}
2257	2913
2258	2914	if (is_input_yuv && !is_output_yuv) {
..	..	@@ -2380,8 +3036,14 @@
2380	3036	if (ret < 0)
2381	3037	goto err_disable_hclk;
2382	3038
	3039	+ ret = clk_enable(vop2->pclk);
	3040	+ if (ret < 0)
	3041	+ goto err_disable_aclk;
	3042	+
2383	3043	return 0;
2384	3044
	3045	+err_disable_aclk:
	3046	+ clk_disable(vop2->aclk);
2385	3047	err_disable_hclk:
2386	3048	clk_disable(vop2->hclk);
2387	3049	return ret;
..	..	@@ -2389,6 +3051,7 @@
2389	3051
2390	3052	static void vop2_core_clks_disable(struct vop2 *vop2)
2391	3053	{
	3054	+ clk_disable(vop2->pclk);
2392	3055	clk_disable(vop2->aclk);
2393	3056	clk_disable(vop2->hclk);
2394	3057	}
..	..	@@ -2499,6 +3162,18 @@
2499	3162	return MODE_OK;
2500	3163	}
2501	3164
	3165	+static inline bool
	3166	+vop2_wb_connector_changed_only(struct drm_crtc_state cstate, struct drm_connector conn)
	3167	+{
	3168	+ struct drm_crtc_state *old_state;
	3169	+ u32 changed_connectors;
	3170	+
	3171	+ old_state = drm_atomic_get_old_crtc_state(cstate->state, cstate->crtc);
	3172	+ changed_connectors = cstate->connector_mask ^ old_state->connector_mask;
	3173	+
	3174	+ return BIT(drm_connector_index(conn)) == changed_connectors;
	3175	+}
	3176	+
2502	3177	static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder,
2503	3178	struct drm_crtc_state *cstate,
2504	3179	struct drm_connector_state *conn_state)
..	..	@@ -2507,7 +3182,18 @@
2507	3182	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
2508	3183	struct vop2_video_port *vp = to_vop2_video_port(cstate->crtc);
2509	3184	struct drm_framebuffer *fb;
	3185	+ struct drm_gem_object obj, uv_obj;
	3186	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
2510	3187
	3188	+ /*
	3189	+ * No need for a full modested when the only connector changed is the
	3190	+ * writeback connector.
	3191	+ */
	3192	+ if (cstate->connectors_changed &&
	3193	+ vop2_wb_connector_changed_only(cstate, conn_state->connector)) {
	3194	+ cstate->connectors_changed = false;
	3195	+ DRM_DEBUG("VP%d force change connectors_changed to false when only wb changed\n", vp->id);
	3196	+ }
2511	3197	if (!conn_state->writeback_job \|\| !conn_state->writeback_job->fb)
2512	3198	return 0;
2513	3199
..	..	@@ -2520,7 +3206,7 @@
2520	3206	}
2521	3207
2522	3208	if ((fb->width > cstate->mode.hdisplay) \|\|
2523		- ((fb->height != cstate->mode.vdisplay) &&
	3209	+ ((fb->height < cstate->mode.vdisplay) &&
2524	3210	(fb->height != (cstate->mode.vdisplay >> 1)))) {
2525	3211	DRM_DEBUG_KMS("Invalid framebuffer size %ux%u, Only support x scale down and 1/2 y scale down\n",
2526	3212	fb->width, fb->height);
..	..	@@ -2528,7 +3214,7 @@
2528	3214	}
2529	3215
2530	3216	wb_state->scale_x_factor = vop2_scale_factor(SCALE_DOWN, VOP2_SCALE_DOWN_BIL,
2531		- cstate->mode.hdisplay, fb->width);
	3217	+ cstate->mode.hdisplay, fb->width);
2532	3218	wb_state->scale_x_en = (fb->width < cstate->mode.hdisplay) ? 1 : 0;
2533	3219	wb_state->scale_y_en = (fb->height < cstate->mode.vdisplay) ? 1 : 0;
2534	3220
..	..	@@ -2543,15 +3229,15 @@
2543	3229	}
2544	3230
2545	3231	wb_state->vp_id = vp->id;
2546		- wb_state->yrgb_addr = rockchip_fb_get_dma_addr(fb, 0);
2547		- /*
2548		- * uv address must follow yrgb address without gap.
2549		- * the fb->offsets is include stride, so we should
2550		- * not use it.
2551		- */
	3232	+ obj = fb->obj[0];
	3233	+ rk_obj = to_rockchip_obj(obj);
	3234	+ wb_state->yrgb_addr = rk_obj->dma_addr + fb->offsets[0];
	3235	+
2552	3236	if (fb->format->is_yuv) {
2553		- wb_state->uv_addr = wb_state->yrgb_addr;
2554		- wb_state->uv_addr += DIV_ROUND_UP(fb->width * fb->format->bpp[0], 8) * fb->height;
	3237	+ uv_obj = fb->obj[1];
	3238	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	3239	+
	3240	+ wb_state->uv_addr = rk_uv_obj->dma_addr + fb->offsets[1];
2555	3241	}
2556	3242
2557	3243	return 0;
..	..	@@ -2641,10 +3327,12 @@
2641	3327	if (conn_state->writeback_job && conn_state->writeback_job->fb) {
2642	3328	struct drm_framebuffer *fb = conn_state->writeback_job->fb;
2643	3329
2644		- DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
2645		- fb->width, fb->height, wb_state->format, fb->pitches[0], &wb_state->yrgb_addr);
	3330	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_WB,
	3331	+ "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
	3332	+ fb->width, fb->height, wb_state->format,
	3333	+ fb->pitches[0], &wb_state->yrgb_addr);
2646	3334
2647		- drm_writeback_queue_job(wb_conn, conn_state->writeback_job);
	3335	+ drm_writeback_queue_job(wb_conn, conn_state);
2648	3336	conn_state->writeback_job = NULL;
2649	3337
2650	3338	spin_lock_irqsave(&wb->job_lock, flags);
..	..	@@ -2657,7 +3345,7 @@
2657	3345	fifo_throd = fb->pitches[0] >> 4;
2658	3346	if (fifo_throd >= vop2->data->wb->fifo_depth)
2659	3347	fifo_throd = vop2->data->wb->fifo_depth;
2660		- r2y = fb->format->is_yuv && (!is_yuv_output(vcstate->bus_format));
	3348	+ r2y = !vcstate->yuv_overlay && fb->format->is_yuv;
2661	3349
2662	3350	/*
2663	3351	* the vp_id register config done immediately
..	..	@@ -2673,6 +3361,7 @@
2673	3361	VOP_MODULE_SET(vop2, wb, r2y_en, r2y);
2674	3362	VOP_MODULE_SET(vop2, wb, enable, 1);
2675	3363	vop2_wb_irqs_enable(vop2);
	3364	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 1);
2676	3365	}
2677	3366	}
2678	3367
..	..	@@ -2697,6 +3386,7 @@
2697	3386
2698	3387	return;
2699	3388	}
	3389	+
2700	3390	spin_lock(&vop2->reg_lock);
2701	3391	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 0);
2702	3392	vop2_cfg_done(crtc);
..	..	@@ -2712,8 +3402,7 @@
2712	3402	spin_lock(&vop2->reg_lock);
2713	3403
2714	3404	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2715		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
2716		- vop2_cfg_done(crtc);
	3405	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2717	3406	vp->gamma_lut_active = true;
2718	3407
2719	3408	spin_unlock(&vop2->reg_lock);
..	..	@@ -2733,7 +3422,7 @@
2733	3422	vop2_write_lut(vop2, i << 2, lut[i]);
2734	3423
2735	3424	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2736		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
	3425	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2737	3426	vp->gamma_lut_active = true;
2738	3427
2739	3428	spin_unlock(&vop2->reg_lock);
..	..	@@ -2753,27 +3442,14 @@
2753	3442	if (vop2->version == VOP_VERSION_RK3568) {
2754	3443	rk3568_crtc_load_lut(crtc);
2755	3444	} else {
2756		- rk3588_crtc_load_lut(crtc, vp->lut);
2757		- vop2_cfg_done(crtc);
	3445	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	3446	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3447	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3448	+
	3449	+ rk3588_crtc_load_lut(&vp->rockchip_crtc.crtc, vp->lut);
	3450	+ if (vcstate->splice_mode)
	3451	+ rk3588_crtc_load_lut(&splice_vp->rockchip_crtc.crtc, vp->lut);
2758	3452	}
2759		- /*
2760		- * maybe appear the following case:
2761		- * -> set gamma
2762		- * -> config done
2763		- * -> atomic commit
2764		- * --> update win format
2765		- * --> update win address
2766		- * ---> here maybe meet vop hardware frame start, and triggle some config take affect.
2767		- * ---> as only some config take affect, this maybe lead to iommu pagefault.
2768		- * --> update win size
2769		- * --> update win other parameters
2770		- * -> config done
2771		- *
2772		- * so we add vop2_wait_for_fs_by_done_bit_status() to make sure the first config done take
2773		- * effect and then to do next frame config.
2774		- */
2775		- if (VOP_MODULE_GET(vop2, vp, standby) == 0)
2776		- vop2_wait_for_fs_by_done_bit_status(vp);
2777	3453	}
2778	3454
2779	3455	static void rockchip_vop2_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red,
..	..	@@ -2815,6 +3491,7 @@
2815	3491	struct drm_modeset_acquire_ctx *ctx)
2816	3492	{
2817	3493	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	3494	+ struct vop2 *vop2 = vp->vop2;
2818	3495	int i;
2819	3496
2820	3497	if (!vp->lut)
..	..	@@ -2829,6 +3506,25 @@
2829	3506	rockchip_vop2_crtc_fb_gamma_set(crtc, red[i], green[i],
2830	3507	blue[i], i);
2831	3508	vop2_crtc_load_lut(crtc);
	3509	+ vop2_cfg_done(crtc);
	3510	+ /*
	3511	+ * maybe appear the following case:
	3512	+ * -> set gamma
	3513	+ * -> config done
	3514	+ * -> atomic commit
	3515	+ * --> update win format
	3516	+ * --> update win address
	3517	+ * ---> here maybe meet vop hardware frame start, and triggle some config take affect.
	3518	+ * ---> as only some config take affect, this maybe lead to iommu pagefault.
	3519	+ * --> update win size
	3520	+ * --> update win other parameters
	3521	+ * -> config done
	3522	+ *
	3523	+ * so we add vop2_wait_for_fs_by_done_bit_status() to make sure the first config done take
	3524	+ * effect and then to do next frame config.
	3525	+ */
	3526	+ if (VOP_MODULE_GET(vop2, vp, standby) == 0)
	3527	+ vop2_wait_for_fs_by_done_bit_status(vp);
2832	3528
2833	3529	return 0;
2834	3530	}
..	..	@@ -2851,6 +3547,7 @@
2851	3547	static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
2852	3548	struct drm_crtc_state *old_state)
2853	3549	{
	3550	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2854	3551	struct vop2_video_port *vp = to_vop2_video_port(crtc);
2855	3552	struct rockchip_drm_private *private = crtc->dev->dev_private;
2856	3553	struct drm_color_lut *lut = vp->cubic_lut;
..	..	@@ -2901,12 +3598,51 @@
2901	3598	*cubic_lut_kvaddr = 0;
2902	3599	}
2903	3600
	3601	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid);
2904	3602	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
2905	3603	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 1);
2906	3604	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 1);
2907	3605	VOP_CTRL_SET(vop2, lut_dma_en, 1);
2908	3606
	3607	+ if (vcstate->splice_mode) {
	3608	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3609	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3610	+
	3611	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_mst, cubic_lut_mst);
	3612	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_update_en, 1);
	3613	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_en, 1);
	3614	+ }
	3615	+
2909	3616	return 0;
	3617	+}
	3618	+
	3619	+static void vop2_attach_cubic_lut_prop(struct drm_crtc *crtc, unsigned int cubic_lut_size)
	3620	+{
	3621	+ struct rockchip_drm_private *private = crtc->dev->dev_private;
	3622	+
	3623	+ drm_object_attach_property(&crtc->base, private->cubic_lut_prop, 0);
	3624	+ drm_object_attach_property(&crtc->base, private->cubic_lut_size_prop, cubic_lut_size);
	3625	+}
	3626	+
	3627	+static void vop2_cubic_lut_init(struct vop2 *vop2)
	3628	+{
	3629	+ const struct vop2_data *vop2_data = vop2->data;
	3630	+ const struct vop2_video_port_data *vp_data;
	3631	+ struct vop2_video_port *vp;
	3632	+ struct drm_crtc *crtc;
	3633	+ int i;
	3634	+
	3635	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	3636	+ vp = &vop2->vps[i];
	3637	+ crtc = &vp->rockchip_crtc.crtc;
	3638	+ if (!crtc->dev)
	3639	+ continue;
	3640	+ vp_data = &vop2_data->vp[vp->id];
	3641	+ vp->cubic_lut_len = vp_data->cubic_lut_len;
	3642	+
	3643	+ if (vp->cubic_lut_len)
	3644	+ vop2_attach_cubic_lut_prop(crtc, vp->cubic_lut_len);
	3645	+ }
2910	3646	}
2911	3647
2912	3648	static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
..	..	@@ -2925,7 +3661,15 @@
2925	3661	goto err;
2926	3662	}
2927	3663
	3664	+ ret = clk_prepare_enable(vop2->pclk);
	3665	+ if (ret < 0) {
	3666	+ dev_err(vop2->dev, "failed to enable pclk - %d\n", ret);
	3667	+ goto err1;
	3668	+ }
	3669	+
2928	3670	return 0;
	3671	+err1:
	3672	+ clk_disable_unprepare(vop2->aclk);
2929	3673	err:
2930	3674	clk_disable_unprepare(vop2->hclk);
2931	3675
..	..	@@ -2963,25 +3707,16 @@
2963	3707	*/
2964	3708	static void vop3_layer_map_initial(struct vop2 *vop2, uint32_t current_vp_id)
2965	3709	{
2966		- struct vop2_video_port *vp;
2967		- struct vop2_win *win;
2968		- unsigned long win_mask;
2969	3710	uint16_t vp_id;
2970		- int phys_id;
2971		- int i;
	3711	+ struct drm_plane *plane = NULL;
2972	3712
2973		- for (i = 0; i < vop2->data->nr_vps; i++) {
2974		- vp_id = i;
2975		- vp = &vop2->vps[vp_id];
2976		- vp->win_mask = vp->plane_mask;
2977		- win_mask = vp->win_mask;
2978		- for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2979		- win = vop2_find_win_by_phys_id(vop2, phys_id);
2980		- VOP_CTRL_SET(vop2, win_vp_id[phys_id], vp_id);
2981		- win->vp_mask = BIT(vp_id);
2982		- win->old_vp_mask = win->vp_mask;
2983		- DRM_DEV_DEBUG(vop2->dev, "%s attach to vp%d\n", win->name, vp_id);
2984		- }
	3713	+ drm_for_each_plane(plane, vop2->drm_dev) {
	3714	+ struct vop2_win *win = to_vop2_win(plane);
	3715	+
	3716	+ vp_id = VOP_CTRL_GET(vop2, win_vp_id[win->phys_id]);
	3717	+ win->vp_mask = BIT(vp_id);
	3718	+ win->old_vp_mask = win->vp_mask;
	3719	+ vop2->vps[vp_id].win_mask \|= BIT(win->phys_id);
2985	3720	}
2986	3721	}
2987	3722
..	..	@@ -3051,6 +3786,18 @@
3051	3786
3052	3787	}
3053	3788
	3789	+static void rk3588_vop2_regsbak(struct vop2 *vop2)
	3790	+{
	3791	+ uint32_t *base = vop2->regs;
	3792	+ int i;
	3793	+
	3794	+ /*
	3795	+ * No need to backup DSC/GAMMA_LUT/BPP_LUT/MMU
	3796	+ */
	3797	+ for (i = 0; i < (0x2000 >> 2); i++)
	3798	+ vop2->regsbak[i] = base[i];
	3799	+}
	3800	+
3054	3801	static void vop2_initial(struct drm_crtc *crtc)
3055	3802	{
3056	3803	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3075,14 +3822,29 @@
3075	3822	if (vop2_soc_is_rk3566())
3076	3823	VOP_CTRL_SET(vop2, otp_en, 1);
3077	3824
3078		- memcpy(vop2->regsbak, vop2->regs, vop2->len);
	3825	+ /*
	3826	+ * rk3588 don't support access mmio by memcpy
	3827	+ */
	3828	+ if (vop2->version == VOP_VERSION_RK3588)
	3829	+ rk3588_vop2_regsbak(vop2);
	3830	+ else
	3831	+ memcpy(vop2->regsbak, vop2->regs, vop2->len);
3079	3832
3080	3833	VOP_MODULE_SET(vop2, wb, axi_yrgb_id, 0xd);
3081	3834	VOP_MODULE_SET(vop2, wb, axi_uv_id, 0xe);
3082	3835	vop2_wb_cfg_done(vp);
3083	3836
3084		- if (is_vop3(vop2))
3085		- VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->data->esmart_lb_mode);
	3837	+ if (is_vop3(vop2)) {
	3838	+ VOP_CTRL_SET(vop2, dsp_vs_t_sel, 0);
	3839	+ VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->esmart_lb_mode);
	3840	+ }
	3841	+
	3842	+ /*
	3843	+ * This is unused and error init value for rk3528/rk3562 vp1, if less of this config,
	3844	+ * vp1 can't display normally.
	3845	+ */
	3846	+ if (vop2->version == VOP_VERSION_RK3528 \|\| vop2->version == VOP_VERSION_RK3562)
	3847	+ vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true);
3086	3848
3087	3849	VOP_CTRL_SET(vop2, cfg_done_en, 1);
3088	3850	/*
..	..	@@ -3092,6 +3854,7 @@
3092	3854	VOP_CTRL_SET(vop2, auto_gating_en, 0);
3093	3855
3094	3856	VOP_CTRL_SET(vop2, aclk_pre_auto_gating_en, 0);
	3857	+
3095	3858	/*
3096	3859	* Register OVERLAY_LAYER_SEL and OVERLAY_PORT_SEL should take effect immediately,
3097	3860	* than windows configuration(CLUSTER/ESMART/SMART) can take effect according the
..	..	@@ -3104,9 +3867,17 @@
3104	3867	*/
3105	3868	VOP_CTRL_SET(vop2, if_ctrl_cfg_done_imd, 1);
3106	3869
	3870	+ /* Close dynamic turn on/off rk3588 PD_ESMART and keep esmart pd on when enable */
	3871	+ if (vop2->version == VOP_VERSION_RK3588) {
	3872	+ struct vop2_power_domain *esmart_pd = vop2_find_pd_by_id(vop2, VOP2_PD_ESMART);
	3873	+
	3874	+ if (vop2_power_domain_status(esmart_pd))
	3875	+ esmart_pd->on = true;
	3876	+ else
	3877	+ vop2_power_domain_on(esmart_pd);
	3878	+ }
3107	3879	vop2_layer_map_initial(vop2, current_vp_id);
3108	3880	vop2_axi_irqs_enable(vop2);
3109		-
3110	3881	vop2->is_enabled = true;
3111	3882	}
3112	3883
..	..	@@ -3120,6 +3891,93 @@
3120	3891	vp->id, ret);
3121	3892	}
3122	3893
	3894	+/*
	3895	+ * The internal PD of VOP2 on rk3588 take effect immediately
	3896	+ * for power up and take effect by vsync for power down.
	3897	+ *
	3898	+ * And the PD_CLUSTER0 is a parent PD of PD_CLUSTER1/2/3,
	3899	+ * we may have this use case:
	3900	+ * Cluster0 is attached to VP0 for HDMI output,
	3901	+ * Cluster1 is attached to VP1 for MIPI DSI,
	3902	+
	3903	+ * When we enable Cluster1 on VP1, we should enable PD_CLUSTER0 as
	3904	+ * it is the parent PD, event though HDMI is plugout, VP1 is disabled,
	3905	+ * the PD of Cluster0 should keep power on.
	3906	+
	3907	+ * When system go to suspend:
	3908	+ * (1) Power down PD of Cluster1 before VP1 standby(the power down is take
	3909	+ * effect by vsync)
	3910	+ * (2) Power down PD of Cluster0
	3911	+ *
	3912	+ * But we have problem at step (2), Cluster0 is attached to VP0. but VP0
	3913	+ * is in standby mode, as it is never used or hdmi plugout. So there is
	3914	+ * no vsync, the power down will never take effect.
	3915	+
	3916	+ * According to IC designer: We must power down all internal PD of VOP
	3917	+ * before we power down the global PD_VOP.
	3918	+
	3919	+ * So we get this workaround:
	3920	+ * If we found a VP is in standby mode when we want power down a PD is
	3921	+ * attached to it, we release the VP from standby mode, than it will
	3922	+ * run a default timing and generate vsync. Than we can power down the
	3923	+ * PD by this vsync. After all this is done, we standby the VP at last.
	3924	+ */
	3925	+static void vop2_power_domain_off_by_disabled_vp(struct vop2_power_domain *pd)
	3926	+{
	3927	+ struct vop2_video_port *vp = NULL;
	3928	+ struct vop2 *vop2 = pd->vop2;
	3929	+ struct vop2_win *win;
	3930	+ struct drm_crtc *crtc;
	3931	+ uint32_t vp_id;
	3932	+ uint8_t phys_id;
	3933	+ int ret;
	3934	+
	3935	+ if (pd->data->id == VOP2_PD_CLUSTER0 \|\| pd->data->id == VOP2_PD_CLUSTER1 \|\|
	3936	+ pd->data->id == VOP2_PD_CLUSTER2 \|\| pd->data->id == VOP2_PD_CLUSTER3 \|\|
	3937	+ pd->data->id == VOP2_PD_ESMART) {
	3938	+ phys_id = ffs(pd->data->module_id_mask) - 1;
	3939	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	3940	+ vp_id = ffs(win->vp_mask) - 1;
	3941	+ vp = &vop2->vps[vp_id];
	3942	+ } else {
	3943	+ DRM_DEV_ERROR(vop2->dev, "unexpected power on pd%d\n", ffs(pd->data->id) - 1);
	3944	+ }
	3945	+
	3946	+ if (vp) {
	3947	+ ret = clk_prepare_enable(vp->dclk);
	3948	+ if (ret < 0)
	3949	+ DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n",
	3950	+ vp->id, ret);
	3951	+ crtc = &vp->rockchip_crtc.crtc;
	3952	+ VOP_MODULE_SET(vop2, vp, standby, 0);
	3953	+ vop2_power_domain_off(pd);
	3954	+ vop2_cfg_done(crtc);
	3955	+ vop2_wait_power_domain_off(pd);
	3956	+
	3957	+ reinit_completion(&vp->dsp_hold_completion);
	3958	+ vop2_dsp_hold_valid_irq_enable(crtc);
	3959	+ VOP_MODULE_SET(vop2, vp, standby, 1);
	3960	+ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, msecs_to_jiffies(50));
	3961	+ if (!ret)
	3962	+ DRM_DEV_INFO(vop2->dev, "wait for vp%d dsp_hold timeout\n", vp->id);
	3963	+
	3964	+ vop2_dsp_hold_valid_irq_disable(crtc);
	3965	+ clk_disable_unprepare(vp->dclk);
	3966	+ }
	3967	+}
	3968	+
	3969	+static void vop2_power_off_all_pd(struct vop2 *vop2)
	3970	+{
	3971	+ struct vop2_power_domain pd, n;
	3972	+
	3973	+ list_for_each_entry_safe_reverse(pd, n, &vop2->pd_list_head, list) {
	3974	+ if (vop2_power_domain_status(pd))
	3975	+ vop2_power_domain_off_by_disabled_vp(pd);
	3976	+ pd->on = false;
	3977	+ pd->vp_mask = 0;
	3978	+ }
	3979	+}
	3980	+
3123	3981	static void vop2_disable(struct drm_crtc *crtc)
3124	3982	{
3125	3983	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3130,7 +3988,6 @@
3130	3988	if (--vop2->enable_count > 0)
3131	3989	return;
3132	3990
3133		- vop2->is_enabled = false;
3134	3991	if (vop2->is_iommu_enabled) {
3135	3992	/*
3136	3993	* vop2 standby complete, so iommu detach is safe.
..	..	@@ -3139,32 +3996,455 @@
3139	3996	rockchip_drm_dma_detach_device(vop2->drm_dev, vop2->dev);
3140	3997	vop2->is_iommu_enabled = false;
3141	3998	}
	3999	+ if (vop2->version == VOP_VERSION_RK3588)
	4000	+ vop2_power_off_all_pd(vop2);
3142	4001
	4002	+ vop2->is_enabled = false;
3143	4003	pm_runtime_put_sync(vop2->dev);
3144	4004
	4005	+ clk_disable_unprepare(vop2->pclk);
3145	4006	clk_disable_unprepare(vop2->aclk);
3146	4007	clk_disable_unprepare(vop2->hclk);
	4008	+}
	4009	+
	4010	+static void vop2_crtc_disable_dsc(struct vop2 *vop2, u8 dsc_id)
	4011	+{
	4012	+ struct vop2_dsc *dsc = &vop2->dscs[dsc_id];
	4013	+
	4014	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	4015	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, 0);
	4016	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 0);
	4017	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 0);
	4018	+}
	4019	+
	4020	+static struct vop2_clk vop2_clk_get(struct vop2 vop2, const char *name)
	4021	+{
	4022	+ struct vop2_clk clk, n;
	4023	+
	4024	+ if (!name)
	4025	+ return NULL;
	4026	+
	4027	+ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
	4028	+ if (!strcmp(clk_hw_get_name(&clk->hw), name))
	4029	+ return clk;
	4030	+ }
	4031	+
	4032	+ return NULL;
	4033	+}
	4034	+
	4035	+static void vop2_clk_set_parent(struct clk clk, struct clk parent)
	4036	+{
	4037	+ int ret = 0;
	4038	+
	4039	+ if (parent)
	4040	+ ret = clk_set_parent(clk, parent);
	4041	+ if (ret < 0)
	4042	+ DRM_WARN("failed to set %s as parent for %s\n",
	4043	+ __clk_get_name(parent), __clk_get_name(clk));
	4044	+}
	4045	+
	4046	+static int vop2_extend_clk_init(struct vop2 *vop2)
	4047	+{
	4048	+ const char * const extend_clk_name[] = {
	4049	+ "hdmi0_phy_pll", "hdmi1_phy_pll"};
	4050	+ struct drm_device *drm_dev = vop2->drm_dev;
	4051	+ struct clk *clk;
	4052	+ struct vop2_extend_pll *extend_pll;
	4053	+ int i;
	4054	+
	4055	+ INIT_LIST_HEAD(&vop2->extend_clk_list_head);
	4056	+
	4057	+ if (vop2->version != VOP_VERSION_RK3588)
	4058	+ return 0;
	4059	+
	4060	+ for (i = 0; i < ARRAY_SIZE(extend_clk_name); i++) {
	4061	+ clk = devm_clk_get_optional(drm_dev->dev, extend_clk_name[i]);
	4062	+ if (IS_ERR(clk)) {
	4063	+ dev_warn(drm_dev->dev, "failed to get %s: %ld\n",
	4064	+ extend_clk_name[i], PTR_ERR(clk));
	4065	+ continue;
	4066	+ }
	4067	+
	4068	+ if (!clk)
	4069	+ continue;
	4070	+
	4071	+ extend_pll = devm_kzalloc(drm_dev->dev, sizeof(*extend_pll), GFP_KERNEL);
	4072	+ if (!extend_pll)
	4073	+ return -ENOMEM;
	4074	+
	4075	+ extend_pll->clk = clk;
	4076	+ extend_pll->vp_mask = 0;
	4077	+ strncpy(extend_pll->clk_name, extend_clk_name[i], sizeof(extend_pll->clk_name));
	4078	+ list_add_tail(&extend_pll->list, &vop2->extend_clk_list_head);
	4079	+ }
	4080	+
	4081	+ return 0;
	4082	+}
	4083	+
	4084	+static struct vop2_extend_pll vop2_extend_clk_find_by_name(struct vop2 vop2, char *clk_name)
	4085	+{
	4086	+ struct vop2_extend_pll *extend_pll;
	4087	+
	4088	+ list_for_each_entry(extend_pll, &vop2->extend_clk_list_head, list) {
	4089	+ if (!strcmp(extend_pll->clk_name, clk_name))
	4090	+ return extend_pll;
	4091	+ }
	4092	+
	4093	+ return NULL;
	4094	+}
	4095	+
	4096	+static int vop2_extend_clk_switch_pll(struct vop2 vop2, struct vop2_extend_pll src,
	4097	+ struct vop2_extend_pll *dst)
	4098	+{
	4099	+ struct vop2_clk *dclk;
	4100	+ u32 vp_mask;
	4101	+ int i = 0;
	4102	+ char clk_name[32];
	4103	+
	4104	+ if (!src->vp_mask)
	4105	+ return -EINVAL;
	4106	+
	4107	+ if (dst->vp_mask)
	4108	+ return -EBUSY;
	4109	+
	4110	+ vp_mask = src->vp_mask;
	4111	+
	4112	+ while (vp_mask) {
	4113	+ if ((BIT(i) & src->vp_mask)) {
	4114	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", i);
	4115	+ dclk = vop2_clk_get(vop2, clk_name);
	4116	+ clk_set_rate(dst->clk, dclk->rate);
	4117	+ vop2_clk_set_parent(vop2->vps[i].dclk, dst->clk);
	4118	+ src->vp_mask &= ~BIT(i);
	4119	+ dst->vp_mask \|= BIT(i);
	4120	+ }
	4121	+ i++;
	4122	+ vp_mask = vp_mask >> 1;
	4123	+ }
	4124	+
	4125	+ return 0;
	4126	+}
	4127	+
	4128	+static inline int vop2_extend_clk_get_vp_id(struct vop2_extend_pll *ext_pll)
	4129	+{
	4130	+ return ffs(ext_pll->vp_mask) - 1;
	4131	+}
	4132	+
	4133	+/*
	4134	+ * Here are 2 hdmi phy pll can use for video port dclk. The strategies of how to use hdmi phy pll
	4135	+ * as follow:
	4136	+ *
	4137	+ * 1. hdmi phy pll can be used for video port0/1/2 when output format under 4K@60Hz;
	4138	+ *
	4139	+ * 2. When a video port connect both hdmi0 and hdmi1(may also connect other output interface),
	4140	+ * it must hold the hdmi0 and hdmi1 phy pll, and other video port can't use it. if request dclk
	4141	+ * is under 4K@60Hz, set the video port dlk parent as hdmi0 phy pll.if hdmi0 or hdmi1 phy pll
	4142	+ * is used by other video port, report a error.
	4143	+ *
	4144	+ * 3. When a video port(A) connect hdmi0(may also connect other output interface but not hdmi1),
	4145	+ * it must hold the hdmi0 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4146	+ * phy pll is used by other video port, report a error. If hdmi0 phy pll is used by another
	4147	+ * video port(B) and hdmi1 phy pll is free, set hdmi1 phy pll as video port(B) dclk parent and
	4148	+ * video port(A) hold hdmi0 phy pll. If hdmi0 phy pll is free, video port(A) hold hdmi0 pll.If
	4149	+ * video port(A) hold hdmi0 phy pll and request dclk is under 4k@60Hz, set hdmi0 phy pll as
	4150	+ * video port(A) dclk parent.
	4151	+ *
	4152	+ * 4. When a video port(A) connect hdmi1(may also connect other output interface but not hdmi0),
	4153	+ * it must hold the hdmi1 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4154	+ * phy pll is used by other video port, report a error. If hdmi1 phy pll is used by another
	4155	+ * video port(B) and hdmi0 phy pll is free, set hdmi0 phy pll as video port(B) dclk parent and
	4156	+ * video port(A) hold hdmi1 phy pll. If hdmi1 phy pll is free, video port(A) hold hdmi1 pll. If
	4157	+ * video port(A) hold hdmi1 phy pll and request dclk is under 4k@60Hz, set hdmi1 phy pll as
	4158	+ * video port(A) dclk parent.
	4159	+ *
	4160	+ * 5. When a video port connect dp(0, 1, or both, may also connect other output type but not hdmi0
	4161	+ * and hdmi1). If the request dclk is higher than 4K@60Hz or video port id is 2, do nothing.
	4162	+ * Otherwise get a free hdmi phy pll as video port dclk parent. If no free hdmi phy pll can be
	4163	+ * get, report a error.
	4164	+ */
	4165	+
	4166	+static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
	4167	+ struct rockchip_crtc_state *vcstate, bool enable)
	4168	+{
	4169	+ struct vop2 *vop2 = vp->vop2;
	4170	+ struct vop2_extend_pll hdmi0_phy_pll, hdmi1_phy_pll;
	4171	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	4172	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	4173	+
	4174	+ hdmi0_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	4175	+ hdmi1_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	4176	+
	4177	+ if (hdmi0_phy_pll)
	4178	+ clk_get_rate(hdmi0_phy_pll->clk);
	4179	+ if (hdmi1_phy_pll)
	4180	+ clk_get_rate(hdmi1_phy_pll->clk);
	4181	+
	4182	+ if ((!hdmi0_phy_pll && !hdmi1_phy_pll) \|\|
	4183	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) && !hdmi0_phy_pll) \|\|
	4184	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI1) && !hdmi1_phy_pll))
	4185	+ return 0;
	4186	+
	4187	+ if (enable) {
	4188	+ if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4189	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4190	+ if (hdmi0_phy_pll->vp_mask) {
	4191	+ DRM_ERROR("hdmi0 phy pll is used by vp%d\n",
	4192	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4193	+ return -EBUSY;
	4194	+ }
	4195	+
	4196	+ if (hdmi1_phy_pll->vp_mask) {
	4197	+ DRM_ERROR("hdmi1 phy pll is used by vp%d\n",
	4198	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4199	+ return -EBUSY;
	4200	+ }
	4201	+
	4202	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4203	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4204	+ else
	4205	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4206	+
	4207	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4208	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4209	+ } else if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4210	+ !(vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4211	+ if (hdmi0_phy_pll->vp_mask) {
	4212	+ if (hdmi1_phy_pll) {
	4213	+ if (hdmi1_phy_pll->vp_mask) {
	4214	+ DRM_ERROR("hdmi0: phy pll is used by vp%d:vp%d\n",
	4215	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4216	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4217	+ return -EBUSY;
	4218	+ }
	4219	+
	4220	+ vop2_extend_clk_switch_pll(vop2, hdmi0_phy_pll,
	4221	+ hdmi1_phy_pll);
	4222	+ } else {
	4223	+ DRM_ERROR("hdmi0: phy pll is used by vp%d\n",
	4224	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4225	+ return -EBUSY;
	4226	+ }
	4227	+ }
	4228	+
	4229	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4230	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4231	+ else
	4232	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4233	+
	4234	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4235	+ } else if (!(vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4236	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4237	+ if (hdmi1_phy_pll->vp_mask) {
	4238	+ if (hdmi0_phy_pll) {
	4239	+ if (hdmi0_phy_pll->vp_mask) {
	4240	+ DRM_ERROR("hdmi1: phy pll is used by vp%d:vp%d\n",
	4241	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4242	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4243	+ return -EBUSY;
	4244	+ }
	4245	+
	4246	+ vop2_extend_clk_switch_pll(vop2, hdmi1_phy_pll,
	4247	+ hdmi0_phy_pll);
	4248	+ } else {
	4249	+ DRM_ERROR("hdmi1: phy pll is used by vp%d\n",
	4250	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4251	+ return -EBUSY;
	4252	+ }
	4253	+ }
	4254	+
	4255	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4256	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4257	+ else
	4258	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4259	+
	4260	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4261	+ } else if (output_if_is_dp(vcstate->output_if)) {
	4262	+ if (vp->id == 2) {
	4263	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4264	+ return 0;
	4265	+ }
	4266	+
	4267	+ if (hdmi0_phy_pll && !hdmi0_phy_pll->vp_mask) {
	4268	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4269	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4270	+ } else if (hdmi1_phy_pll && !hdmi1_phy_pll->vp_mask) {
	4271	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4272	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4273	+ } else {
	4274	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4275	+ DRM_INFO("No free hdmi phy pll for DP, use default parent\n");
	4276	+ }
	4277	+ }
	4278	+ } else {
	4279	+ if (hdmi0_phy_pll && (BIT(vp->id) & hdmi0_phy_pll->vp_mask))
	4280	+ hdmi0_phy_pll->vp_mask &= ~BIT(vp->id);
	4281	+
	4282	+ if (hdmi1_phy_pll && (BIT(vp->id) & hdmi1_phy_pll->vp_mask))
	4283	+ hdmi1_phy_pll->vp_mask &= ~BIT(vp->id);
	4284	+ }
	4285	+
	4286	+ return 0;
	4287	+}
	4288	+
	4289	+static void vop2_crtc_atomic_enter_psr(struct drm_crtc crtc, struct drm_crtc_state old_state)
	4290	+{
	4291	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4292	+ struct vop2 *vop2 = vp->vop2;
	4293	+ struct vop2_win *win;
	4294	+ unsigned long win_mask = vp->enabled_win_mask;
	4295	+ int phys_id;
	4296	+
	4297	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	4298	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	4299	+ VOP_WIN_SET(vop2, win, enable, 0);
	4300	+
	4301	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4302	+ VOP_CLUSTER_SET(vop2, win, enable, 0);
	4303	+ }
	4304	+
	4305	+ vop2_cfg_done(crtc);
	4306	+ vop2_wait_for_fs_by_done_bit_status(vp);
	4307	+ drm_crtc_vblank_off(crtc);
	4308	+ if (hweight8(vop2->active_vp_mask) == 1) {
	4309	+ u32 adjust_aclk_rate = 0;
	4310	+ u32 htotal = (VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16) & 0xffff;
	4311	+ u32 pre_scan_dly = VOP_MODULE_GET(vop2, vp, pre_scan_htiming);
	4312	+ u32 pre_scan_hblank = pre_scan_dly & 0x1fff;
	4313	+ u32 pre_scan_hactive = (pre_scan_dly >> 16) & 0x1fff;
	4314	+ u32 dclk_rate = crtc->state->adjusted_mode.crtc_clock / 1000;
	4315	+ /**
	4316	+ * (pre_scan_hblank + pre_scan_hactive) x aclk_margin / adjust_aclk_rate = hotal / dclk_rate
	4317	+ * aclk_margin = 1.2, so
	4318	+ * adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) x 1.2 * aclk_margin / htotal
	4319	+ */
	4320	+
	4321	+ adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) * dclk_rate * 12 / 10 / htotal;
	4322	+
	4323	+ vop2->aclk_rate = clk_get_rate(vop2->aclk);
	4324	+ clk_set_rate(vop2->aclk, adjust_aclk_rate * 1000000L);
	4325	+ vop2->aclk_rate_reset = true;
	4326	+ }
	4327	+}
	4328	+
	4329	+static void vop2_crtc_atomic_exit_psr(struct drm_crtc crtc, struct drm_crtc_state old_state)
	4330	+{
	4331	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4332	+ struct vop2 *vop2 = vp->vop2;
	4333	+ u32 phys_id;
	4334	+ struct vop2_win *win;
	4335	+ unsigned long enabled_win_mask = vp->enabled_win_mask;
	4336	+
	4337	+ drm_crtc_vblank_on(crtc);
	4338	+ if (vop2->aclk_rate_reset)
	4339	+ clk_set_rate(vop2->aclk, vop2->aclk_rate);
	4340	+ vop2->aclk_rate_reset = false;
	4341	+
	4342	+ for_each_set_bit(phys_id, &enabled_win_mask, ROCKCHIP_MAX_LAYER) {
	4343	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	4344	+ VOP_WIN_SET(vop2, win, enable, 1);
	4345	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4346	+ VOP_CLUSTER_SET(vop2, win, enable, 1);
	4347	+ }
	4348	+
	4349	+ vop2_cfg_done(crtc);
	4350	+ vop2_wait_for_fs_by_done_bit_status(vp);
3147	4351	}
3148	4352
3149	4353	static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
3150	4354	struct drm_crtc_state *old_state)
3151	4355	{
3152	4356	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4357	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3153	4358	struct vop2 *vop2 = vp->vop2;
	4359	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	4360	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	4361	+ bool dual_channel = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE);
3154	4362	int ret;
3155	4363
3156	4364	WARN_ON(vp->event);
	4365	+
	4366	+ if (crtc->state->self_refresh_active) {
	4367	+ vop2_crtc_atomic_enter_psr(crtc, old_state);
	4368	+ goto out;
	4369	+ }
	4370	+
3157	4371	vop2_lock(vop2);
3158	4372	DRM_DEV_INFO(vop2->dev, "Crtc atomic disable vp%d\n", vp->id);
	4373	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 0);
	4374	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 0);
3159	4375	drm_crtc_vblank_off(crtc);
	4376	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4377	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4378	+ vop2->data->nr_dscs) {
	4379	+ if (dual_channel) {
	4380	+ vop2_crtc_disable_dsc(vop2, 0);
	4381	+ vop2_crtc_disable_dsc(vop2, 1);
	4382	+ } else {
	4383	+ vop2_crtc_disable_dsc(vop2, vcstate->dsc_id);
	4384	+ }
	4385	+ }
3160	4386
3161	4387	if (vp->cubic_lut) {
3162	4388	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
3163	4389	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 0);
3164	4390	}
3165	4391
	4392	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	4393	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
3166	4394	vop2_disable_all_planes_for_crtc(crtc);
3167	4395
	4396	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4397	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4398	+ vop2->data->nr_dscs && vop2->dscs[vcstate->dsc_id].pd) {
	4399	+ if (dual_channel) {
	4400	+ vop2_power_domain_put(vop2->dscs[0].pd);
	4401	+ vop2_power_domain_put(vop2->dscs[1].pd);
	4402	+ vop2->dscs[0].pd->vp_mask = 0;
	4403	+ vop2->dscs[1].pd->vp_mask = 0;
	4404	+ vop2->dscs[0].attach_vp_id = -1;
	4405	+ vop2->dscs[1].attach_vp_id = -1;
	4406	+ } else {
	4407	+ vop2_power_domain_put(vop2->dscs[vcstate->dsc_id].pd);
	4408	+ vop2->dscs[vcstate->dsc_id].pd->vp_mask = 0;
	4409	+ vop2->dscs[vcstate->dsc_id].attach_vp_id = -1;
	4410	+ }
	4411	+ vop2->dscs[vcstate->dsc_id].enabled = false;
	4412	+ vcstate->dsc_enable = false;
	4413	+ }
	4414	+
	4415	+ if (vp->output_if & VOP_OUTPUT_IF_eDP0)
	4416	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 0);
	4417	+
	4418	+ if (vp->output_if & VOP_OUTPUT_IF_eDP1) {
	4419	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 0);
	4420	+ if (dual_channel)
	4421	+ VOP_CTRL_SET(vop2, edp_dual_en, 0);
	4422	+ }
	4423	+
	4424	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI0) {
	4425	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 0);
	4426	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 0);
	4427	+ }
	4428	+
	4429	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI1) {
	4430	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 0);
	4431	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 0);
	4432	+ if (dual_channel)
	4433	+ VOP_CTRL_SET(vop2, hdmi_dual_en, 0);
	4434	+ }
	4435	+
	4436	+ if ((vcstate->output_if & VOP_OUTPUT_IF_DP1) && dual_channel)
	4437	+ VOP_CTRL_SET(vop2, dp_dual_en, 0);
	4438	+
	4439	+ if ((vcstate->output_if & VOP_OUTPUT_IF_MIPI1) && dual_channel)
	4440	+ VOP_CTRL_SET(vop2, mipi_dual_en, 0);
	4441	+
	4442	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 0);
	4443	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 0);
	4444	+
	4445	+ vp->output_if = 0;
	4446	+
	4447	+ vop2_clk_set_parent_extend(vp, vcstate, false);
3168	4448	/*
3169	4449	* Vop standby will take effect at end of current frame,
3170	4450	* if dsp hold valid irq happen, it means standby complete.
..	..	@@ -3177,6 +4457,8 @@
3177	4457
3178	4458	spin_lock(&vop2->reg_lock);
3179	4459
	4460	+ VOP_MODULE_SET(vop2, vp, splice_en, 0);
	4461	+
3180	4462	VOP_MODULE_SET(vop2, vp, standby, 1);
3181	4463
3182	4464	spin_unlock(&vop2->reg_lock);
..	..	@@ -3188,11 +4470,21 @@
3188	4470	vop2_dsp_hold_valid_irq_disable(crtc);
3189	4471
3190	4472	vop2_disable(crtc);
3191		- vop2_unlock(vop2);
3192	4473
3193	4474	vop2->active_vp_mask &= ~BIT(vp->id);
	4475	+ if (vcstate->splice_mode)
	4476	+ vop2->active_vp_mask &= ~BIT(splice_vp->id);
	4477	+ vcstate->splice_mode = false;
	4478	+ vcstate->output_flags = 0;
	4479	+ vp->splice_mode_right = false;
	4480	+ vp->loader_protect = false;
	4481	+ splice_vp->splice_mode_right = false;
	4482	+ memset(&vp->active_tv_state, 0, sizeof(vp->active_tv_state));
	4483	+ vop2_unlock(vop2);
	4484	+
3194	4485	vop2_set_system_status(vop2);
3195	4486
	4487	+out:
3196	4488	if (crtc->state->event && !crtc->state->active) {
3197	4489	spin_lock_irq(&crtc->dev->event_lock);
3198	4490	drm_crtc_send_vblank_event(crtc, crtc->state->event);
..	..	@@ -3202,23 +4494,241 @@
3202	4494	}
3203	4495	}
3204	4496
	4497	+static int vop2_cluster_two_win_mode_check(struct drm_plane_state *pstate)
	4498	+{
	4499	+ struct drm_atomic_state *state = pstate->state;
	4500	+ struct drm_plane *plane = pstate->plane;
	4501	+ struct vop2_win *win = to_vop2_win(plane);
	4502	+ struct vop2 *vop2 = win->vop2;
	4503	+ struct vop2_win *main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
	4504	+ struct drm_plane_state *main_pstate;
	4505	+ int actual_w = drm_rect_width(&pstate->src) >> 16;
	4506	+ int xoffset;
	4507	+
	4508	+ if (pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4509	+ xoffset = 0;
	4510	+ else
	4511	+ xoffset = pstate->src.x1 >> 16;
	4512	+
	4513	+ if ((actual_w + xoffset % 16) > 2048) {
	4514	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4515	+ win->name, actual_w, xoffset);
	4516	+ return -EINVAL;
	4517	+ }
	4518	+
	4519	+ main_pstate = drm_atomic_get_new_plane_state(state, &main_win->base);
	4520	+
	4521	+ if (pstate->fb->modifier != main_pstate->fb->modifier) {
	4522	+ DRM_ERROR("%s(fb->modifier: 0x%llx) must use same data layout as %s(fb->modifier: 0x%llx)\n",
	4523	+ win->name, pstate->fb->modifier, main_win->name, main_pstate->fb->modifier);
	4524	+ return -EINVAL;
	4525	+ }
	4526	+
	4527	+ if (main_pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4528	+ xoffset = 0;
	4529	+ else
	4530	+ xoffset = main_pstate->src.x1 >> 16;
	4531	+ actual_w = drm_rect_width(&main_pstate->src) >> 16;
	4532	+
	4533	+ if ((actual_w + xoffset % 16) > 2048) {
	4534	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4535	+ main_win->name, actual_w, xoffset);
	4536	+ return -EINVAL;
	4537	+ }
	4538	+
	4539	+ return 0;
	4540	+}
	4541	+
	4542	+static int vop2_cluter_splice_scale_check(struct vop2_win win, struct drm_plane_state pstate,
	4543	+ u16 hdisplay)
	4544	+{
	4545	+ struct drm_rect src = drm_plane_state_src(pstate);
	4546	+ struct drm_rect dst = drm_plane_state_dest(pstate);
	4547	+ u16 half_hdisplay = hdisplay >> 1;
	4548	+
	4549	+ /* scale up is ok */
	4550	+ if ((drm_rect_width(&src) >> 16) <= drm_rect_width(&dst))
	4551	+ return 0;
	4552	+
	4553	+ if ((drm_rect_width(&src) >> 16) <= VOP2_MAX_VP_OUTPUT_WIDTH)
	4554	+ return 0;
	4555	+ /*
	4556	+ * Cluster scale down limitation in splice mode:
	4557	+ * If scale down, must display at horizontal center
	4558	+ */
	4559	+ if ((dst.x1 < half_hdisplay) && (dst.x2 > half_hdisplay)) {
	4560	+ if ((dst.x2 + dst.x1) != hdisplay) {
	4561	+ DRM_ERROR("%s src_w: %d dst_w %d dst(%d %d) must scale down at center in splice mode\n",
	4562	+ win->name, drm_rect_width(&src) >> 16,
	4563	+ drm_rect_width(&dst), dst.x1, dst.x2);
	4564	+ return -EINVAL;
	4565	+ }
	4566	+
	4567	+ if (drm_rect_calc_hscale(&src, &dst, 1, FRAC_16_16(6, 5)) < 0) {
	4568	+ DRM_ERROR("%s %d --> %d scale down factor should < 1.2 in splice mode\n",
	4569	+ win->name, drm_rect_width(&src) >> 16, drm_rect_width(&dst));
	4570	+ return -EINVAL;
	4571	+ }
	4572	+ }
	4573	+
	4574	+ return 0;
	4575	+}
	4576	+
	4577	+static int vop2_plane_splice_check(struct drm_plane plane, struct drm_plane_state pstate,
	4578	+ struct drm_display_mode *mode)
	4579	+{
	4580	+ struct vop2_win *win = to_vop2_win(plane);
	4581	+ int ret = 0;
	4582	+
	4583	+ if (!(win->feature & WIN_FEATURE_SPLICE_LEFT)) {
	4584	+ DRM_ERROR("%s can't be left win in splice mode\n", win->name);
	4585	+ return -EINVAL;
	4586	+ }
	4587	+
	4588	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4589	+ DRM_ERROR("%s can't use two win mode in splice mode\n", win->name);
	4590	+ return -EINVAL;
	4591	+ }
	4592	+
	4593	+ if ((pstate->rotation & DRM_MODE_ROTATE_270) \|\|
	4594	+ (pstate->rotation & DRM_MODE_ROTATE_90) \|\|
	4595	+ (pstate->rotation & DRM_MODE_REFLECT_X)) {
	4596	+ DRM_ERROR("%s can't rotate 270/90 and xmirror in splice mode\n", win->name);
	4597	+ return -EINVAL;
	4598	+ }
	4599	+
	4600	+ /* check for cluster splice scale down */
	4601	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4602	+ ret = vop2_cluter_splice_scale_check(win, pstate, mode->hdisplay);
	4603	+
	4604	+ return ret;
	4605	+}
	4606	+
	4607	+/*
	4608	+ * 1. NV12/NV16/YUYV xoffset must aligned as 2 pixel;
	4609	+ * 2. NV12/NV15 yoffset must aligned as 2 pixel;
	4610	+ * 3. NV30 xoffset must aligned as 4 pixel;
	4611	+ * 4. NV15/NV20 xoffset must aligend as 8 pixel at rk3568/rk3588/rk3528/rk3562,
	4612	+ * others must aligned as 4 pixel;
	4613	+ */
	4614	+static int vop2_linear_yuv_format_check(struct drm_plane plane, struct drm_plane_state state)
	4615	+{
	4616	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(state);
	4617	+ struct drm_crtc *crtc = state->crtc;
	4618	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4619	+ struct vop2_win *win = to_vop2_win(plane);
	4620	+ struct drm_framebuffer *fb = state->fb;
	4621	+ struct drm_rect *src = &vpstate->src;
	4622	+ u32 val = 0;
	4623	+
	4624	+ if (vpstate->afbc_en \|\| vpstate->tiled_en \|\| !fb->format->is_yuv)
	4625	+ return 0;
	4626	+
	4627	+ switch (fb->format->format) {
	4628	+ case DRM_FORMAT_NV12:
	4629	+ case DRM_FORMAT_NV21:
	4630	+ val = src->x1 >> 16;
	4631	+ if (val % 2) {
	4632	+ src->x1 = ALIGN(val, 2) << 16;
	4633	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 2 pixel at NV12 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4634	+ }
	4635	+ val = src->y1 >> 16;
	4636	+ if (val % 2) {
	4637	+ src->y1 = ALIGN(val, 2) << 16;
	4638	+ DRM_WARN("VP%d %s src y offset[%d] must aligned as 2 pixel at NV12 fmt, and adjust to: %d\n", vp->id, win->name, val, src->y1 >> 16);
	4639	+ }
	4640	+ break;
	4641	+ case DRM_FORMAT_NV15:
	4642	+ val = src->y1 >> 16;
	4643	+ if (val % 2) {
	4644	+ src->y1 = ALIGN(val, 2) << 16;
	4645	+ DRM_WARN("VP%d %s src y offset[%d] must aligned as 2 pixel at NV15 fmt, and adjust to: %d\n", vp->id, win->name, val, src->y1 >> 16);
	4646	+ }
	4647	+ if (vp->vop2->version == VOP_VERSION_RK3568 \|\|
	4648	+ vp->vop2->version == VOP_VERSION_RK3588 \|\|
	4649	+ vp->vop2->version == VOP_VERSION_RK3528 \|\|
	4650	+ vp->vop2->version == VOP_VERSION_RK3562) {
	4651	+ val = src->x1 >> 16;
	4652	+ if (val % 8) {
	4653	+ src->x1 = ALIGN(val, 8) << 16;
	4654	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 8 pixel at NV15 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4655	+ }
	4656	+ } else {
	4657	+ val = src->x1 >> 16;
	4658	+ if (val % 4) {
	4659	+ src->x1 = ALIGN(val, 4) << 16;
	4660	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 4 pixel at NV15 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4661	+ }
	4662	+ }
	4663	+ break;
	4664	+ case DRM_FORMAT_NV16:
	4665	+ case DRM_FORMAT_NV61:
	4666	+ case DRM_FORMAT_YUYV:
	4667	+ case DRM_FORMAT_YVYU:
	4668	+ case DRM_FORMAT_VYUY:
	4669	+ case DRM_FORMAT_UYVY:
	4670	+ val = src->x1 >> 16;
	4671	+ if (val % 2) {
	4672	+ src->x1 = ALIGN(val, 2) << 16;
	4673	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 2 pixel at YUYV fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4674	+ }
	4675	+ break;
	4676	+ case DRM_FORMAT_NV20:
	4677	+ if (vp->vop2->version == VOP_VERSION_RK3568 \|\|
	4678	+ vp->vop2->version == VOP_VERSION_RK3588 \|\|
	4679	+ vp->vop2->version == VOP_VERSION_RK3528 \|\|
	4680	+ vp->vop2->version == VOP_VERSION_RK3562) {
	4681	+ val = src->x1 >> 16;
	4682	+ if (val % 8) {
	4683	+ src->x1 = ALIGN(val, 8) << 16;
	4684	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 8 pixel at NV20 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4685	+ }
	4686	+ } else {
	4687	+ val = src->x1 >> 16;
	4688	+ if (val % 4) {
	4689	+ src->x1 = ALIGN(val, 4) << 16;
	4690	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 4 pixel at NV20 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4691	+ }
	4692	+ }
	4693	+ break;
	4694	+ case DRM_FORMAT_NV30:
	4695	+ val = src->x1 >> 16;
	4696	+ if (val % 4) {
	4697	+ src->x1 = ALIGN(val, 4) << 16;
	4698	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 4 pixel at NV30 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4699	+ }
	4700	+ break;
	4701	+ default:
	4702	+ return 0;
	4703	+ }
	4704	+
	4705	+ return 0;
	4706	+}
	4707	+
3205	4708	static int vop2_plane_atomic_check(struct drm_plane plane, struct drm_plane_state state)
3206	4709	{
3207	4710	struct vop2_plane_state *vpstate = to_vop2_plane_state(state);
3208	4711	struct vop2_win *win = to_vop2_win(plane);
	4712	+ struct vop2_win *splice_win;
	4713	+ struct vop2 *vop2 = win->vop2;
3209	4714	struct drm_framebuffer *fb = state->fb;
	4715	+ struct drm_display_mode *mode;
3210	4716	struct drm_crtc *crtc = state->crtc;
3211	4717	struct drm_crtc_state *cstate;
	4718	+ struct rockchip_crtc_state *vcstate;
3212	4719	struct vop2_video_port *vp;
3213	4720	const struct vop2_data *vop2_data;
3214	4721	struct drm_rect *dest = &vpstate->dest;
3215	4722	struct drm_rect *src = &vpstate->src;
	4723	+ struct drm_gem_object obj, uv_obj;
	4724	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
3216	4725	int min_scale = win->regs->scl ? FRAC_16_16(1, 8) : DRM_PLANE_HELPER_NO_SCALING;
3217	4726	int max_scale = win->regs->scl ? FRAC_16_16(8, 1) : DRM_PLANE_HELPER_NO_SCALING;
3218	4727	uint32_t tile_size = 1;
	4728	+ int max_input_w;
	4729	+ int max_input_h;
3219	4730	unsigned long offset;
3220	4731	dma_addr_t dma_addr;
3221		- void *kvaddr;
3222	4732	int ret;
3223	4733
3224	4734	crtc = crtc ? crtc : plane->state->crtc;
..	..	@@ -3234,6 +4744,26 @@
3234	4744	if (WARN_ON(!cstate))
3235	4745	return -EINVAL;
3236	4746
	4747	+ mode = &cstate->mode;
	4748	+ vcstate = to_rockchip_crtc_state(cstate);
	4749	+
	4750	+ max_input_w = vop2_data->max_input.width;
	4751	+ max_input_h = vop2_data->max_input.height;
	4752	+
	4753	+ if (vop2_has_feature(win->vop2, VOP_FEATURE_SPLICE)) {
	4754	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	4755	+ vcstate->splice_mode = true;
	4756	+ ret = vop2_plane_splice_check(plane, state, mode);
	4757	+ if (ret < 0)
	4758	+ return ret;
	4759	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	4760	+ splice_win->splice_mode_right = true;
	4761	+ splice_win->left_win = win;
	4762	+ win->splice_win = splice_win;
	4763	+ max_input_w <<= 1;
	4764	+ }
	4765	+ }
	4766	+
3237	4767	vpstate->xmirror_en = (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0;
3238	4768	vpstate->ymirror_en = (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0;
3239	4769	vpstate->rotate_270_en = (state->rotation & DRM_MODE_ROTATE_270) ? 1 : 0;
..	..	@@ -3243,7 +4773,6 @@
3243	4773	DRM_ERROR("Can't rotate 90 and 270 at the same time\n");
3244	4774	return -EINVAL;
3245	4775	}
3246		-
3247	4776
3248	4777	ret = drm_atomic_helper_check_plane_state(state, cstate,
3249	4778	min_scale, max_scale,
..	..	@@ -3284,13 +4813,13 @@
3284	4813	return 0;
3285	4814	}
3286	4815
3287		- if (drm_rect_width(src) >> 16 > vop2_data->max_input.width \|\|
3288		- drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
	4816	+ if (drm_rect_width(src) >> 16 > max_input_w \|\|
	4817	+ drm_rect_height(src) >> 16 > max_input_h) {
3289	4818	DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
3290	4819	drm_rect_width(src) >> 16,
3291	4820	drm_rect_height(src) >> 16,
3292		- vop2_data->max_input.width,
3293		- vop2_data->max_input.height);
	4821	+ max_input_w,
	4822	+ max_input_h);
3294	4823	return -EINVAL;
3295	4824	}
3296	4825
..	..	@@ -3313,23 +4842,40 @@
3313	4842	* This is special feature at rk356x, the cluster layer only can support
3314	4843	* afbc format and can't support linear format;
3315	4844	*/
3316		- if (VOP_MAJOR(vop2_data->version) == 0x40 && VOP_MINOR(vop2_data->version) == 0x15) {
	4845	+ if (vp->vop2->version == VOP_VERSION_RK3568) {
3317	4846	if (vop2_cluster_window(win) && !vpstate->afbc_en) {
3318	4847	DRM_ERROR("Unsupported linear format at %s\n", win->name);
3319	4848	return -EINVAL;
3320	4849	}
3321	4850	}
3322	4851
3323		- /*
3324		- * Src.x1 can be odd when do clip, but yuv plane start point
3325		- * need align with 2 pixel.
3326		- */
3327		- if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
3328		- DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
3329		- return -EINVAL;
	4852	+ if (vp->vop2->version > VOP_VERSION_RK3568) {
	4853	+ if (vop2_cluster_window(win) && !vpstate->afbc_en && fb->format->is_yuv && !is_vop3(vop2)) {
	4854	+ DRM_ERROR("Unsupported linear yuv format at %s\n", win->name);
	4855	+ return -EINVAL;
	4856	+ }
	4857	+
	4858	+ if (vop2_cluster_window(win) && !vpstate->afbc_en &&
	4859	+ (win->supported_rotations & state->rotation)) {
	4860	+ DRM_ERROR("Unsupported linear rotation(%d) format at %s\n",
	4861	+ state->rotation, win->name);
	4862	+ return -EINVAL;
	4863	+ }
3330	4864	}
3331	4865
3332		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[0] / 8 * tile_size;
	4866	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4867	+ ret = vop2_cluster_two_win_mode_check(state);
	4868	+ if (ret < 0)
	4869	+ return ret;
	4870	+ }
	4871	+
	4872	+ if (vop2_linear_yuv_format_check(plane, state))
	4873	+ return -EINVAL;
	4874	+
	4875	+ if (fb->format->char_per_block[0] == 0)
	4876	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[0] * tile_size;
	4877	+ else
	4878	+ offset = drm_format_info_min_pitch(fb->format, 0, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size;
3333	4879	vpstate->offset = offset + fb->offsets[0];
3334	4880
3335	4881	/*
..	..	@@ -3342,30 +4888,33 @@
3342	4888	else
3343	4889	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[0];
3344	4890
3345		- dma_addr = rockchip_fb_get_dma_addr(fb, 0);
3346		- kvaddr = rockchip_fb_get_kvaddr(fb, 0);
	4891	+ obj = fb->obj[0];
	4892	+ rk_obj = to_rockchip_obj(obj);
3347	4893
3348		- vpstate->yrgb_mst = dma_addr + offset + fb->offsets[0];
3349		- vpstate->yrgb_kvaddr = kvaddr + offset + fb->offsets[0];
3350		- if (fb->format->is_yuv) {
3351		- int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
3352		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
	4894	+ vpstate->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
	4895	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	4896	+ int hsub = fb->format->hsub;
	4897	+ int vsub = fb->format->vsub;
3353	4898
3354		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[1] / hsub / 8 * tile_size;
	4899	+ if (fb->format->char_per_block[0] == 0)
	4900	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[1] / hsub * tile_size;
	4901	+ else
	4902	+ offset = drm_format_info_min_pitch(fb->format, 1, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size / hsub;
	4903	+
3355	4904	if (vpstate->tiled_en)
3356	4905	offset /= vsub;
3357	4906	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[1] / vsub;
	4907	+
	4908	+ uv_obj = fb->obj[1];
	4909	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	4910	+
3358	4911	if (vpstate->ymirror_en && !vpstate->afbc_en)
3359	4912	offset += fb->pitches[1] * ((state->src_h >> 16) - 2) / vsub;
3360		- dma_addr = rockchip_fb_get_dma_addr(fb, 1);
3361		- dma_addr += offset + fb->offsets[1];
	4913	+ dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
3362	4914	vpstate->uv_mst = dma_addr;
3363		-
3364	4915	/* tile 4x4 m0 format, y and uv is packed together */
3365		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0) {
	4916	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0)
3366	4917	vpstate->yrgb_mst += offset;
3367		- vpstate->yrgb_kvaddr += offset;
3368		- }
3369	4918	}
3370	4919
3371	4920	return 0;
..	..	@@ -3375,19 +4924,30 @@
3375	4924	{
3376	4925	struct vop2_win *win = to_vop2_win(plane);
3377	4926	struct vop2 *vop2 = win->vop2;
	4927	+ struct drm_crtc *crtc;
	4928	+ struct vop2_video_port *vp;
	4929	+
3378	4930	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
3379	4931	struct vop2_plane_state *vpstate = to_vop2_plane_state(plane->state);
3380	4932	#endif
3381	4933
3382		- DRM_DEV_DEBUG(vop2->dev, "%s disable\n", win->name);
	4934	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE, "%s disable %s\n",
	4935	+ win->name, current->comm);
3383	4936
3384	4937	if (!old_state->crtc)
3385	4938	return;
3386	4939
3387	4940	spin_lock(&vop2->reg_lock);
3388	4941
3389		- vop2_win_disable(win);
3390		- VOP_WIN_SET(vop2, win, yuv_clip, 0);
	4942	+ crtc = old_state->crtc;
	4943	+ vp = to_vop2_video_port(crtc);
	4944	+
	4945	+ vop2_win_disable(win, false);
	4946	+ vp->enabled_win_mask &= ~BIT(win->phys_id);
	4947	+ if (win->splice_win) {
	4948	+ vop2_win_disable(win->splice_win, false);
	4949	+ vp->enabled_win_mask &= ~BIT(win->splice_win->phys_id);
	4950	+ }
3391	4951
3392	4952	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
3393	4953	kfree(vpstate->planlist);
..	..	@@ -3451,6 +5011,64 @@
3451	5011	VOP_WIN_SET(vop2, win, color_key, color_key);
3452	5012	}
3453	5013
	5014	+static void vop2_calc_drm_rect_for_splice(struct vop2_plane_state *vpstate,
	5015	+ struct drm_rect left_src, struct drm_rect left_dst,
	5016	+ struct drm_rect right_src, struct drm_rect right_dst)
	5017	+{
	5018	+ struct drm_crtc *crtc = vpstate->base.crtc;
	5019	+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	5020	+ struct drm_rect *dst = &vpstate->dest;
	5021	+ struct drm_rect *src = &vpstate->src;
	5022	+ u16 half_hdisplay = mode->crtc_hdisplay >> 1;
	5023	+ int hscale = drm_rect_calc_hscale(src, dst, 0, INT_MAX);
	5024	+ int dst_w = drm_rect_width(dst);
	5025	+ int src_w = drm_rect_width(src) >> 16;
	5026	+ int left_src_w, left_dst_w, right_dst_w;
	5027	+ struct drm_plane_state *pstate = &vpstate->base;
	5028	+ struct drm_framebuffer *fb = pstate->fb;
	5029	+
	5030	+ left_dst_w = min_t(u16, half_hdisplay, dst->x2) - dst->x1;
	5031	+ if (left_dst_w < 0)
	5032	+ left_dst_w = 0;
	5033	+ right_dst_w = dst_w - left_dst_w;
	5034	+
	5035	+ if (!right_dst_w)
	5036	+ left_src_w = src_w;
	5037	+ else
	5038	+ left_src_w = (left_dst_w * hscale) >> 16;
	5039	+
	5040	+ /*
	5041	+ * Make sure the yrgb/uv mst of right win are byte aligned
	5042	+ * with full pixel.
	5043	+ */
	5044	+ if (right_dst_w) {
	5045	+ if (fb->format->format == DRM_FORMAT_NV15)
	5046	+ left_src_w &= ~0x7;
	5047	+ else if (fb->format->format == DRM_FORMAT_NV12)
	5048	+ left_src_w &= ~0x1;
	5049	+ }
	5050	+ left_src->x1 = src->x1;
	5051	+ left_src->x2 = src->x1 + (left_src_w << 16);
	5052	+ left_dst->x1 = dst->x1;
	5053	+ left_dst->x2 = dst->x1 + left_dst_w;
	5054	+ right_src->x1 = left_src->x2;
	5055	+ right_src->x2 = src->x2;
	5056	+ right_dst->x1 = dst->x1 + left_dst_w - half_hdisplay;
	5057	+ if (right_dst->x1 < 0)
	5058	+ right_dst->x1 = 0;
	5059	+
	5060	+ right_dst->x2 = right_dst->x1 + right_dst_w;
	5061	+
	5062	+ left_src->y1 = src->y1;
	5063	+ left_src->y2 = src->y2;
	5064	+ left_dst->y1 = dst->y1;
	5065	+ left_dst->y2 = dst->y2;
	5066	+ right_src->y1 = src->y1;
	5067	+ right_src->y2 = src->y2;
	5068	+ right_dst->y1 = dst->y1;
	5069	+ right_dst->y2 = dst->y2;
	5070	+}
	5071	+
3454	5072	static void rk3588_vop2_win_cfg_axi(struct vop2_win *win)
3455	5073	{
3456	5074	struct vop2 *vop2 = win->vop2;
..	..	@@ -3485,49 +5103,316 @@
3485	5103	}
3486	5104	}
3487	5105
	5106	+static void vop2_win_atomic_update(struct vop2_win win, struct drm_rect src, struct drm_rect *dst,
	5107	+ struct drm_plane_state *pstate)
	5108	+{
	5109	+ struct drm_crtc *crtc = pstate->crtc;
	5110	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5111	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	5112	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	5113	+ struct vop2 *vop2 = win->vop2;
	5114	+ struct drm_framebuffer *fb = pstate->fb;
	5115	+ struct drm_rect *left_src = &vpstate->src;
	5116	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
	5117	+ uint32_t actual_w, actual_h, dsp_w, dsp_h;
	5118	+ uint32_t dsp_stx, dsp_sty;
	5119	+ uint32_t act_info, dsp_info, dsp_st;
	5120	+ uint32_t format, check_size;
	5121	+ uint32_t afbc_format;
	5122	+ uint32_t rb_swap;
	5123	+ uint32_t uv_swap;
	5124	+ uint32_t afbc_half_block_en;
	5125	+ uint32_t afbc_tile_num;
	5126	+ uint32_t lb_mode;
	5127	+ uint32_t stride, uv_stride = 0;
	5128	+ uint32_t transform_offset;
	5129	+ /* offset of the right window in splice mode */
	5130	+ uint32_t splice_pixel_offset = 0;
	5131	+ uint32_t splice_yrgb_offset = 0;
	5132	+ uint32_t splice_uv_offset = 0;
	5133	+ uint32_t afbc_xoffset;
	5134	+ uint32_t hsub;
	5135	+ dma_addr_t yrgb_mst;
	5136	+ dma_addr_t uv_mst;
	5137	+
	5138	+ struct drm_format_name_buf format_name;
	5139	+ bool dither_up;
	5140	+ bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
	5141	+
	5142	+ actual_w = drm_rect_width(src) >> 16;
	5143	+ actual_h = drm_rect_height(src) >> 16;
	5144	+
	5145	+ if (!actual_w \|\| !actual_h) {
	5146	+ vop2_win_disable(win, true);
	5147	+ return;
	5148	+ }
	5149	+
	5150	+ dsp_w = drm_rect_width(dst);
	5151	+ /*
	5152	+ * This win is for the right part of the plane,
	5153	+ * we need calculate the fb offset for it.
	5154	+ */
	5155	+ if (win->splice_mode_right) {
	5156	+ splice_pixel_offset = (src->x1 - left_src->x1) >> 16;
	5157	+ splice_yrgb_offset = drm_format_info_min_pitch(fb->format, 0, splice_pixel_offset);
	5158	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	5159	+ hsub = fb->format->hsub;
	5160	+ splice_uv_offset = drm_format_info_min_pitch(fb->format, 1, splice_pixel_offset / hsub);
	5161	+ }
	5162	+ }
	5163	+
	5164	+ if (dst->x1 + dsp_w > adjusted_mode->crtc_hdisplay) {
	5165	+ DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
	5166	+ vp->id, win->name, dst->x1, dsp_w, adjusted_mode->crtc_hdisplay);
	5167	+ dsp_w = adjusted_mode->crtc_hdisplay - dst->x1;
	5168	+ if (dsp_w < 4)
	5169	+ dsp_w = 4;
	5170	+ actual_w = dsp_w * actual_w / drm_rect_width(dst);
	5171	+ }
	5172	+ dsp_h = drm_rect_height(dst);
	5173	+ check_size = adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE ? adjusted_mode->vdisplay : adjusted_mode->crtc_vdisplay;
	5174	+ if (dst->y1 + dsp_h > check_size) {
	5175	+ DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
	5176	+ vp->id, win->name, dst->y1, dsp_h, adjusted_mode->crtc_vdisplay);
	5177	+ dsp_h = adjusted_mode->crtc_vdisplay - dst->y1;
	5178	+ if (dsp_h < 4)
	5179	+ dsp_h = 4;
	5180	+ actual_h = dsp_h * actual_h / drm_rect_height(dst);
	5181	+ }
	5182	+
	5183	+ /*
	5184	+ * Workaround only for rk3568 vop
	5185	+ */
	5186	+ if (vop2->version == VOP_VERSION_RK3568) {
	5187	+ /*
	5188	+ * This is workaround solution for IC design:
	5189	+ * esmart can't support scale down when actual_w % 16 == 1;
	5190	+ * esmart can't support scale down when dsp_w % 2 == 1;
	5191	+ * esmart actual_w should align as 4 pixel when is linear 10 bit yuv format;
	5192	+ *
	5193	+ * cluster actual_w should align as 4 pixel when enable afbc;
	5194	+ */
	5195	+ if (!vop2_cluster_window(win)) {
	5196	+ if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
	5197	+ DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1 at scale down mode\n", vp->id, win->name, actual_w);
	5198	+ actual_w -= 1;
	5199	+ }
	5200	+ if (actual_w > dsp_w && (dsp_w & 0x1) == 1) {
	5201	+ DRM_WARN("vp%d %s dsp_w[%d] MODE 2 == 1 at scale down mode\n", vp->id, win->name, dsp_w);
	5202	+ dsp_w -= 1;
	5203	+ }
	5204	+ }
	5205	+
	5206	+ if (vop2_cluster_window(win) && actual_w % 4) {
	5207	+ DRM_WARN("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
	5208	+ vp->id, win->name, actual_w);
	5209	+ actual_w = ALIGN_DOWN(actual_w, 4);
	5210	+ }
	5211	+ }
	5212	+
	5213	+ if (is_linear_10bit_yuv(fb->format->format) && actual_w & 0x3) {
	5214	+ DRM_WARN("vp%d %s actual_w[%d] should align as 4 pixel when is linear 10 bit yuv format\n", vp->id, win->name, actual_w);
	5215	+ actual_w = ALIGN_DOWN(actual_w, 4);
	5216	+ }
	5217	+
	5218	+ act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
	5219	+ dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
	5220	+ stride = DIV_ROUND_UP(fb->pitches[0], 4);
	5221	+ dsp_stx = dst->x1;
	5222	+ dsp_sty = dst->y1;
	5223	+ dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
	5224	+
	5225	+ if (vpstate->tiled_en) {
	5226	+ if (is_vop3(vop2))
	5227	+ format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
	5228	+ else
	5229	+ format = vop2_convert_tiled_format(fb->format->format);
	5230	+ } else {
	5231	+ format = vop2_convert_format(fb->format->format);
	5232	+ }
	5233	+
	5234	+ vop2_setup_csc_mode(vp, vpstate);
	5235	+
	5236	+ afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
	5237	+
	5238	+ vop2_win_enable(win);
	5239	+ spin_lock(&vop2->reg_lock);
	5240	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
	5241	+ "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad] by %s\n",
	5242	+ vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
	5243	+ dsp_stx, dsp_sty,
	5244	+ drm_get_format_name(fb->format->format, &format_name),
	5245	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
	5246	+
	5247	+ if (vop2->version != VOP_VERSION_RK3568)
	5248	+ rk3588_vop2_win_cfg_axi(win);
	5249	+
	5250	+ if (!win->parent && !vop2_cluster_window(win) && is_vop3(vop2))
	5251	+ VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
	5252	+
	5253	+ if (vpstate->afbc_en) {
	5254	+ /* the afbc superblock is 16 x 16 */
	5255	+ afbc_format = vop2_convert_afbc_format(fb->format->format);
	5256	+ /* Enable color transform for YTR */
	5257	+ if (fb->modifier & AFBC_FORMAT_MOD_YTR)
	5258	+ afbc_format \|= (1 << 4);
	5259	+ afbc_tile_num = ALIGN(actual_w, 16) >> 4;
	5260	+
	5261	+ /* The right win should have a src offset in splice mode */
	5262	+ afbc_xoffset = (src->x1 >> 16);
	5263	+ /* AFBC pic_vir_width is count by pixel, this is different
	5264	+ * with WIN_VIR_STRIDE.
	5265	+ */
	5266	+ if (!bpp) {
	5267	+ WARN(1, "bpp is zero\n");
	5268	+ bpp = 1;
	5269	+ }
	5270	+ stride = (fb->pitches[0] << 3) / bpp;
	5271	+ if ((stride & 0x3f) &&
	5272	+ (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
	5273	+ DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
	5274	+ vp->id, win->name, stride, pstate->rotation);
	5275	+
	5276	+ rb_swap = vop2_afbc_rb_swap(fb->format->format);
	5277	+ uv_swap = vop2_afbc_uv_swap(fb->format->format);
	5278	+ vpstate->afbc_half_block_en = afbc_half_block_en;
	5279	+
	5280	+ transform_offset = vop2_afbc_transform_offset(vpstate, splice_pixel_offset);
	5281	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
	5282	+ VOP_AFBC_SET(vop2, win, format, afbc_format);
	5283	+ VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
	5284	+ VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
	5285	+
	5286	+ if (vop2->version == VOP_VERSION_RK3568)
	5287	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
	5288	+ else
	5289	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
	5290	+ VOP_AFBC_SET(vop2, win, block_split_en, 0);
	5291	+ VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
	5292	+ VOP_AFBC_SET(vop2, win, pic_size, act_info);
	5293	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5294	+ VOP_AFBC_SET(vop2, win, pic_offset, (afbc_xoffset \| src->y1));
	5295	+ VOP_AFBC_SET(vop2, win, dsp_offset, (dst->x1 \| (dst->y1 << 16)));
	5296	+ VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
	5297	+ VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
	5298	+ VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5299	+ VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5300	+ VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
	5301	+ VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
	5302	+ } else {
	5303	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
	5304	+ transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
	5305	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5306	+ VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5307	+ VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5308	+ }
	5309	+
	5310	+ if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
	5311	+ act_info = swahw32(act_info);
	5312	+ actual_w = drm_rect_height(src) >> 16;
	5313	+ actual_h = drm_rect_width(src) >> 16;
	5314	+ }
	5315	+
	5316	+ yrgb_mst = vpstate->yrgb_mst + splice_yrgb_offset;
	5317	+ uv_mst = vpstate->uv_mst + splice_uv_offset;
	5318	+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
	5319	+ VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
	5320	+
	5321	+ VOP_WIN_SET(vop2, win, format, format);
	5322	+ VOP_WIN_SET(vop2, win, yrgb_mst, yrgb_mst);
	5323	+
	5324	+ rb_swap = vop2_win_rb_swap(fb->format->format);
	5325	+ uv_swap = vop2_win_uv_swap(fb->format->format);
	5326	+ if (vpstate->tiled_en) {
	5327	+ uv_swap = 1;
	5328	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5329	+ stride <<= 3;
	5330	+ else
	5331	+ stride <<= 2;
	5332	+ }
	5333	+ VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
	5334	+ VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
	5335	+
	5336	+ if (fb->format->is_yuv) {
	5337	+ uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
	5338	+ if (vpstate->tiled_en) {
	5339	+ int vsub = fb->format->vsub;
	5340	+
	5341	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5342	+ uv_stride = uv_stride * 8 / vsub;
	5343	+ else
	5344	+ uv_stride = uv_stride * 4 / vsub;
	5345	+ VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
	5346	+ }
	5347	+
	5348	+ VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
	5349	+ VOP_WIN_SET(vop2, win, uv_mst, uv_mst);
	5350	+ }
	5351	+
	5352	+ /* tile 4x4 m0 format, y and uv is packed together */
	5353	+ if (tile_4x4_m0)
	5354	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
	5355	+ else
	5356	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride);
	5357	+
	5358	+ vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
	5359	+ vop2_plane_setup_color_key(&win->base);
	5360	+ VOP_WIN_SET(vop2, win, act_info, act_info);
	5361	+ VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
	5362	+ VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
	5363	+
	5364	+ VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
	5365	+ VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
	5366	+ VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
	5367	+
	5368	+ if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
	5369	+ VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
	5370	+
	5371	+ dither_up = vop2_win_dither_up(fb->format->format);
	5372	+ VOP_WIN_SET(vop2, win, dither_up, dither_up);
	5373	+
	5374	+ VOP_WIN_SET(vop2, win, enable, 1);
	5375	+ vp->enabled_win_mask \|= BIT(win->phys_id);
	5376	+ if (vop2_cluster_window(win)) {
	5377	+ lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
	5378	+ VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
	5379	+ VOP_CLUSTER_SET(vop2, win, scl_lb_mode, lb_mode == 1 ? 3 : 0);
	5380	+ VOP_CLUSTER_SET(vop2, win, enable, 1);
	5381	+ VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
	5382	+ }
	5383	+ spin_unlock(&vop2->reg_lock);
	5384	+}
	5385	+
3488	5386	static void vop2_plane_atomic_update(struct drm_plane plane, struct drm_plane_state old_state)
3489	5387	{
3490	5388	struct drm_plane_state *pstate = plane->state;
3491	5389	struct drm_crtc *crtc = pstate->crtc;
3492	5390	struct vop2_win *win = to_vop2_win(plane);
	5391	+ struct vop2_win *splice_win;
3493	5392	struct vop2_video_port *vp = to_vop2_video_port(crtc);
3494	5393	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
3495		- struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
3496	5394	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3497		- struct vop2 *vop2 = win->vop2;
3498	5395	struct drm_framebuffer *fb = pstate->fb;
3499		- uint32_t bpp = fb->format->bpp[0];
3500		- uint32_t actual_w, actual_h, dsp_w, dsp_h;
3501		- uint32_t dsp_stx, dsp_sty;
3502		- uint32_t act_info, dsp_info, dsp_st;
3503		- uint32_t format;
3504		- uint32_t afbc_format;
3505		- uint32_t rb_swap;
3506		- uint32_t uv_swap;
3507		- struct drm_rect *src = &vpstate->src;
3508		- struct drm_rect *dest = &vpstate->dest;
3509		- uint32_t afbc_tile_num;
3510		- uint32_t afbc_half_block_en;
3511		- uint32_t lb_mode;
3512		- uint32_t stride, uv_stride = 0;
3513		- uint32_t transform_offset;
3514	5396	struct drm_format_name_buf format_name;
3515		- bool dither_up;
3516		- bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
	5397	+ struct vop2 *vop2 = win->vop2;
	5398	+ struct drm_rect wsrc;
	5399	+ struct drm_rect wdst;
	5400	+ /* right part in splice mode */
	5401	+ struct drm_rect right_wsrc;
	5402	+ struct drm_rect right_wdst;
3517	5403
3518	5404	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
	5405	+ struct drm_rect *psrc = &vpstate->src;
3519	5406	bool AFBC_flag = false;
3520	5407	struct vop_dump_list *planlist;
3521	5408	unsigned long num_pages;
3522	5409	struct page **pages;
3523		- struct rockchip_drm_fb *rk_fb;
3524	5410	struct drm_gem_object *obj;
3525	5411	struct rockchip_gem_object *rk_obj;
3526	5412
3527	5413	num_pages = 0;
3528	5414	pages = NULL;
3529		- rk_fb = to_rockchip_fb(fb);
3530		- obj = rk_fb->obj[0];
	5415	+ obj = fb->obj[0];
3531	5416	rk_obj = to_rockchip_obj(obj);
3532	5417	if (rk_obj) {
3533	5418	num_pages = rk_obj->num_pages;
..	..	@@ -3566,211 +5451,24 @@
3566	5451	vp->skip_vsync = false;
3567	5452	}
3568	5453
3569		- actual_w = drm_rect_width(src) >> 16;
3570		- actual_h = drm_rect_height(src) >> 16;
3571		- dsp_w = drm_rect_width(dest);
3572		- if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
3573		- DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
3574		- vp->id, win->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
3575		- dsp_w = adjusted_mode->hdisplay - dest->x1;
3576		- if (dsp_w < 4)
3577		- dsp_w = 4;
3578		- actual_w = dsp_w * actual_w / drm_rect_width(dest);
3579		- }
3580		- dsp_h = drm_rect_height(dest);
3581		- if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
3582		- DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
3583		- vp->id, win->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
3584		- dsp_h = adjusted_mode->vdisplay - dest->y1;
3585		- if (dsp_h < 4)
3586		- dsp_h = 4;
3587		- actual_h = dsp_h * actual_h / drm_rect_height(dest);
3588		- }
	5454	+ if (vcstate->splice_mode) {
	5455	+ DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d,%d)] fmt[%.4s%s] addr[%pad]\n",
	5456	+ vp->id, win->name, drm_rect_width(&vpstate->src) >> 16,
	5457	+ drm_rect_height(&vpstate->src) >> 16,
	5458	+ drm_rect_width(&vpstate->dest), drm_rect_height(&vpstate->dest),
	5459	+ vpstate->dest.x1, vpstate->dest.y1,
	5460	+ drm_get_format_name(fb->format->format, &format_name),
	5461	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
3589	5462
3590		- /*
3591		- * This is workaround solution for IC design:
3592		- * esmart can't support scale down when actual_w % 16 == 1.
3593		- */
3594		- if (!(win->feature & WIN_FEATURE_AFBDC)) {
3595		- if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
3596		- DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
3597		- actual_w -= 1;
3598		- }
3599		- }
3600		-
3601		- if (vpstate->afbc_en && actual_w % 4) {
3602		- DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
3603		- vp->id, win->name, actual_w);
3604		- actual_w = ALIGN_DOWN(actual_w, 4);
3605		- }
3606		-
3607		- act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
3608		- dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
3609		- stride = DIV_ROUND_UP(fb->pitches[0], 4);
3610		- dsp_stx = dest->x1;
3611		- dsp_sty = dest->y1;
3612		- dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
3613		-
3614		- if (vpstate->tiled_en) {
3615		- if (is_vop3(vop2))
3616		- format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
3617		- else
3618		- format = vop2_convert_tiled_format(fb->format->format);
	5463	+ vop2_calc_drm_rect_for_splice(vpstate, &wsrc, &wdst, &right_wsrc, &right_wdst);
	5464	+ splice_win = win->splice_win;
	5465	+ vop2_win_atomic_update(splice_win, &right_wsrc, &right_wdst, pstate);
3619	5466	} else {
3620		- format = vop2_convert_format(fb->format->format);
	5467	+ memcpy(&wsrc, &vpstate->src, sizeof(struct drm_rect));
	5468	+ memcpy(&wdst, &vpstate->dest, sizeof(struct drm_rect));
3621	5469	}
3622	5470
3623		- vop2_setup_csc_mode(vp, vpstate);
3624		- afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
3625		-
3626		- spin_lock(&vop2->reg_lock);
3627		- DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%.4s%s] addr[%pad] zpos[%d]\n",
3628		- vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
3629		- dsp_stx, dsp_sty,
3630		- drm_get_format_name(fb->format->format, &format_name),
3631		- modifier_to_string(fb->modifier), &vpstate->yrgb_mst, vpstate->zpos);
3632		-
3633		- if (vop2->version != VOP_VERSION_RK3568)
3634		- rk3588_vop2_win_cfg_axi(win);
3635		-
3636		- if (is_vop3(vop2) && !vop2_cluster_window(win))
3637		- VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
3638		-
3639		- if (vpstate->afbc_en) {
3640		- /* the afbc superblock is 16 x 16 */
3641		- afbc_format = vop2_convert_afbc_format(fb->format->format);
3642		- /* Enable color transform for YTR */
3643		- if (fb->modifier & AFBC_FORMAT_MOD_YTR)
3644		- afbc_format \|= (1 << 4);
3645		- afbc_tile_num = ALIGN(actual_w, 16) >> 4;
3646		- /* AFBC pic_vir_width is count by pixel, this is different
3647		- * with WIN_VIR_STRIDE.
3648		- */
3649		- if (!bpp) {
3650		- WARN(1, "bpp is zero\n");
3651		- bpp = 1;
3652		- }
3653		- stride = (fb->pitches[0] << 3) / bpp;
3654		- if ((stride & 0x3f) &&
3655		- (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
3656		- DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
3657		- vp->id, win->name, stride, pstate->rotation);
3658		-
3659		- rb_swap = vop2_afbc_rb_swap(fb->format->format);
3660		- uv_swap = vop2_afbc_uv_swap(fb->format->format);
3661		- /*
3662		- * This is a workaround for crazy IC design, Cluster
3663		- * and Esmart/Smart use different format configuration map:
3664		- * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
3665		- *
3666		- * This is one thing we can make the convert simple:
3667		- * AFBCD decode all the YUV data to YUV444. So we just
3668		- * set all the yuv 10 bit to YUV444_10.
3669		- */
3670		- if (fb->format->is_yuv && (bpp == 10) && (vop2->version == VOP_VERSION_RK3568))
3671		- format = VOP2_CLUSTER_YUV444_10;
3672		-
3673		- vpstate->afbc_half_block_en = afbc_half_block_en;
3674		- transform_offset = vop2_afbc_transform_offset(vpstate);
3675		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
3676		- VOP_AFBC_SET(vop2, win, format, afbc_format);
3677		- VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
3678		- VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
3679		- if (vop2->version == VOP_VERSION_RK3568)
3680		- VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
3681		- else
3682		- VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
3683		- VOP_AFBC_SET(vop2, win, block_split_en, 0);
3684		- VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
3685		- VOP_AFBC_SET(vop2, win, pic_size, act_info);
3686		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3687		- VOP_AFBC_SET(vop2, win, pic_offset, ((src->x1 >> 16) \| src->y1));
3688		- VOP_AFBC_SET(vop2, win, dsp_offset, (dest->x1 \| (dest->y1 << 16)));
3689		- VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
3690		- VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
3691		- VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
3692		- VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
3693		- VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
3694		- VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
3695		- } else {
3696		- VOP_AFBC_SET(vop2, win, enable, 0);
3697		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
3698		- transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
3699		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3700		- VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
3701		- VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
3702		- }
3703		-
3704		- if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
3705		- act_info = swahw32(act_info);
3706		- actual_w = drm_rect_height(src) >> 16;
3707		- actual_h = drm_rect_width(src) >> 16;
3708		- }
3709		- VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
3710		-
3711		- VOP_WIN_SET(vop2, win, format, format);
3712		- VOP_WIN_SET(vop2, win, yrgb_mst, vpstate->yrgb_mst);
3713		-
3714		- rb_swap = vop2_win_rb_swap(fb->format->format);
3715		- uv_swap = vop2_win_uv_swap(fb->format->format);
3716		- if (vpstate->tiled_en) {
3717		- uv_swap = 1;
3718		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3719		- stride <<= 3;
3720		- else
3721		- stride <<= 2;
3722		- }
3723		- VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
3724		- VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
3725		-
3726		- if (fb->format->is_yuv) {
3727		- uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
3728		- if (vpstate->tiled_en) {
3729		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
3730		-
3731		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3732		- uv_stride = uv_stride * 8 / vsub;
3733		- else
3734		- uv_stride = uv_stride * 4 / vsub;
3735		- VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
3736		- }
3737		-
3738		- VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
3739		- VOP_WIN_SET(vop2, win, uv_mst, vpstate->uv_mst);
3740		- }
3741		-
3742		- /* tile 4x4 m0 format, y and uv is packed together */
3743		- if (tile_4x4_m0)
3744		- VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
3745		- else
3746		- VOP_WIN_SET(vop2, win, yrgb_vir, stride);
3747		-
3748		- vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
3749		- vop2_plane_setup_color_key(plane);
3750		- VOP_WIN_SET(vop2, win, act_info, act_info);
3751		- VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
3752		- VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
3753		-
3754		- VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
3755		- VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
3756		- VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
3757		-
3758		- if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
3759		- VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
3760		-
3761		- dither_up = vop2_win_dither_up(fb->format->format);
3762		- VOP_WIN_SET(vop2, win, dither_up, dither_up);
3763		-
3764		- VOP_WIN_SET(vop2, win, enable, 1);
3765		- if (vop2_cluster_window(win)) {
3766		- lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
3767		- VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
3768		- VOP_CLUSTER_SET(vop2, win, enable, 1);
3769		- }
3770		- if (vcstate->output_if & VOP_OUTPUT_IF_BT1120 \|\|
3771		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
3772		- VOP_WIN_SET(vop2, win, yuv_clip, 1);
3773		- spin_unlock(&vop2->reg_lock);
	5471	+ vop2_win_atomic_update(win, &wsrc, &wdst, pstate);
3774	5472
3775	5473	vop2->is_iommu_needed = true;
3776	5474	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
..	..	@@ -3787,18 +5485,18 @@
3787	5485	planlist->dump_info.pages = pages;
3788	5486	planlist->dump_info.offset = vpstate->offset;
3789	5487	planlist->dump_info.pitches = fb->pitches[0];
3790		- planlist->dump_info.height = actual_h;
3791		- planlist->dump_info.pixel_format = fb->format->format;
3792		- list_add_tail(&planlist->entry, &crtc->vop_dump_list_head);
	5488	+ planlist->dump_info.height = drm_rect_height(psrc) >> 16;
	5489	+ planlist->dump_info.format = fb->format;
	5490	+ list_add_tail(&planlist->entry, &vp->rockchip_crtc.vop_dump_list_head);
3793	5491	vpstate->planlist = planlist;
3794	5492	} else {
3795	5493	DRM_ERROR("can't alloc a node of planlist %p\n", planlist);
3796	5494	return;
3797	5495	}
3798		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
3799		- crtc->vop_dump_times > 0) {
3800		- vop_plane_dump(&planlist->dump_info, crtc->frame_count);
3801		- crtc->vop_dump_times--;
	5496	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	5497	+ vp->rockchip_crtc.vop_dump_times > 0) {
	5498	+ rockchip_drm_dump_plane_buffer(&planlist->dump_info, vp->rockchip_crtc.frame_count);
	5499	+ vp->rockchip_crtc.vop_dump_times--;
3802	5500	}
3803	5501	#endif
3804	5502	}
..	..	@@ -3944,11 +5642,8 @@
3944	5642	if (!vpstate)
3945	5643	return;
3946	5644
3947		- plane->state = &vpstate->base;
3948		- plane->state->plane = plane;
3949		- plane->state->zpos = win->zpos;
3950		- plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
3951		- plane->state->rotation = DRM_MODE_ROTATE_0;
	5645	+ __drm_atomic_helper_plane_reset(plane, &vpstate->base);
	5646	+ vpstate->base.zpos = win->zpos;
3952	5647	}
3953	5648
3954	5649	static struct drm_plane_state vop2_atomic_plane_duplicate_state(struct drm_plane plane)
..	..	@@ -4136,6 +5831,192 @@
4136	5831	spin_unlock_irqrestore(&drm->event_lock, flags);
4137	5832	}
4138	5833
	5834	+static bool vop2_crtc_line_flag_irq_is_enabled(struct vop2_video_port *vp)
	5835	+{
	5836	+ struct vop2 *vop2 = vp->vop2;
	5837	+ const struct vop2_data *vop2_data = vop2->data;
	5838	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5839	+ const struct vop_intr *intr = vp_data->intr;
	5840	+ uint32_t line_flag_irq;
	5841	+ unsigned long flags;
	5842	+
	5843	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5844	+ line_flag_irq = VOP_INTR_GET_TYPE(vop2, intr, enable, LINE_FLAG_INTR);
	5845	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5846	+
	5847	+ return !!line_flag_irq;
	5848	+}
	5849	+
	5850	+static void vop2_crtc_line_flag_irq_enable(struct vop2_video_port *vp)
	5851	+{
	5852	+ struct vop2 *vop2 = vp->vop2;
	5853	+ const struct vop2_data *vop2_data = vop2->data;
	5854	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5855	+ const struct vop_intr *intr = vp_data->intr;
	5856	+ unsigned long flags;
	5857	+
	5858	+ if (!vop2->is_enabled)
	5859	+ return;
	5860	+
	5861	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5862	+ VOP_INTR_SET_TYPE(vop2, intr, clear, LINE_FLAG_INTR, 1);
	5863	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 1);
	5864	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5865	+}
	5866	+
	5867	+static void vop2_crtc_line_flag_irq_disable(struct vop2_video_port *vp)
	5868	+{
	5869	+ struct vop2 *vop2 = vp->vop2;
	5870	+ const struct vop2_data *vop2_data = vop2->data;
	5871	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5872	+ const struct vop_intr *intr = vp_data->intr;
	5873	+ unsigned long flags;
	5874	+
	5875	+ if (!vop2->is_enabled)
	5876	+ return;
	5877	+
	5878	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5879	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 0);
	5880	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5881	+}
	5882	+
	5883	+static void vop3_mcu_mode_setup(struct drm_crtc *crtc)
	5884	+{
	5885	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5886	+ struct vop2 *vop2 = vp->vop2;
	5887	+
	5888	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5889	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5890	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, vp->mcu_timing.mcu_pix_total);
	5891	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, vp->mcu_timing.mcu_cs_pst);
	5892	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, vp->mcu_timing.mcu_cs_pend);
	5893	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, vp->mcu_timing.mcu_rw_pst);
	5894	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, vp->mcu_timing.mcu_rw_pend);
	5895	+}
	5896	+
	5897	+static void vop3_mcu_bypass_mode_setup(struct drm_crtc *crtc)
	5898	+{
	5899	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5900	+ struct vop2 *vop2 = vp->vop2;
	5901	+
	5902	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5903	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5904	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, 53);
	5905	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, 6);
	5906	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, 48);
	5907	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, 12);
	5908	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, 30);
	5909	+}
	5910	+
	5911	+static u32 vop3_mode_done(struct vop2_video_port *vp)
	5912	+{
	5913	+ return VOP_MODULE_GET(vp->vop2, vp, out_mode);
	5914	+}
	5915	+
	5916	+static void vop3_set_out_mode(struct drm_crtc *crtc, u32 out_mode)
	5917	+{
	5918	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5919	+ struct vop2 *vop2 = vp->vop2;
	5920	+ int ret;
	5921	+ u32 val;
	5922	+
	5923	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	5924	+ vop2_cfg_done(crtc);
	5925	+ ret = readx_poll_timeout(vop3_mode_done, vp, val, val == out_mode,
	5926	+ 1000, 500 * 1000);
	5927	+ if (ret)
	5928	+ dev_err(vop2->dev, "wait mode 0x%x timeout\n", out_mode);
	5929	+}
	5930	+
	5931	+static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value)
	5932	+{
	5933	+ struct drm_crtc_state *crtc_state;
	5934	+ struct drm_display_mode *adjusted_mode;
	5935	+ struct vop2_video_port *vp;
	5936	+ struct vop2 *vop2;
	5937	+
	5938	+ if (!crtc)
	5939	+ return;
	5940	+
	5941	+ crtc_state = crtc->state;
	5942	+ adjusted_mode = &crtc_state->adjusted_mode;
	5943	+ vp = to_vop2_video_port(crtc);
	5944	+ vop2 = vp->vop2;
	5945	+
	5946	+ /*
	5947	+ * 1.set mcu bypass mode timing.
	5948	+ * 2.set dclk rate to 150M.
	5949	+ */
	5950	+ if ((type == MCU_SETBYPASS) && value) {
	5951	+ vop3_mcu_bypass_mode_setup(crtc);
	5952	+ clk_set_rate(vp->dclk, 150000000);
	5953	+ }
	5954	+
	5955	+ mutex_lock(&vop2->vop2_lock);
	5956	+ if (vop2 && vop2->is_enabled) {
	5957	+ switch (type) {
	5958	+ case MCU_WRCMD:
	5959	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 0);
	5960	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5961	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5962	+ break;
	5963	+ case MCU_WRDATA:
	5964	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5965	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5966	+ break;
	5967	+ case MCU_SETBYPASS:
	5968	+ VOP_MODULE_SET(vop2, vp, mcu_bypass, value ? 1 : 0);
	5969	+ break;
	5970	+ default:
	5971	+ break;
	5972	+ }
	5973	+ }
	5974	+ mutex_unlock(&vop2->vop2_lock);
	5975	+
	5976	+ /*
	5977	+ * 1.restore mcu data mode timing.
	5978	+ * 2.restore dclk rate to crtc_clock.
	5979	+ */
	5980	+ if ((type == MCU_SETBYPASS) && !value) {
	5981	+ vop3_mcu_mode_setup(crtc);
	5982	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	5983	+ }
	5984	+}
	5985	+
	5986	+static int vop2_crtc_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
	5987	+{
	5988	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5989	+ struct vop2 *vop2 = vp->vop2;
	5990	+ unsigned long jiffies_left;
	5991	+ int ret = 0;
	5992	+
	5993	+ if (!vop2->is_enabled)
	5994	+ return -ENODEV;
	5995	+
	5996	+ mutex_lock(&vop2->vop2_lock);
	5997	+
	5998	+ if (vop2_crtc_line_flag_irq_is_enabled(vp)) {
	5999	+ ret = -EBUSY;
	6000	+ goto out;
	6001	+ }
	6002	+
	6003	+ reinit_completion(&vp->line_flag_completion);
	6004	+ vop2_crtc_line_flag_irq_enable(vp);
	6005	+ jiffies_left = wait_for_completion_timeout(&vp->line_flag_completion,
	6006	+ msecs_to_jiffies(mstimeout));
	6007	+ vop2_crtc_line_flag_irq_disable(vp);
	6008	+
	6009	+ if (jiffies_left == 0) {
	6010	+ DRM_DEV_ERROR(vop2->dev, "timeout waiting for lineflag IRQ\n");
	6011	+ ret = -ETIMEDOUT;
	6012	+ goto out;
	6013	+ }
	6014	+
	6015	+out:
	6016	+ mutex_unlock(&vop2->vop2_lock);
	6017	+ return ret;
	6018	+}
	6019	+
4139	6020	static int vop2_crtc_enable_line_flag_event(struct drm_crtc *crtc, uint32_t line)
4140	6021	{
4141	6022	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -4179,21 +6060,129 @@
4179	6060	spin_unlock_irqrestore(&vop2->irq_lock, flags);
4180	6061	}
4181	6062
4182		-
4183		-static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on)
	6063	+static int vop2_crtc_get_inital_acm_info(struct drm_crtc *crtc)
4184	6064	{
4185	6065	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4186	6066	struct vop2 *vop2 = vp->vop2;
	6067	+ struct post_acm *acm = &vp->acm_info;
	6068	+ s16 *lut_y;
	6069	+ s16 *lut_h;
	6070	+ s16 *lut_s;
	6071	+ u32 value;
	6072	+ int i;
	6073	+
	6074	+ value = readl(vop2->acm_regs + RK3528_ACM_CTRL);
	6075	+ acm->acm_enable = value & 0x1;
	6076	+ value = readl(vop2->acm_regs + RK3528_ACM_DELTA_RANGE);
	6077	+ acm->y_gain = value & 0x3ff;
	6078	+ acm->h_gain = (value >> 10) & 0x3ff;
	6079	+ acm->s_gain = (value >> 20) & 0x3ff;
	6080	+
	6081	+ lut_y = &acm->gain_lut_hy[0];
	6082	+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
	6083	+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
	6084	+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
	6085	+ value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
	6086	+ lut_y[i] = value & 0xff;
	6087	+ lut_h[i] = (value >> 8) & 0xff;
	6088	+ lut_s[i] = (value >> 16) & 0xff;
	6089	+ }
	6090	+
	6091	+ lut_y = &acm->gain_lut_hs[0];
	6092	+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
	6093	+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
	6094	+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
	6095	+ value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
	6096	+ lut_y[i] = value & 0xff;
	6097	+ lut_h[i] = (value >> 8) & 0xff;
	6098	+ lut_s[i] = (value >> 16) & 0xff;
	6099	+ }
	6100	+
	6101	+ lut_y = &acm->delta_lut_h[0];
	6102	+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
	6103	+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
	6104	+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
	6105	+ value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
	6106	+ lut_y[i] = value & 0x3ff;
	6107	+ lut_h[i] = (value >> 12) & 0xff;
	6108	+ lut_s[i] = (value >> 20) & 0x3ff;
	6109	+ }
	6110	+
	6111	+ return 0;
	6112	+}
	6113	+
	6114	+static int vop2_crtc_loader_protect(struct drm_crtc crtc, bool on, void data)
	6115	+{
	6116	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6117	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6118	+ struct vop2 *vop2 = vp->vop2;
4187	6119	struct rockchip_drm_private *private = crtc->dev->dev_private;
	6120	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	6121	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	6122	+ struct drm_crtc_state *crtc_state;
	6123	+ struct drm_display_mode *mode;
	6124	+ struct vop2_win win, splice_win;
	6125	+ struct vop2_extend_pll *ext_pll;
	6126	+ struct clk *parent_clk;
	6127	+ const char *clk_name;
4188	6128
4189	6129	if (on == vp->loader_protect)
4190	6130	return 0;
4191	6131
4192	6132	if (on) {
	6133	+ vp->loader_protect = true;
4193	6134	vop2->active_vp_mask \|= BIT(vp->id);
4194	6135	vop2_set_system_status(vop2);
4195	6136	vop2_initial(crtc);
	6137	+ if (crtc->primary) {
	6138	+ win = to_vop2_win(crtc->primary);
	6139	+ if (VOP_WIN_GET(vop2, win, enable)) {
	6140	+ if (win->pd) {
	6141	+ win->pd->ref_count++;
	6142	+ win->pd->vp_mask \|= BIT(vp->id);
	6143	+ }
	6144	+
	6145	+ vp->enabled_win_mask \|= BIT(win->phys_id);
	6146	+ crtc_state = drm_atomic_get_crtc_state(crtc->state->state, crtc);
	6147	+ mode = &crtc_state->adjusted_mode;
	6148	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	6149	+ vcstate->splice_mode = true;
	6150	+ splice_win = vop2_find_win_by_phys_id(vop2,
	6151	+ win->splice_win_id);
	6152	+ splice_win->splice_mode_right = true;
	6153	+ splice_win->left_win = win;
	6154	+ win->splice_win = splice_win;
	6155	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	6156	+ splice_win->vp_mask = BIT(splice_vp->id);
	6157	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	6158	+ vp->enabled_win_mask \|= BIT(splice_win->phys_id);
	6159	+
	6160	+ if (splice_win->pd &&
	6161	+ VOP_WIN_GET(vop2, splice_win, enable)) {
	6162	+ splice_win->pd->ref_count++;
	6163	+ splice_win->pd->vp_mask \|= BIT(splice_vp->id);
	6164	+ }
	6165	+ }
	6166	+ }
	6167	+ }
	6168	+ parent_clk = clk_get_parent(vp->dclk);
	6169	+ clk_name = __clk_get_name(parent_clk);
	6170	+ if (!strcmp(clk_name, "clk_hdmiphy_pixel0")) {
	6171	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	6172	+ if (ext_pll)
	6173	+ ext_pll->vp_mask \|= BIT(vp->id);
	6174	+ } else if (!strcmp(clk_name, "clk_hdmiphy_pixel1")) {
	6175	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	6176	+ if (ext_pll)
	6177	+ ext_pll->vp_mask \|= BIT(vp->id);
	6178	+ }
4196	6179	drm_crtc_vblank_on(crtc);
	6180	+ if (is_vop3(vop2)) {
	6181	+ if (vp_data->feature & (VOP_FEATURE_POST_ACM))
	6182	+ vop2_crtc_get_inital_acm_info(crtc);
	6183	+ if (data && (vp_data->feature & VOP_FEATURE_POST_CSC))
	6184	+ memcpy(&vp->csc_info, data, sizeof(struct post_csc));
	6185	+ }
4197	6186	if (private->cubic_lut[vp->id].enable) {
4198	6187	dma_addr_t cubic_lut_mst;
4199	6188	struct loader_cubic_lut *cubic_lut = &private->cubic_lut[vp->id];
..	..	@@ -4201,10 +6190,8 @@
4201	6190	cubic_lut_mst = cubic_lut->offset + private->cubic_lut_dma_addr;
4202	6191	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
4203	6192	}
4204		- vp->loader_protect = true;
4205	6193	} else {
4206	6194	vop2_crtc_atomic_disable(crtc, NULL);
4207		- vp->loader_protect = false;
4208	6195	}
4209	6196
4210	6197	return 0;
..	..	@@ -4226,6 +6213,10 @@
4226	6213	struct drm_rect src, dest;
4227	6214	struct drm_framebuffer *fb = pstate->fb;
4228	6215	struct drm_format_name_buf format_name;
	6216	+ struct drm_gem_object *obj;
	6217	+ struct rockchip_gem_object *rk_obj;
	6218	+ dma_addr_t fb_addr;
	6219	+
4229	6220	int i;
4230	6221
4231	6222	DEBUG_PRINT(" %s: %s\n", win->name, pstate->crtc ? "ACTIVE" : "DISABLED");
..	..	@@ -4256,8 +6247,10 @@
4256	6247	DEBUG_PRINT("\tdst: pos[%d, %d] rect[%d x %d]\n", dest->x1, dest->y1,
4257	6248	drm_rect_width(dest), drm_rect_height(dest));
4258	6249
4259		- for (i = 0; i < drm_format_num_planes(fb->format->format); i++) {
4260		- dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
	6250	+ for (i = 0; i < fb->format->num_planes; i++) {
	6251	+ obj = fb->obj[0];
	6252	+ rk_obj = to_rockchip_obj(obj);
	6253	+ fb_addr = rk_obj->dma_addr + fb->offsets[0];
4261	6254
4262	6255	DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
4263	6256	i, &fb_addr, fb->pitches[i], fb->offsets[i]);
..	..	@@ -4337,8 +6330,8 @@
4337	6330
4338	6331	/* only need to dump once at first active crtc for vop2 */
4339	6332	for (i = 0; i < vop2_data->nr_vps; i++) {
4340		- if (vop2->vps[i].crtc.state->active) {
4341		- first_active_crtc = &vop2->vps[i].crtc;
	6333	+ if (vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6334	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4342	6335	break;
4343	6336	}
4344	6337	}
..	..	@@ -4380,8 +6373,8 @@
4380	6373
4381	6374	/* only need to dump once at first active crtc for vop2 */
4382	6375	for (i = 0; i < vop2_data->nr_vps; i++) {
4383		- if (vop2->vps[i].crtc.state->active) {
4384		- first_active_crtc = &vop2->vps[i].crtc;
	6376	+ if (vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6377	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4385	6378	break;
4386	6379	}
4387	6380	}
..	..	@@ -4417,7 +6410,7 @@
4417	6410	struct vop2_video_port *vp = &vop2->vps[i];
4418	6411
4419	6412	if (!vp->lut \|\| !vp->gamma_lut_active \|\|
4420		- !vop2->lut_regs \|\| !vp->crtc.state->enable) {
	6413	+ !vop2->lut_regs \|\| !vp->rockchip_crtc.crtc.state->enable) {
4421	6414	DEBUG_PRINT("Video port%d gamma disabled\n", vp->id);
4422	6415	continue;
4423	6416	}
..	..	@@ -4444,7 +6437,7 @@
4444	6437	struct vop2_video_port *vp = &vop2->vps[i];
4445	6438
4446	6439	if ((!vp->cubic_lut_gem_obj && !private->cubic_lut[vp->id].enable) \|\|
4447		- !vp->cubic_lut \|\| !vp->crtc.state->enable) {
	6440	+ !vp->cubic_lut \|\| !vp->rockchip_crtc.crtc.state->enable) {
4448	6441	DEBUG_PRINT("Video port%d cubic lut disabled\n", vp->id);
4449	6442	continue;
4450	6443	}
..	..	@@ -4487,24 +6480,17 @@
4487	6480	goto remove;
4488	6481	}
4489	6482	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4490		- drm_debugfs_vop_add(crtc, vop2->debugfs);
	6483	+ rockchip_drm_add_dump_buffer(crtc, vop2->debugfs);
	6484	+ rockchip_drm_debugfs_add_color_bar(crtc, vop2->debugfs);
4491	6485	#endif
4492	6486	for (i = 0; i < ARRAY_SIZE(vop2_debugfs_files); i++)
4493	6487	vop2->debugfs_files[i].data = vop2;
4494	6488
4495		- ret = drm_debugfs_create_files(vop2->debugfs_files,
4496		- ARRAY_SIZE(vop2_debugfs_files),
4497		- vop2->debugfs,
4498		- minor);
4499		- if (ret) {
4500		- dev_err(vop2->dev, "could not install rockchip_debugfs_list\n");
4501		- goto free;
4502		- }
4503		-
	6489	+ drm_debugfs_create_files(vop2->debugfs_files,
	6490	+ ARRAY_SIZE(vop2_debugfs_files),
	6491	+ vop2->debugfs,
	6492	+ minor);
4504	6493	return 0;
4505		-free:
4506		- kfree(vop2->debugfs_files);
4507		- vop2->debugfs_files = NULL;
4508	6494	remove:
4509	6495	debugfs_remove(vop2->debugfs);
4510	6496	vop2->debugfs = NULL;
..	..	@@ -4512,29 +6498,59 @@
4512	6498	}
4513	6499
4514	6500	static enum drm_mode_status
4515		-vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode,
4516		- int output_type)
	6501	+vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode)
4517	6502	{
	6503	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4518	6504	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4519	6505	struct vop2 *vop2 = vp->vop2;
4520	6506	const struct vop2_data *vop2_data = vop2->data;
4521	6507	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4522	6508	int request_clock = mode->clock;
4523	6509	int clock;
	6510	+ unsigned long aclk_rate;
	6511	+ uint8_t active_vp_mask = vop2->active_vp_mask;
	6512	+
	6513	+ /*
	6514	+ * For RK3588, VP0 and VP1 will be both used in splice mode. All display
	6515	+ * modes of the right VP should be set as invalid when vop2 is working in
	6516	+ * splice mode.
	6517	+ */
	6518	+ if (vp->splice_mode_right)
	6519	+ return MODE_BAD;
	6520	+
	6521	+ if ((active_vp_mask & BIT(ROCKCHIP_VOP_VP1)) && !vcstate->splice_mode &&
	6522	+ mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	6523	+ DRM_DEV_DEBUG(vop2->dev, "can not support resolution %dx%d, vp1 is busy\n",
	6524	+ mode->hdisplay, mode->vdisplay);
	6525	+ return MODE_BAD;
	6526	+ }
4524	6527
4525	6528	if (mode->hdisplay > vp_data->max_output.width)
4526	6529	return MODE_BAD_HVALUE;
4527	6530
4528		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6531	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4529	6532	request_clock *= 2;
4530	6533
4531		- clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6534	+ aclk_rate = clk_get_rate(vop2->aclk) / 1000;
	6535	+
	6536	+ if (request_clock > VOP2_MAX_DCLK_RATE && aclk_rate <= VOP2_COMMON_ACLK_RATE)
	6537	+ return MODE_BAD;
	6538	+
	6539	+ if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
	6540	+ (vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") \|\|
	6541	+ vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {
	6542	+ clock = request_clock;
	6543	+ } else {
	6544	+ if (request_clock > VOP2_MAX_DCLK_RATE)
	6545	+ request_clock = request_clock >> 2;
	6546	+ clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6547	+ }
4532	6548
4533	6549	/*
4534	6550	* Hdmi or DisplayPort request a Accurate clock.
4535	6551	*/
4536		- if (output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
4537		- output_type == DRM_MODE_CONNECTOR_DisplayPort)
	6552	+ if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
	6553	+ vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
4538	6554	if (clock != request_clock)
4539	6555	return MODE_CLOCK_RANGE;
4540	6556
..	..	@@ -4561,7 +6577,7 @@
4561	6577	struct drm_framebuffer *fb = pstate->fb;
4562	6578	struct drm_rect *dst = &vpstate->dest;
4563	6579	struct drm_rect *src = &vpstate->src;
4564		- int bpp = fb->format->bpp[0];
	6580	+ int bpp = rockchip_drm_get_bpp(fb->format);
4565	6581	int src_width = drm_rect_width(src) >> 16;
4566	6582	int src_height = drm_rect_height(src) >> 16;
4567	6583	int dst_width = drm_rect_width(dst);
..	..	@@ -4577,9 +6593,9 @@
4577	6593
4578	6594	bandwidth = bandwidth * src_width / dst_width;
4579	6595	bandwidth = bandwidth * src_height / dst_height;
4580		- if (vskiplines == 2)
	6596	+ if (vskiplines == 2 && vpstate->afbc_en == 0)
4581	6597	bandwidth /= 2;
4582		- else if (vskiplines == 4)
	6598	+ else if (vskiplines == 4 && vpstate->afbc_en == 0)
4583	6599	bandwidth /= 4;
4584	6600
4585	6601	return bandwidth;
..	..	@@ -4609,10 +6625,9 @@
4609	6625
4610	6626	static size_t vop2_crtc_bandwidth(struct drm_crtc *crtc,
4611	6627	struct drm_crtc_state *crtc_state,
4612		- size_t *frame_bw_mbyte,
4613		- unsigned int *plane_num_total)
	6628	+ struct dmcfreq_vop_info *vop_bw_info)
4614	6629	{
4615		- struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
	6630	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
4616	6631	uint16_t htotal = adjusted_mode->crtc_htotal;
4617	6632	uint16_t vdisplay = adjusted_mode->crtc_vdisplay;
4618	6633	int clock = adjusted_mode->crtc_clock;
..	..	@@ -4621,44 +6636,49 @@
4621	6636	struct drm_plane_state *pstate;
4622	6637	struct vop2_bandwidth *pbandwidth;
4623	6638	struct drm_plane *plane;
4624		- uint64_t line_bandwidth;
	6639	+ u64 line_bw_mbyte = 0;
4625	6640	int8_t cnt = 0, plane_num = 0;
	6641	+ int i = 0;
4626	6642	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4627	6643	struct vop_dump_list pos, n;
	6644	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
4628	6645	#endif
4629	6646
4630	6647	if (!htotal \|\| !vdisplay)
4631	6648	return 0;
4632	6649
4633	6650	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4634		- if (!crtc->vop_dump_list_init_flag) {
4635		- INIT_LIST_HEAD(&crtc->vop_dump_list_head);
4636		- crtc->vop_dump_list_init_flag = true;
	6651	+ if (!vp->rockchip_crtc.vop_dump_list_init_flag) {
	6652	+ INIT_LIST_HEAD(&vp->rockchip_crtc.vop_dump_list_head);
	6653	+ vp->rockchip_crtc.vop_dump_list_init_flag = true;
4637	6654	}
4638		- list_for_each_entry_safe(pos, n, &crtc->vop_dump_list_head, entry) {
	6655	+ list_for_each_entry_safe(pos, n, &vp->rockchip_crtc.vop_dump_list_head, entry) {
4639	6656	list_del(&pos->entry);
4640	6657	}
4641		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
4642		- crtc->vop_dump_times > 0) {
4643		- crtc->frame_count++;
	6658	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	6659	+ vp->rockchip_crtc.vop_dump_times > 0) {
	6660	+ vp->rockchip_crtc.frame_count++;
4644	6661	}
4645	6662	#endif
4646	6663
4647		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
4648		- plane_num++;
	6664	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6665	+ if (pstate->crtc == crtc)
	6666	+ plane_num++;
	6667	+ }
4649	6668
4650		- if (plane_num_total)
4651		- *plane_num_total += plane_num;
	6669	+ vop_bw_info->plane_num += plane_num;
4652	6670	pbandwidth = kmalloc_array(plane_num, sizeof(*pbandwidth),
4653	6671	GFP_KERNEL);
4654	6672	if (!pbandwidth)
4655	6673	return -ENOMEM;
4656		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
4657		- int act_w, act_h, bpp, afbc_fac;
4658	6674
4659		- pstate = drm_atomic_get_new_plane_state(state, plane);
	6675	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6676	+ int act_w, act_h, bpp, afbc_fac;
	6677	+ int fps = drm_mode_vrefresh(adjusted_mode);
	6678	+
4660	6679	if (!pstate \|\| pstate->crtc != crtc \|\| !pstate->fb)
4661	6680	continue;
	6681	+
4662	6682	/* This is an empirical value, if it's afbc format, the frame buffer size div 2 */
4663	6683	afbc_fac = rockchip_afbc(plane, pstate->fb->modifier) ? 2 : 1;
4664	6684
..	..	@@ -4669,24 +6689,28 @@
4669	6689
4670	6690	act_w = drm_rect_width(&pstate->src) >> 16;
4671	6691	act_h = drm_rect_height(&pstate->src) >> 16;
4672		- bpp = pstate->fb->format->bpp[0];
	6692	+ if (pstate->fb->format->is_yuv && (act_w >= 3840 \|\| act_h >= 3840))
	6693	+ vop_bw_info->plane_num_4k++;
4673	6694
4674		- frame_bw_mbyte += act_w act_h / 1000 * bpp / 8 * adjusted_mode->vrefresh / afbc_fac / 1000;
	6695	+ bpp = rockchip_drm_get_bpp(pstate->fb->format);
	6696	+
	6697	+ vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000 / afbc_fac;
4675	6698	}
4676	6699
4677	6700	sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop2_bandwidth_cmp, NULL);
4678	6701
4679		- line_bandwidth = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
	6702	+ line_bw_mbyte = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
4680	6703	kfree(pbandwidth);
4681	6704	/*
4682	6705	* line_bandwidth(MB/s)
4683		- * = line_bandwidth(Byte) / line_time(s)
	6706	+ * = line_bandwidth / line_time
4684	6707	* = line_bandwidth(Byte) * clock(KHZ) / 1000 / htotal
4685	6708	*/
4686		- line_bandwidth *= clock;
4687		- do_div(line_bandwidth, htotal * 1000);
	6709	+ line_bw_mbyte *= clock;
	6710	+ do_div(line_bw_mbyte, htotal * 1000);
	6711	+ vop_bw_info->line_bw_mbyte = line_bw_mbyte;
4688	6712
4689		- return line_bandwidth;
	6713	+ return 0;
4690	6714	}
4691	6715
4692	6716	static void vop2_crtc_close(struct drm_crtc *crtc)
..	..	@@ -4718,6 +6742,44 @@
4718	6742	VOP_MODULE_SET(vop2, vp, edpi_wms_fs, 1);
4719	6743	}
4720	6744
	6745	+static int vop2_crtc_set_color_bar(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode)
	6746	+{
	6747	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6748	+ struct vop2 *vop2 = vp->vop2;
	6749	+ int ret = 0;
	6750	+
	6751	+ if (!crtc->state->active) {
	6752	+ DRM_INFO("Video port%d disabled\n", vp->id);
	6753	+ return -EINVAL;
	6754	+ }
	6755	+
	6756	+ switch (mode) {
	6757	+ case ROCKCHIP_COLOR_BAR_OFF:
	6758	+ DRM_INFO("disable color bar in VP%d\n", vp->id);
	6759	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 0);
	6760	+ vop2_cfg_done(crtc);
	6761	+ break;
	6762	+ case ROCKCHIP_COLOR_BAR_HORIZONTAL:
	6763	+ DRM_INFO("enable horizontal color bar in VP%d\n", vp->id);
	6764	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 0);
	6765	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6766	+ vop2_cfg_done(crtc);
	6767	+ break;
	6768	+ case ROCKCHIP_COLOR_BAR_VERTICAL:
	6769	+ DRM_INFO("enable vertical color bar in VP%d\n", vp->id);
	6770	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 1);
	6771	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6772	+ vop2_cfg_done(crtc);
	6773	+ break;
	6774	+ default:
	6775	+ DRM_INFO("Unsupported color bar mode\n");
	6776	+ ret = -EINVAL;
	6777	+ break;
	6778	+ }
	6779	+
	6780	+ return ret;
	6781	+}
	6782	+
4721	6783	static const struct rockchip_crtc_funcs private_crtc_funcs = {
4722	6784	.loader_protect = vop2_crtc_loader_protect,
4723	6785	.cancel_pending_vblank = vop2_crtc_cancel_pending_vblank,
..	..	@@ -4725,10 +6787,13 @@
4725	6787	.debugfs_dump = vop2_crtc_debugfs_dump,
4726	6788	.regs_dump = vop2_crtc_regs_dump,
4727	6789	.active_regs_dump = vop2_crtc_active_regs_dump,
4728		- .mode_valid = vop2_crtc_mode_valid,
4729	6790	.bandwidth = vop2_crtc_bandwidth,
4730	6791	.crtc_close = vop2_crtc_close,
4731	6792	.te_handler = vop2_crtc_te_handler,
	6793	+ .crtc_send_mcu_cmd = vop3_crtc_send_mcu_cmd,
	6794	+ .wait_vact_end = vop2_crtc_wait_vact_end,
	6795	+ .crtc_standby = vop2_crtc_standby,
	6796	+ .crtc_set_color_bar = vop2_crtc_set_color_bar,
4732	6797	};
4733	6798
4734	6799	static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
..	..	@@ -4736,60 +6801,105 @@
4736	6801	struct drm_display_mode *adj_mode)
4737	6802	{
4738	6803	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6804	+ struct vop2 *vop2 = vp->vop2;
	6805	+ struct drm_connector *connector;
	6806	+ struct drm_connector_list_iter conn_iter;
	6807	+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
	6808	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(new_crtc_state);
	6809	+
	6810	+ /*
	6811	+ * For RK3568 and RK3588, the hactive of video timing must
	6812	+ * be 4-pixel aligned.
	6813	+ */
	6814	+ if (vop2->version == VOP_VERSION_RK3568 \|\| vop2->version == VOP_VERSION_RK3588) {
	6815	+ if (adj_mode->hdisplay % 4) {
	6816	+ u16 old_hdisplay = adj_mode->hdisplay;
	6817	+ u16 align;
	6818	+
	6819	+ align = 4 - (adj_mode->hdisplay % 4);
	6820	+ adj_mode->hdisplay += align;
	6821	+ adj_mode->hsync_start += align;
	6822	+ adj_mode->hsync_end += align;
	6823	+ adj_mode->htotal += align;
	6824	+
	6825	+ DRM_WARN("VP%d: hactive need to be aligned with 4-pixel, %d -> %d\n",
	6826	+ vp->id, old_hdisplay, adj_mode->hdisplay);
	6827	+ }
	6828	+ }
4739	6829
4740	6830	drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V \| CRTC_STEREO_DOUBLE);
4741	6831
4742		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6832	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4743	6833	adj_mode->crtc_clock *= 2;
4744	6834
4745		- adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
4746		- adj_mode->crtc_clock * 1000), 1000);
	6835	+ if (vp->mcu_timing.mcu_pix_total)
	6836	+ adj_mode->crtc_clock = rockchip_drm_get_cycles_per_pixel(vcstate->bus_format)
	6837	+ (vp->mcu_timing.mcu_pix_total + 1);
4747	6838
	6839	+ drm_connector_list_iter_begin(crtc->dev, &conn_iter);
	6840	+ drm_for_each_connector_iter(connector, &conn_iter) {
	6841	+ if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) &&
	6842	+ ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
	6843	+ (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) {
	6844	+ drm_connector_list_iter_end(&conn_iter);
	6845	+ return true;
	6846	+ }
	6847	+ }
	6848	+ drm_connector_list_iter_end(&conn_iter);
	6849	+
	6850	+ if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE)
	6851	+ adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
	6852	+ adj_mode->crtc_clock * 1000), 1000);
4748	6853	return true;
4749	6854	}
4750	6855
4751		-static void vop2_dither_setup(struct drm_crtc *crtc)
	6856	+static void vop2_dither_setup(struct rockchip_crtc_state vcstate, struct drm_crtc crtc)
4752	6857	{
4753		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4754	6858	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4755	6859	struct vop2 *vop2 = vp->vop2;
	6860	+ bool pre_dither_down_en = false;
4756	6861
4757	6862	switch (vcstate->bus_format) {
4758	6863	case MEDIA_BUS_FMT_RGB565_1X16:
4759	6864	VOP_MODULE_SET(vop2, vp, dither_down_en, 1);
4760	6865	VOP_MODULE_SET(vop2, vp, dither_down_mode, RGB888_TO_RGB565);
4761		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6866	+ pre_dither_down_en = true;
4762	6867	break;
4763	6868	case MEDIA_BUS_FMT_RGB666_1X18:
4764	6869	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
4765	6870	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
4766		- case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
4767	6871	VOP_MODULE_SET(vop2, vp, dither_down_en, 1);
4768	6872	VOP_MODULE_SET(vop2, vp, dither_down_mode, RGB888_TO_RGB666);
4769		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6873	+ pre_dither_down_en = true;
4770	6874	break;
	6875	+ case MEDIA_BUS_FMT_YUYV8_1X16:
4771	6876	case MEDIA_BUS_FMT_YUV8_1X24:
4772	6877	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
4773	6878	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4774		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6879	+ pre_dither_down_en = true;
4775	6880	break;
	6881	+ case MEDIA_BUS_FMT_YUYV10_1X20:
4776	6882	case MEDIA_BUS_FMT_YUV10_1X30:
4777	6883	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
4778	6884	case MEDIA_BUS_FMT_RGB101010_1X30:
4779	6885	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4780		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0);
	6886	+ pre_dither_down_en = false;
4781	6887	break;
4782		- case MEDIA_BUS_FMT_SRGB888_3X8:
4783		- case MEDIA_BUS_FMT_SRGB888_DUMMY_4X8:
	6888	+ case MEDIA_BUS_FMT_RGB888_3X8:
	6889	+ case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
4784	6890	case MEDIA_BUS_FMT_RGB888_1X24:
4785	6891	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
4786	6892	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
4787	6893	default:
4788	6894	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4789		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6895	+ pre_dither_down_en = true;
4790	6896	break;
4791	6897	}
4792	6898
	6899	+ if (is_yuv_output(vcstate->bus_format))
	6900	+ pre_dither_down_en = false;
	6901	+
	6902	+ VOP_MODULE_SET(vop2, vp, pre_dither_down_en, pre_dither_down_en);
4793	6903	VOP_MODULE_SET(vop2, vp, dither_down_sel, DITHER_DOWN_ALLEGRO);
4794	6904	}
4795	6905
..	..	@@ -4799,6 +6909,8 @@
4799	6909	to_rockchip_crtc_state(crtc->state);
4800	6910	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4801	6911	struct vop2 *vop2 = vp->vop2;
	6912	+ const struct vop2_data *vop2_data = vop2->data;
	6913	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4802	6914	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
4803	6915	u16 vtotal = mode->crtc_vtotal;
4804	6916	u16 hdisplay = mode->crtc_hdisplay;
..	..	@@ -4838,8 +6950,16 @@
4838	6950	val = vact_st_f1 << 16 \| vact_end_f1;
4839	6951	VOP_MODULE_SET(vop2, vp, vpost_st_end_f1, val);
4840	6952	}
4841		- VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y,
4842		- is_yuv_output(vcstate->bus_format));
	6953	+
	6954	+ /*
	6955	+ * BCSH[R2Y] -> POST Linebuffer[post scale] -> the background R2Y will be deal by post_dsp_out_r2y
	6956	+ *
	6957	+ * POST Linebuffer[post scale] -> ACM[R2Y] -> the background R2Y will be deal by ACM[R2Y]
	6958	+ */
	6959	+ if (vp_data->feature & VOP_FEATURE_POST_ACM)
	6960	+ VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y, vcstate->yuv_overlay);
	6961	+ else
	6962	+ VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y, is_yuv_output(vcstate->bus_format));
4843	6963	}
4844	6964
4845	6965	/*
..	..	@@ -4866,13 +6986,13 @@
4866	6986	u16 vact_end = vact_st + vdisplay;
4867	6987	u32 htotal_sync = htotal << 16 \| hsync_len;
4868	6988	u32 hactive_st_end = hact_st << 16 \| hact_end;
4869		- u32 vtotal_sync = vtotal << 16 \| vsync_len;
4870	6989	u32 vactive_st_end = vact_st << 16 \| vact_end;
4871	6990	u32 crtc_clock = adjusted_mode->crtc_clock * 100;
4872	6991
4873	6992	if (htotal_sync != VOP_MODULE_GET(vop2, vp, htotal_pw) \|\|
4874	6993	hactive_st_end != VOP_MODULE_GET(vop2, vp, hact_st_end) \|\|
4875		- vtotal_sync != VOP_MODULE_GET(vop2, vp, vtotal_pw) \|\|
	6994	+ vtotal != VOP_MODULE_GET(vop2, vp, dsp_vtotal) \|\|
	6995	+ vsync_len != VOP_MODULE_GET(vop2, vp, dsp_vs_end) \|\|
4876	6996	vactive_st_end != VOP_MODULE_GET(vop2, vp, vact_st_end) \|\|
4877	6997	crtc_clock != clk_get_rate(vp->dclk))
4878	6998	return true;
..	..	@@ -4880,15 +7000,719 @@
4880	7000	return false;
4881	7001	}
4882	7002
	7003	+static int vop2_cru_set_rate(struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	7004	+{
	7005	+ int ret = 0;
	7006	+
	7007	+ if (if_pixclk) {
	7008	+ ret = clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate);
	7009	+ if (ret < 0) {
	7010	+ DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n",
	7011	+ clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret);
	7012	+ return ret;
	7013	+ }
	7014	+ }
	7015	+
	7016	+ if (if_dclk) {
	7017	+ ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate);
	7018	+ if (ret < 0)
	7019	+ DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n",
	7020	+ clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret);
	7021	+ }
	7022	+
	7023	+ return ret;
	7024	+}
	7025	+
	7026	+static int vop2_set_dsc_clk(struct drm_crtc *crtc, u8 dsc_id)
	7027	+{
	7028	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7029	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7030	+ struct vop2 *vop2 = vp->vop2;
	7031	+ const struct vop2_data *vop2_data = vop2->data;
	7032	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	7033	+ struct vop2_clk dsc_txp_clk, dsc_pxl_clk, dsc_cds_clk, dsc_txp_clk_parent;
	7034	+ char clk_name[32];
	7035	+ int ret = 0;
	7036	+
	7037	+ /* set clk parent */
	7038	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	7039	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_src_name);
	7040	+ dsc_txp_clk_parent = vop2_clk_get(vop2, clk_name);
	7041	+ if (!dsc_txp_clk \|\| !dsc_txp_clk_parent) {
	7042	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc clk\n");
	7043	+ return -ENODEV;
	7044	+ }
	7045	+ ret = clk_set_parent(dsc_txp_clk->hw.clk, dsc_txp_clk_parent->hw.clk);
	7046	+ if (ret < 0) {
	7047	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	7048	+ __clk_get_name(dsc_txp_clk_parent->hw.clk),
	7049	+ __clk_get_name(dsc_txp_clk->hw.clk), ret);
	7050	+ return ret;
	7051	+ }
	7052	+
	7053	+ /* set dsc txp clk rate */
	7054	+ clk_set_rate(dsc_txp_clk->hw.clk, vcstate->dsc_txp_clk_rate);
	7055	+
	7056	+ /* set dsc pxl clk rate */
	7057	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	7058	+ if (!dsc_pxl_clk) {
	7059	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_pxl_clk\n");
	7060	+ return -ENODEV;
	7061	+ }
	7062	+ clk_set_rate(dsc_pxl_clk->hw.clk, vcstate->dsc_pxl_clk_rate);
	7063	+
	7064	+ /* set dsc cds clk rate */
	7065	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	7066	+ if (!dsc_cds_clk) {
	7067	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_cds_clk\n");
	7068	+ return -ENODEV;
	7069	+ }
	7070	+ clk_set_rate(dsc_cds_clk->hw.clk, vcstate->dsc_cds_clk_rate);
	7071	+
	7072	+ return 0;
	7073	+}
	7074	+
	7075	+static int vop2_calc_if_clk(struct drm_crtc crtc, const struct vop2_connector_if_data if_data,
	7076	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk, int conn_id)
	7077	+{
	7078	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7079	+ struct vop2 *vop2 = vp->vop2;
	7080	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7081	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7082	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	7083	+ unsigned long dclk_core_rate, dclk_out_rate = 0;
	7084	+ /conn_dclk = conn_pixclk or conn_dclk = conn_pixclk / 2 /
	7085	+ u64 hdmi_edp_pixclk, hdmi_edp_dclk, mipi_pixclk;
	7086	+ char dclk_core_div_shift = 2;
	7087	+ char K = 1;
	7088	+ char clk_name[32];
	7089	+ struct vop2_clk dclk_core, dclk_out, *dclk;
	7090	+ int ret;
	7091	+ bool dsc_txp_clk_is_biggest = false;
	7092	+ u8 dsc_id = conn_id & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	7093	+
	7094	+ dclk_core_div_shift = if_data->post_proc_div_shift;
	7095	+ dclk_core_rate = v_pixclk >> dclk_core_div_shift;
	7096	+
	7097	+ if (!if_dclk && (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id)))
	7098	+ return -EINVAL;
	7099	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) &&
	7100	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420)) {
	7101	+ DRM_DEV_ERROR(vop2->dev, "Dual channel and YUV420 can't work together\n");
	7102	+ return -EINVAL;
	7103	+ }
	7104	+
	7105	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) \|\|
	7106	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420))
	7107	+ K = 2;
	7108	+
	7109	+ if (output_if_is_hdmi(conn_id)) {
	7110	+ if (vcstate->dsc_enable) {
	7111	+ hdmi_edp_pixclk = vcstate->dsc_cds_clk_rate << 1;
	7112	+ hdmi_edp_dclk = vcstate->dsc_cds_clk_rate;
	7113	+ } else {
	7114	+ hdmi_edp_pixclk = (dclk_core_rate << 1) / K;
	7115	+ hdmi_edp_dclk = dclk_core_rate / K;
	7116	+ }
	7117	+
	7118	+ if_pixclk->rate = hdmi_edp_pixclk;
	7119	+ if_dclk->rate = hdmi_edp_dclk;
	7120	+ } else if (output_if_is_edp(conn_id)) {
	7121	+ hdmi_edp_pixclk = v_pixclk;
	7122	+ do_div(hdmi_edp_pixclk, K);
	7123	+ hdmi_edp_dclk = hdmi_edp_pixclk;
	7124	+
	7125	+ if_pixclk->rate = hdmi_edp_pixclk;
	7126	+ if_dclk->rate = hdmi_edp_dclk;
	7127	+ } else if (output_if_is_dp(conn_id)) {
	7128	+ dclk_out_rate = v_pixclk >> 2;
	7129	+ dclk_out_rate = dclk_out_rate / K;
	7130	+ if_pixclk->rate = dclk_out_rate;
	7131	+ } else if (output_if_is_mipi(conn_id)) {
	7132	+ if (vcstate->dsc_enable)
	7133	+ /* dsc output is 96bit, dsi input is 192 bit */
	7134	+ mipi_pixclk = vcstate->dsc_cds_clk_rate >> 1;
	7135	+ else
	7136	+ mipi_pixclk = dclk_core_rate / K;
	7137	+
	7138	+ dclk_out_rate = dclk_core_rate / K;
	7139	+ if_pixclk->rate = mipi_pixclk;
	7140	+ } else if (output_if_is_dpi(conn_id)) {
	7141	+ if_pixclk->rate = v_pixclk;
	7142	+ }
	7143	+
	7144	+ /*
	7145	+ * RGB/eDP/HDMI: if_pixclk >= dclk_core
	7146	+ * DP: dp_pixclk = dclk_out <= dclk_core
	7147	+ * DSI: mipi_pixclk <= dclk_out <= dclk_core
	7148	+ *
	7149	+ */
	7150	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7151	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7152	+
	7153	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	7154	+ dclk_out = vop2_clk_get(vop2, clk_name);
	7155	+
	7156	+ /*
	7157	+ * HDMI use 1:1 dclk for rgb/yuv444, 1:2 for yuv420 when
	7158	+ * pixclk <= 600
	7159	+ * We want use HDMI PHY clk as dclk source for DP/HDMI.
	7160	+ * The max freq of HDMI PHY CLK is 600 MHZ.
	7161	+ * When used for HDMI, the input freq and v_pixclk must
	7162	+ * keep 1:1 for rgb/yuv444, 1:2 for yuv420
	7163	+ */
	7164	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_dp(conn_id) \|\| output_if_is_mipi(conn_id)) {
	7165	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	7166	+ dclk = vop2_clk_get(vop2, clk_name);
	7167	+ if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) {
	7168	+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420 \|\|
	7169	+ (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE))
	7170	+ v_pixclk = v_pixclk >> 1;
	7171	+ } else {
	7172	+ v_pixclk = v_pixclk >> 2;
	7173	+ }
	7174	+ clk_set_rate(dclk->hw.clk, v_pixclk);
	7175	+ }
	7176	+
	7177	+ if (vcstate->dsc_enable) {
	7178	+ if ((vcstate->dsc_txp_clk_rate >= dclk_core_rate) &&
	7179	+ (vcstate->dsc_txp_clk_rate >= if_pixclk->rate)) {
	7180	+ dsc_txp_clk_is_biggest = true;
	7181	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	7182	+ vop2_set_dsc_clk(crtc, 0);
	7183	+ vop2_set_dsc_clk(crtc, 1);
	7184	+ } else {
	7185	+ vop2_set_dsc_clk(crtc, dsc_id);
	7186	+ }
	7187	+ }
	7188	+ }
	7189	+
	7190	+ if (dclk_core_rate > if_pixclk->rate) {
	7191	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	7192	+ if (output_if_is_mipi(conn_id))
	7193	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	7194	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	7195	+ } else {
	7196	+ if (output_if_is_mipi(conn_id))
	7197	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	7198	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	7199	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	7200	+ }
	7201	+
	7202	+ if (!dsc_txp_clk_is_biggest && vcstate->dsc_enable) {
	7203	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	7204	+ vop2_set_dsc_clk(crtc, 0);
	7205	+ vop2_set_dsc_clk(crtc, 1);
	7206	+ } else {
	7207	+ vop2_set_dsc_clk(crtc, dsc_id);
	7208	+ }
	7209	+ }
	7210	+
	7211	+ return ret;
	7212	+}
	7213	+
	7214	+static int vop2_calc_dsc_clk(struct drm_crtc *crtc)
	7215	+{
	7216	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7217	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7218	+ struct vop2 *vop2 = vp->vop2;
	7219	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7220	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	7221	+ u8 k = 1;
	7222	+
	7223	+ if (!vop2->data->nr_dscs) {
	7224	+ DRM_WARN("Unsupported DSC\n");
	7225	+
	7226	+ return 0;
	7227	+ }
	7228	+
	7229	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7230	+ k = 2;
	7231	+
	7232	+ vcstate->dsc_txp_clk_rate = v_pixclk;
	7233	+ do_div(vcstate->dsc_txp_clk_rate, (vcstate->dsc_pixel_num * k));
	7234	+
	7235	+ vcstate->dsc_pxl_clk_rate = v_pixclk;
	7236	+ do_div(vcstate->dsc_pxl_clk_rate, (vcstate->dsc_slice_num * k));
	7237	+
	7238	+ /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel)
	7239	+ * cds_dat_width = 96;
	7240	+ * bits_per_pixel = [8-12];
	7241	+ * As cds clk is div from txp clk and only support 1/2/4 div,
	7242	+ * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4,
	7243	+ * otherwise dsc_cds = crtc_clock / 8;
	7244	+ */
	7245	+ vcstate->dsc_cds_clk_rate = v_pixclk / (vcstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8);
	7246	+
	7247	+ return 0;
	7248	+}
	7249	+
	7250	+static int vop2_calc_cru_cfg(struct drm_crtc *crtc, int conn_id,
	7251	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	7252	+{
	7253	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7254	+ struct vop2 *vop2 = vp->vop2;
	7255	+ const struct vop2_connector_if_data *if_data;
	7256	+ struct vop2_clk if_clk_src, if_clk_parent;
	7257	+ char clk_name[32];
	7258	+ int ret;
	7259	+
	7260	+ if (vop2->version != VOP_VERSION_RK3588)
	7261	+ return 0;
	7262	+
	7263	+ if_data = vop2_find_connector_if_data(vop2, conn_id);
	7264	+ if_clk_src = vop2_clk_get(vop2, if_data->clk_src_name);
	7265	+ snprintf(clk_name, sizeof(clk_name), "%s%d", if_data->clk_parent_name, vp->id);
	7266	+ if_clk_parent = vop2_clk_get(vop2, clk_name);
	7267	+ *if_pixclk = vop2_clk_get(vop2, if_data->pixclk_name);
	7268	+ *if_dclk = vop2_clk_get(vop2, if_data->dclk_name);
	7269	+ if (!(*if_pixclk) \|\| !if_clk_parent) {
	7270	+ DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n");
	7271	+ return -ENODEV;
	7272	+ }
	7273	+
	7274	+ ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk);
	7275	+ if (ret < 0) {
	7276	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	7277	+ __clk_get_name(if_clk_parent->hw.clk),
	7278	+ __clk_get_name(if_clk_src->hw.clk), ret);
	7279	+ return ret;
	7280	+ }
	7281	+
	7282	+ /* HDMI and eDP use independent if_pixclk and if_dclk, and others if_pixclk = if_dclk */
	7283	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id))
	7284	+ ret = vop2_calc_if_clk(crtc, if_data, if_pixclk, if_dclk, conn_id);
	7285	+ else
	7286	+ ret = vop2_calc_if_clk(crtc, if_data, *if_pixclk, NULL, conn_id);
	7287	+
	7288	+ return ret;
	7289	+}
	7290	+
	7291	+static void vop2_crtc_load_pps(struct drm_crtc *crtc, u8 dsc_id)
	7292	+{
	7293	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7294	+ struct vop2 *vop2 = vp->vop2;
	7295	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7296	+
	7297	+ struct drm_dsc_picture_parameter_set *pps = &vcstate->pps;
	7298	+ struct drm_dsc_picture_parameter_set config_pps;
	7299	+ int i = 0;
	7300	+ u32 pps_val = (u32 )&config_pps;
	7301	+ u32 offset;
	7302	+ struct vop2_dsc *dsc;
	7303	+
	7304	+ dsc = &vop2->dscs[dsc_id];
	7305	+ offset = dsc->regs->dsc_pps0_3.offset;
	7306	+
	7307	+ memcpy(&config_pps, pps, sizeof(config_pps));
	7308	+
	7309	+ if ((config_pps.pps_3 & 0xf) > dsc->max_linebuf_depth) {
	7310	+ config_pps.pps_3 &= 0xf0;
	7311	+ config_pps.pps_3 \|= dsc->max_linebuf_depth;
	7312	+ DRM_WARN("DSC%d max_linebuf_depth is: %d, current set value is: %d\n",
	7313	+ dsc_id, dsc->max_linebuf_depth, config_pps.pps_3 & 0xf);
	7314	+ }
	7315	+
	7316	+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
	7317	+ config_pps.rc_range_parameters[i] =
	7318	+ (pps->rc_range_parameters[i] >> 3 & 0x1f) \|
	7319	+ ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) \|
	7320	+ ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) \|
	7321	+ ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10);
	7322	+ }
	7323	+
	7324	+ for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++)
	7325	+ vop2_writel(vop2, offset + i * 4, *pps_val++);
	7326	+}
	7327	+
	7328	+static void vop2_crtc_enable_dsc(struct drm_crtc crtc, struct drm_crtc_state old_state, u8 dsc_id)
	7329	+{
	7330	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7331	+ struct vop2 *vop2 = vp->vop2;
	7332	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7333	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7334	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
	7335	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7336	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7337	+ u16 htotal = adjusted_mode->crtc_htotal;
	7338	+ u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
	7339	+ u16 vdisplay = adjusted_mode->crtc_vdisplay;
	7340	+ u16 vtotal = adjusted_mode->crtc_vtotal;
	7341	+ u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
	7342	+ u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
	7343	+ u16 vact_end = vact_st + vdisplay;
	7344	+ u8 dsc_interface_mode = 0;
	7345	+ struct vop2_dsc *dsc;
	7346	+ struct vop2_clk dsc_cds_clk, dsc_pxl_clk, *dsc_txp_clk;
	7347	+ const struct vop2_data *vop2_data = vop2->data;
	7348	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	7349	+ bool mipi_ds_mode = false;
	7350	+ uint32_t *reg_base = vop2->regs;
	7351	+ u32 offset = 0;
	7352	+
	7353	+ if (!vop2->data->nr_dscs) {
	7354	+ DRM_WARN("Unsupported DSC\n");
	7355	+
	7356	+ return;
	7357	+ }
	7358	+
	7359	+ if (vcstate->dsc_slice_num > dsc_data->max_slice_num)
	7360	+ DRM_ERROR("DSC%d supported max slice is: %d, current is: %d\n",
	7361	+ dsc_data->id, dsc_data->max_slice_num, vcstate->dsc_slice_num);
	7362	+
	7363	+ dsc = &vop2->dscs[dsc_id];
	7364	+ if (dsc->pd) {
	7365	+ dsc->pd->vp_mask = BIT(vp->id);
	7366	+ vop2_power_domain_get(dsc->pd);
	7367	+ }
	7368	+
	7369	+ VOP_MODULE_SET(vop2, dsc, scan_timing_para_imd_en, 1);
	7370	+ VOP_MODULE_SET(vop2, dsc, dsc_port_sel, vp->id);
	7371	+ if (vcstate->output_if & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1)) {
	7372	+ dsc_interface_mode = VOP_DSC_IF_HDMI;
	7373	+ } else {
	7374	+ mipi_ds_mode = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE);
	7375	+ if (mipi_ds_mode)
	7376	+ dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE;
	7377	+ else
	7378	+ dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE;
	7379	+ }
	7380	+
	7381	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7382	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 0);
	7383	+ else
	7384	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 1);
	7385	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	7386	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	7387	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_name);
	7388	+
	7389	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, dsc_interface_mode);
	7390	+ VOP_MODULE_SET(vop2, dsc, dsc_pixel_num, vcstate->dsc_pixel_num >> 1);
	7391	+ VOP_MODULE_SET(vop2, dsc, dsc_txp_clk_div, dsc_txp_clk->div_val);
	7392	+ VOP_MODULE_SET(vop2, dsc, dsc_pxl_clk_div, dsc_pxl_clk->div_val);
	7393	+ VOP_MODULE_SET(vop2, dsc, dsc_cds_clk_div, dsc_cds_clk->div_val);
	7394	+ VOP_MODULE_SET(vop2, dsc, dsc_scan_en, !mipi_ds_mode);
	7395	+ VOP_MODULE_SET(vop2, dsc, dsc_halt_en, mipi_ds_mode);
	7396	+
	7397	+ if (!mipi_ds_mode) {
	7398	+ u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end;
	7399	+ u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16;
	7400	+ u64 dsc_cds_rate = vcstate->dsc_cds_clk_rate;
	7401	+ u32 v_pixclk_mhz = adjusted_mode->crtc_clock / 1000; /* video timing pixclk */
	7402	+ u32 dly_num, dsc_cds_rate_mhz, val = 0;
	7403	+ struct vop2_clk *dclk_core;
	7404	+ char clk_name[32];
	7405	+ int k = 1;
	7406	+
	7407	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7408	+ k = 2;
	7409	+
	7410	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7411	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7412	+
	7413	+ if (target_bpp >> 4 < dsc->min_bits_per_pixel)
	7414	+ DRM_ERROR("Unsupported bpp less than: %d\n", dsc->min_bits_per_pixel);
	7415	+
	7416	+ /*
	7417	+ * dly_num = delay_line_num * T(one-line) / T (dsc_cds)
	7418	+ * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
	7419	+ * T (dsc_cds) = 1 / dsc_cds_rate_mhz
	7420	+ *
	7421	+ * HDMI:
	7422	+ * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
	7423	+ * delay_line_num = 4 - BPP / 8
	7424	+ * = (64 - target_bpp / 8) / 16
	7425	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7426	+ *
	7427	+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
	7428	+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
	7429	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7430	+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
	7431	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7432	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
	7433	+ */
	7434	+ do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
	7435	+ dsc_cds_rate_mhz = dsc_cds_rate;
	7436	+ dsc_hsync = hsync_len / 2;
	7437	+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
	7438	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7439	+ } else {
	7440	+ int dsc_buf_size = dsc->id == 0 ? 4320 * 8 : 9216 * 2;
	7441	+ int delay_line_num = dsc_buf_size / vcstate->dsc_slice_num / be16_to_cpu(vcstate->pps.chunk_size);
	7442	+
	7443	+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7444	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
	7445	+
	7446	+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
	7447	+ if (dsc_hsync < 8)
	7448	+ dsc_hsync = 8;
	7449	+ }
	7450	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_mode, 0);
	7451	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_num, dly_num);
	7452	+ /*
	7453	+ * htotal / dclk_core = dsc_htotal /cds_clk
	7454	+ *
	7455	+ * dclk_core = DCLK / (1 << dclk_core->div_val)
	7456	+ * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val)
	7457	+ * txp_clk = DCLK / (1 << dsc_txp_clk->div_val)
	7458	+ *
	7459	+ * dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7460	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val))
	7461	+ */
	7462	+ dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7463	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val));
	7464	+ val = dsc_htotal << 16 \| dsc_hsync;
	7465	+ VOP_MODULE_SET(vop2, dsc, dsc_htotal_pw, val);
	7466	+
	7467	+ dsc_hact_st = hact_st / 2;
	7468	+ dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st;
	7469	+ val = dsc_hact_end << 16 \| dsc_hact_st;
	7470	+ VOP_MODULE_SET(vop2, dsc, dsc_hact_st_end, val);
	7471	+
	7472	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, vtotal);
	7473	+ VOP_MODULE_SET(vop2, dsc, dsc_vs_end, vsync_len);
	7474	+ VOP_MODULE_SET(vop2, dsc, dsc_vact_st_end, vact_end << 16 \| vact_st);
	7475	+ }
	7476	+
	7477	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 1);
	7478	+ udelay(10);
	7479	+ /* read current dsc core register and backup to regsbak */
	7480	+ offset = dsc->regs->dsc_en.offset;
	7481	+ vop2->regsbak[offset >> 2] = reg_base[offset >> 2];
	7482	+
	7483	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 1);
	7484	+ vop2_crtc_load_pps(crtc, dsc_id);
	7485	+
	7486	+ VOP_MODULE_SET(vop2, dsc, dsc_rbit, 1);
	7487	+ VOP_MODULE_SET(vop2, dsc, dsc_rbyt, 0);
	7488	+ VOP_MODULE_SET(vop2, dsc, dsc_flal, 1);
	7489	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	7490	+ VOP_MODULE_SET(vop2, dsc, dsc_epb, 0);
	7491	+ VOP_MODULE_SET(vop2, dsc, dsc_epl, 1);
	7492	+ VOP_MODULE_SET(vop2, dsc, dsc_nslc, ilog2(vcstate->dsc_slice_num));
	7493	+ VOP_MODULE_SET(vop2, dsc, dsc_sbo, 1);
	7494	+ VOP_MODULE_SET(vop2, dsc, dsc_ifep, dsc_sink_cap->version_minor == 2 ? 1 : 0);
	7495	+ VOP_MODULE_SET(vop2, dsc, dsc_pps_upd, 1);
	7496	+
	7497	+ DRM_DEV_INFO(vop2->dev, "DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
	7498	+ dsc->id,
	7499	+ vcstate->dsc_txp_clk_rate, dsc_txp_clk->div_val,
	7500	+ vcstate->dsc_pxl_clk_rate, dsc_pxl_clk->div_val,
	7501	+ vcstate->dsc_cds_clk_rate, dsc_cds_clk->div_val);
	7502	+
	7503	+ dsc->attach_vp_id = vp->id;
	7504	+ dsc->enabled = true;
	7505	+}
	7506	+
	7507	+static inline bool vop2_mark_as_left_panel(struct rockchip_crtc_state *vcstate, u32 output_if)
	7508	+{
	7509	+ return vcstate->output_if_left_panel & output_if;
	7510	+}
	7511	+
	7512	+static void vop2_setup_dual_channel_if(struct drm_crtc *crtc)
	7513	+{
	7514	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7515	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7516	+ struct vop2 *vop2 = vp->vop2;
	7517	+
	7518	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE) {
	7519	+ VOP_CTRL_SET(vop2, lvds_dual_en, 1);
	7520	+ VOP_CTRL_SET(vop2, lvds_dual_mode, 0);
	7521	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
	7522	+ VOP_CTRL_SET(vop2, lvds_dual_channel_swap, 1);
	7523	+ return;
	7524	+ }
	7525	+
	7526	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 1);
	7527	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
	7528	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1);
	7529	+
	7530	+ if (vcstate->output_if & VOP_OUTPUT_IF_DP1 &&
	7531	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_DP1))
	7532	+ VOP_CTRL_SET(vop2, dp_dual_en, 1);
	7533	+ else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1 &&
	7534	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_eDP1))
	7535	+ VOP_CTRL_SET(vop2, edp_dual_en, 1);
	7536	+ else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1 &&
	7537	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_HDMI1))
	7538	+ VOP_CTRL_SET(vop2, hdmi_dual_en, 1);
	7539	+ else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1 &&
	7540	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_MIPI1))
	7541	+ VOP_CTRL_SET(vop2, mipi_dual_en, 1);
	7542	+ else if (vcstate->output_if & VOP_OUTPUT_IF_LVDS1) {
	7543	+ VOP_CTRL_SET(vop2, lvds_dual_en, 1);
	7544	+ VOP_CTRL_SET(vop2, lvds_dual_mode, 1);
	7545	+ }
	7546	+}
	7547	+
	7548	+/*
	7549	+ * MIPI port mux on rk3588:
	7550	+ * 0: Video Port2
	7551	+ * 1: Video Port3
	7552	+ * 3: Video Port 1(MIPI1 only)
	7553	+ */
	7554	+static int vop2_get_mipi_port_mux(struct vop2 *vop2, int vp_id)
	7555	+{
	7556	+ if (vop2->version == VOP_VERSION_RK3588) {
	7557	+ if (vp_id == 1)
	7558	+ return 3;
	7559	+ else if (vp_id == 3)
	7560	+ return 1;
	7561	+ else
	7562	+ return 0;
	7563	+ } else {
	7564	+ return vp_id;
	7565	+ }
	7566	+}
	7567	+
	7568	+static u32 vop2_get_hdmi_pol(struct vop2 *vop2, u32 flags)
	7569	+{
	7570	+ u32 val;
	7571	+
	7572	+ if (vop2->version == VOP_VERSION_RK3588) {
	7573	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0;
	7574	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0;
	7575	+ } else {
	7576	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
	7577	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
	7578	+ }
	7579	+
	7580	+ return val;
	7581	+}
	7582	+
	7583	+static void vop2_post_color_swap(struct drm_crtc *crtc)
	7584	+{
	7585	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7586	+ struct vop2 *vop2 = vp->vop2;
	7587	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7588	+ u32 output_if = vcstate->output_if;
	7589	+ u32 data_swap = 0;
	7590	+
	7591	+ if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode) \|\|
	7592	+ vop3_output_rb_swap(vcstate->bus_format, vcstate->output_mode))
	7593	+ data_swap = DSP_RB_SWAP;
	7594	+
	7595	+ if (vop2->version == VOP_VERSION_RK3588 &&
	7596	+ (output_if_is_hdmi(output_if) \|\| output_if_is_dp(output_if)) &&
	7597	+ (vcstate->bus_format == MEDIA_BUS_FMT_YUV8_1X24 \|\|
	7598	+ vcstate->bus_format == MEDIA_BUS_FMT_YUV10_1X30))
	7599	+ data_swap \|= DSP_RG_SWAP;
	7600	+
	7601	+ VOP_MODULE_SET(vop2, vp, dsp_data_swap, data_swap);
	7602	+}
	7603	+
	7604	+/*
	7605	+ * For vop3 video port0, if hdr_vivid is not enable, the pipe delay time as follow:
	7606	+ * win_dly + config_win_dly + layer_mix_dly + sdr2hdr_dly + * hdr_mix_dly = config_bg_dly
	7607	+ *
	7608	+ * if hdr_vivid is enable, the hdr layer's pipe delay time as follow:
	7609	+ * win_dly + config_win_dly +hdrvivid_dly + hdr_mix_dly = config_bg_dly
	7610	+ *
	7611	+ * If hdrvivid and sdr2hdr bot enable, the time arrivr hdr_mix should be the same:
	7612	+ * win_dly + config_win_dly0 + hdrvivid_dly = win_dly + config_win_dly1 + laer_mix_dly +
	7613	+ * sdr2hdr_dly
	7614	+ *
	7615	+ * For vop3 video port1, the pipe delay time as follow:
	7616	+ * win_dly + config_win_dly + layer_mix_dly = config_bg_dly
	7617	+ *
	7618	+ * Here, win_dly, layer_mix_dly, sdr2hdr_dly, hdr_mix_dly, hdrvivid_dly is the hardware
	7619	+ * delay cycles. Config_win_dly and config_bg_dly is the register value that we can config.
	7620	+ * Different hdr vivid mode have different hdrvivid_dly. For sdr2hdr_dly, only sde2hdr
	7621	+ * enable, it will delay, otherwise, the sdr2hdr_dly is 0.
	7622	+ *
	7623	+ * For default, the config_win_dly will be 0, it just user to make the pipe to arrive
	7624	+ * hdr_mix at the same time.
	7625	+ */
	7626	+static void vop3_setup_pipe_dly(struct vop2_video_port vp, const struct vop2_zpos vop2_zpos)
	7627	+{
	7628	+ struct vop2 *vop2 = vp->vop2;
	7629	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	7630	+ const struct vop2_zpos *zpos;
	7631	+ struct drm_plane *plane;
	7632	+ struct vop2_plane_state *vpstate;
	7633	+ struct vop2_win *win;
	7634	+ const struct vop2_data *vop2_data = vop2->data;
	7635	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	7636	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7637	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7638	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7639	+ int bg_dly = 0x0;
	7640	+ int dly = 0x0;
	7641	+ int hdr_win_dly;
	7642	+ int sdr_win_dly;
	7643	+ int sdr2hdr_dly;
	7644	+ int pre_scan_dly;
	7645	+ int i;
	7646	+
	7647	+ /**
	7648	+ * config bg dly, select the max delay num of hdrvivid and sdr2hdr module
	7649	+ * as the increase value of bg delay num. If hdrvivid and sdr2hdr is not
	7650	+ * work, the default bg_dly is 0x10. and the default win delay num is 0.
	7651	+ */
	7652	+ if ((vp->hdr_en \|\| vp->sdr2hdr_en) &&
	7653	+ (vp->hdrvivid_mode >= 0 && vp->hdrvivid_mode <= SDR2HLG)) {
	7654	+ /* set sdr2hdr_dly to 0 if sdr2hdr is disable */
	7655	+ sdr2hdr_dly = vp->sdr2hdr_en ? vp_data->sdr2hdr_dly : 0;
	7656	+
	7657	+ /* set the max delay pipe's config_win_dly as 0 */
	7658	+ if (vp_data->hdrvivid_dly[vp->hdrvivid_mode] >=
	7659	+ sdr2hdr_dly + vp_data->layer_mix_dly) {
	7660	+ bg_dly = vp_data->win_dly + vp_data->hdrvivid_dly[vp->hdrvivid_mode] +
	7661	+ vp_data->hdr_mix_dly;
	7662	+ hdr_win_dly = 0;
	7663	+ sdr_win_dly = vp_data->hdrvivid_dly[vp->hdrvivid_mode] -
	7664	+ vp_data->layer_mix_dly - sdr2hdr_dly;
	7665	+ } else {
	7666	+ bg_dly = vp_data->win_dly + vp_data->layer_mix_dly + sdr2hdr_dly +
	7667	+ vp_data->hdr_mix_dly;
	7668	+ hdr_win_dly = sdr2hdr_dly + vp_data->layer_mix_dly -
	7669	+ vp_data->hdrvivid_dly[vp->hdrvivid_mode];
	7670	+ sdr_win_dly = 0;
	7671	+ }
	7672	+ } else {
	7673	+ bg_dly = vp_data->win_dly + vp_data->layer_mix_dly + vp_data->hdr_mix_dly;
	7674	+ sdr_win_dly = 0;
	7675	+ }
	7676	+
	7677	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	7678	+ pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	7679	+ VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
	7680	+ VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
	7681	+
	7682	+ /**
	7683	+ * config win dly
	7684	+ */
	7685	+ if (!vop2_zpos)
	7686	+ return;
	7687	+
	7688	+ for (i = 0; i < vp->nr_layers; i++) {
	7689	+ zpos = &vop2_zpos[i];
	7690	+ win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
	7691	+ plane = &win->base;
	7692	+ vpstate = to_vop2_plane_state(plane->state);
	7693	+
	7694	+ if ((vp->hdr_en \|\| vp->sdr2hdr_en) &&
	7695	+ (vp->hdrvivid_mode >= 0 && vp->hdrvivid_mode <= SDR2HLG)) {
	7696	+ dly = vpstate->hdr_in ? hdr_win_dly : sdr_win_dly;
	7697	+ }
	7698	+ if (vop2_cluster_window(win))
	7699	+ dly \|= dly << 8;
	7700	+
	7701	+ VOP_CTRL_SET(vop2, win_dly[win->phys_id], dly);
	7702	+ }
	7703	+}
	7704	+
4883	7705	static void vop2_crtc_atomic_enable(struct drm_crtc crtc, struct drm_crtc_state old_state)
4884	7706	{
4885	7707	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7708	+ struct vop2_video_port *splice_vp;
4886	7709	struct vop2 *vop2 = vp->vop2;
4887	7710	const struct vop2_data *vop2_data = vop2->data;
4888	7711	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4889	7712	const struct vop_intr *intr = vp_data->intr;
4890	7713	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4891	7714	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7715	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
4892	7716	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
4893	7717	u16 hdisplay = adjusted_mode->crtc_hdisplay;
4894	7718	u16 htotal = adjusted_mode->crtc_htotal;
..	..	@@ -4900,18 +7724,61 @@
4900	7724	u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
4901	7725	u16 vact_end = vact_st + vdisplay;
4902	7726	bool interlaced = !!(adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
4903		- uint8_t out_mode;
4904	7727	bool dclk_inv, yc_swap = false;
4905	7728	int act_end;
4906	7729	uint32_t val;
	7730	+ char clk_name[32];
	7731	+ struct vop2_clk *if_pixclk = NULL;
	7732	+ struct vop2_clk *if_dclk = NULL;
	7733	+ struct vop2_clk dclk, dclk_out, *dclk_core;
	7734	+ int splice_en = 0;
	7735	+ int port_mux;
	7736	+ int ret;
	7737	+
	7738	+ if (old_state && old_state->self_refresh_active) {
	7739	+ vop2_crtc_atomic_exit_psr(crtc, old_state);
	7740	+
	7741	+ return;
	7742	+ }
4907	7743
4908	7744	vop2->active_vp_mask \|= BIT(vp->id);
4909	7745	vop2_set_system_status(vop2);
4910	7746
4911	7747	vop2_lock(vop2);
4912		- DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
4913		- hdisplay, vdisplay, interlaced ? "i" : "p",
4914		- adjusted_mode->vrefresh, vcstate->output_type, vp->id);
	7748	+ DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x, flag:0x%x) for vp%d dclk: %d\n",
	7749	+ hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p",
	7750	+ drm_mode_vrefresh(adjusted_mode),
	7751	+ vcstate->output_type, vcstate->output_if, vcstate->output_flags,
	7752	+ vp->id, adjusted_mode->crtc_clock * 1000);
	7753	+
	7754	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	7755	+ vcstate->splice_mode = true;
	7756	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	7757	+ splice_vp->splice_mode_right = true;
	7758	+ splice_vp->left_vp = vp;
	7759	+ splice_en = 1;
	7760	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	7761	+ }
	7762	+
	7763	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE)
	7764	+ vcstate->output_flags \|= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
	7765	+
	7766	+ if (vcstate->dsc_enable) {
	7767	+ int k = 1;
	7768	+
	7769	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7770	+ k = 2;
	7771	+
	7772	+ vcstate->dsc_id = vcstate->output_if & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	7773	+ vcstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k;
	7774	+ vcstate->dsc_pixel_num = vcstate->dsc_slice_num > 4 ? 4 : vcstate->dsc_slice_num;
	7775	+
	7776	+ vop2_calc_dsc_clk(crtc);
	7777	+ DRM_DEV_INFO(vop2->dev, "Enable DSC%d slice:%dx%d, slice num:%d\n",
	7778	+ vcstate->dsc_id, dsc_sink_cap->slice_width,
	7779	+ dsc_sink_cap->slice_height, vcstate->dsc_slice_num);
	7780	+ }
	7781	+
4915	7782	vop2_initial(crtc);
4916	7783	vcstate->vdisplay = vdisplay;
4917	7784	vcstate->mode_update = vop2_crtc_mode_update(crtc);
..	..	@@ -4922,25 +7789,51 @@
4922	7789	val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
4923	7790	val \|= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
4924	7791
	7792	+ vp->output_if = vcstate->output_if;
	7793	+
4925	7794	if (vcstate->output_if & VOP_OUTPUT_IF_RGB) {
	7795	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7796	+ if (ret < 0)
	7797	+ goto out;
	7798	+
4926	7799	VOP_CTRL_SET(vop2, rgb_en, 1);
4927	7800	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4928		- VOP_GRF_SET(vop2, grf_dclk_inv, dclk_inv);
	7801	+ VOP_CTRL_SET(vop2, rgb_pin_pol, val);
	7802	+ VOP_GRF_SET(vop2, sys_grf, grf_dclk_inv, dclk_inv);
4929	7803	}
4930	7804
4931	7805	if (vcstate->output_if & VOP_OUTPUT_IF_BT1120) {
4932		- VOP_CTRL_SET(vop2, rgb_en, 1);
4933		- VOP_CTRL_SET(vop2, bt1120_en, 1);
	7806	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7807	+ if (ret < 0)
	7808	+ goto out;
	7809	+
	7810	+ if (vop2->version == VOP_VERSION_RK3588) {
	7811	+ VOP_CTRL_SET(vop2, bt1120_en, 3);
	7812	+ } else {
	7813	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7814	+ VOP_CTRL_SET(vop2, bt1120_en, 1);
	7815	+ }
4934	7816	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4935		- VOP_GRF_SET(vop2, grf_bt1120_clk_inv, !dclk_inv);
	7817	+ VOP_GRF_SET(vop2, sys_grf, grf_bt1120_clk_inv, !dclk_inv);
	7818	+ VOP_CTRL_SET(vop2, bt1120_dclk_pol, !dclk_inv);
4936	7819	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
4937	7820	VOP_CTRL_SET(vop2, bt1120_yc_swap, yc_swap);
4938	7821	}
4939	7822
4940	7823	if (vcstate->output_if & VOP_OUTPUT_IF_BT656) {
4941		- VOP_CTRL_SET(vop2, bt656_en, 1);
	7824	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7825	+ if (ret < 0)
	7826	+ goto out;
	7827	+
	7828	+ if (vop2->version == VOP_VERSION_RK3588) {
	7829	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7830	+ } else {
	7831	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7832	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7833	+ }
4942	7834	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4943		- VOP_GRF_SET(vop2, grf_bt656_clk_inv, !dclk_inv);
	7835	+ VOP_GRF_SET(vop2, sys_grf, grf_bt656_clk_inv, !dclk_inv);
	7836	+ VOP_CTRL_SET(vop2, bt656_dclk_pol, !dclk_inv);
4944	7837	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
4945	7838	VOP_CTRL_SET(vop2, bt656_yc_swap, yc_swap);
4946	7839	}
..	..	@@ -4959,18 +7852,19 @@
4959	7852	VOP_CTRL_SET(vop2, lvds_dclk_pol, dclk_inv);
4960	7853	}
4961	7854
4962		- if (vcstate->output_flags & (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE \|
4963		- ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) {
4964		- VOP_CTRL_SET(vop2, lvds_dual_en, 1);
4965		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
4966		- VOP_CTRL_SET(vop2, lvds_dual_mode, 1);
4967		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
4968		- VOP_CTRL_SET(vop2, lvds_dual_channel_swap, 1);
4969		- }
4970		-
4971	7855	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI0) {
	7856	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI0, &if_pixclk, &if_dclk);
	7857	+ if (ret < 0)
	7858	+ goto out;
	7859	+ if (if_pixclk)
	7860	+ VOP_CTRL_SET(vop2, mipi0_pixclk_div, if_pixclk->div_val);
	7861	+
	7862	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7863	+ VOP_CTRL_SET(vop2, mipi0_ds_mode, 1);
	7864	+
	7865	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
4972	7866	VOP_CTRL_SET(vop2, mipi0_en, 1);
4973		- VOP_CTRL_SET(vop2, mipi0_mux, vp_data->id);
	7867	+ VOP_CTRL_SET(vop2, mipi0_mux, port_mux);
4974	7868	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
4975	7869	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
4976	7870	if (vcstate->hold_mode) {
..	..	@@ -4980,8 +7874,19 @@
4980	7874	}
4981	7875
4982	7876	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1) {
	7877	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI1, &if_pixclk, &if_dclk);
	7878	+ if (ret < 0)
	7879	+ goto out;
	7880	+ if (if_pixclk)
	7881	+ VOP_CTRL_SET(vop2, mipi1_pixclk_div, if_pixclk->div_val);
	7882	+
	7883	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7884	+ VOP_CTRL_SET(vop2, mipi1_ds_mode, 1);
	7885	+
	7886	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
	7887	+
4983	7888	VOP_CTRL_SET(vop2, mipi1_en, 1);
4984		- VOP_CTRL_SET(vop2, mipi1_mux, vp_data->id);
	7889	+ VOP_CTRL_SET(vop2, mipi1_mux, port_mux);
4985	7890	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
4986	7891	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
4987	7892	if (vcstate->hold_mode) {
..	..	@@ -4990,41 +7895,79 @@
4990	7895	}
4991	7896	}
4992	7897
4993		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
4994		- VOP_MODULE_SET(vop2, vp, mipi_dual_en, 1);
4995		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
4996		- VOP_MODULE_SET(vop2, vp, mipi_dual_channel_swap, 1);
4997		- }
	7898	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE \|\|
	7899	+ vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE)
	7900	+ vop2_setup_dual_channel_if(crtc);
4998	7901
4999	7902	if (vcstate->output_if & VOP_OUTPUT_IF_eDP0) {
	7903	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP0, &if_pixclk, &if_dclk);
	7904	+ if (ret < 0)
	7905	+ goto out;
	7906	+ if (if_pixclk && if_dclk) {
	7907	+ VOP_CTRL_SET(vop2, edp0_pixclk_div, if_pixclk->div_val);
	7908	+ VOP_CTRL_SET(vop2, edp0_dclk_div, if_dclk->div_val);
	7909	+ }
	7910	+
5000	7911	VOP_CTRL_SET(vop2, edp0_en, 1);
5001	7912	VOP_CTRL_SET(vop2, edp0_mux, vp_data->id);
5002	7913	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5003	7914	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7915	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 1);
5004	7916	}
5005	7917
5006	7918	if (vcstate->output_if & VOP_OUTPUT_IF_eDP1) {
	7919	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP1, &if_pixclk, &if_dclk);
	7920	+ if (ret < 0)
	7921	+ goto out;
	7922	+ if (if_pixclk && if_dclk) {
	7923	+ VOP_CTRL_SET(vop2, edp1_pixclk_div, if_pixclk->div_val);
	7924	+ VOP_CTRL_SET(vop2, edp1_dclk_div, if_dclk->div_val);
	7925	+ }
	7926	+
5007	7927	VOP_CTRL_SET(vop2, edp1_en, 1);
5008	7928	VOP_CTRL_SET(vop2, edp1_mux, vp_data->id);
5009	7929	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5010	7930	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7931	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 1);
5011	7932	}
5012	7933
5013	7934	if (vcstate->output_if & VOP_OUTPUT_IF_DP0) {
	7935	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7936	+ if (ret < 0)
	7937	+ goto out;
5014	7938	VOP_CTRL_SET(vop2, dp0_en, 1);
5015	7939	VOP_CTRL_SET(vop2, dp0_mux, vp_data->id);
5016		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5017		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7940	+ VOP_CTRL_SET(vop2, dp0_dclk_pol, 0);
	7941	+ VOP_CTRL_SET(vop2, dp0_pin_pol, val);
5018	7942	}
5019	7943
5020	7944	if (vcstate->output_if & VOP_OUTPUT_IF_DP1) {
	7945	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7946	+ if (ret < 0)
	7947	+ goto out;
	7948	+
5021	7949	VOP_CTRL_SET(vop2, dp1_en, 1);
5022	7950	VOP_CTRL_SET(vop2, dp1_mux, vp_data->id);
5023		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5024		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7951	+ VOP_CTRL_SET(vop2, dp1_dclk_pol, 0);
	7952	+ VOP_CTRL_SET(vop2, dp1_pin_pol, val);
5025	7953	}
5026	7954
5027	7955	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI0) {
	7956	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI0, &if_pixclk, &if_dclk);
	7957	+ if (ret < 0)
	7958	+ goto out;
	7959	+ if (if_pixclk && if_dclk) {
	7960	+ VOP_CTRL_SET(vop2, hdmi0_pixclk_div, if_pixclk->div_val);
	7961	+ VOP_CTRL_SET(vop2, hdmi0_dclk_div, if_dclk->div_val);
	7962	+ }
	7963	+
	7964	+ if (vcstate->dsc_enable)
	7965	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 1);
	7966	+
	7967	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	7968	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 1);
	7969	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi0_pin_pol, val);
	7970	+
5028	7971	VOP_CTRL_SET(vop2, hdmi0_en, 1);
5029	7972	VOP_CTRL_SET(vop2, hdmi0_mux, vp_data->id);
5030	7973	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
..	..	@@ -5032,26 +7975,29 @@
5032	7975	}
5033	7976
5034	7977	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1) {
	7978	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI1, &if_pixclk, &if_dclk);
	7979	+ if (ret < 0)
	7980	+ goto out;
	7981	+
	7982	+ if (if_pixclk && if_dclk) {
	7983	+ VOP_CTRL_SET(vop2, hdmi1_pixclk_div, if_pixclk->div_val);
	7984	+ VOP_CTRL_SET(vop2, hdmi1_dclk_div, if_dclk->div_val);
	7985	+ }
	7986	+
	7987	+ if (vcstate->dsc_enable)
	7988	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 1);
	7989	+
	7990	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	7991	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 1);
	7992	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi1_pin_pol, val);
	7993	+
5035	7994	VOP_CTRL_SET(vop2, hdmi1_en, 1);
5036	7995	VOP_CTRL_SET(vop2, hdmi1_mux, vp_data->id);
5037	7996	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
5038	7997	VOP_CTRL_SET(vop2, hdmi_dclk_pol, 1);
5039	7998	}
5040	7999
5041		- if ((vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
5042		- !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
5043		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
5044		- out_mode = ROCKCHIP_OUT_MODE_P888;
5045		- else
5046		- out_mode = vcstate->output_mode;
5047		- VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
5048		-
5049		- if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
5050		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, DSP_RB_SWAP);
5051		- else
5052		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, 0);
5053		-
5054		- vop2_dither_setup(crtc);
	8000	+ VOP_MODULE_SET(vop2, vp, splice_en, splice_en);
5055	8001
5056	8002	VOP_MODULE_SET(vop2, vp, htotal_pw, (htotal << 16) \| hsync_len);
5057	8003	val = hact_st << 16;
..	..	@@ -5089,7 +8035,13 @@
5089	8035	VOP_INTR_SET(vop2, intr, line_flag_num[0], act_end);
5090	8036	VOP_INTR_SET(vop2, intr, line_flag_num[1], act_end);
5091	8037
5092		- VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 \| vsync_len);
	8038	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, vtotal);
	8039	+ VOP_MODULE_SET(vop2, vp, dsp_vs_end, vsync_len);
	8040	+ /**
	8041	+ * when display interface support vrr, config vtotal valid immediately
	8042	+ */
	8043	+ if (vcstate->max_refresh_rate && vcstate->min_refresh_rate)
	8044	+ VOP_MODULE_SET(vop2, vp, sw_dsp_vtotal_imd, 1);
5093	8045
5094	8046	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
5095	8047	vcstate->output_if & VOP_OUTPUT_IF_BT656)
..	..	@@ -5105,9 +8057,70 @@
5105	8057	VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 0);
5106	8058	}
5107	8059
5108		- clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	8060	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	8061	+ dclk_out = vop2_clk_get(vop2, clk_name);
	8062	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	8063	+ dclk_core = vop2_clk_get(vop2, clk_name);
	8064	+ if (dclk_out && dclk_core) {
	8065	+ DRM_DEV_INFO(vop2->dev, "%s div: %d %s div: %d\n",
	8066	+ __clk_get_name(dclk_out->hw.clk), dclk_out->div_val,
	8067	+ __clk_get_name(dclk_core->hw.clk), dclk_core->div_val);
	8068	+ VOP_MODULE_SET(vop2, vp, dclk_src_sel, 0);
	8069	+ VOP_MODULE_SET(vop2, vp, dclk_out_div, dclk_out->div_val);
	8070	+ VOP_MODULE_SET(vop2, vp, dclk_core_div, dclk_core->div_val);
	8071	+ }
5109	8072
5110		- vop2_post_config(crtc);
	8073	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	8074	+ dclk = vop2_clk_get(vop2, clk_name);
	8075	+ if (dclk) {
	8076	+ /*
	8077	+ * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available,
	8078	+ * otherwise use system cru as dclk source.
	8079	+ */
	8080	+ ret = vop2_clk_set_parent_extend(vp, vcstate, true);
	8081	+ if (ret < 0)
	8082	+ goto out;
	8083	+
	8084	+ clk_set_rate(vp->dclk, dclk->rate);
	8085	+ DRM_DEV_INFO(vop2->dev, "set %s to %ld, get %ld\n",
	8086	+ __clk_get_name(vp->dclk), dclk->rate, clk_get_rate(vp->dclk));
	8087	+ } else {
	8088	+ /*
	8089	+ * For RK3528, the path of CVBS output is like:
	8090	+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
	8091	+ * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
	8092	+ */
	8093	+ if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
	8094	+ clk_set_rate(vp->dclk, 4 * adjusted_mode->crtc_clock * 1000);
	8095	+ else
	8096	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	8097	+ }
	8098	+
	8099	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	8100	+ vop2_post_config(crtc);
	8101	+
	8102	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
	8103	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
	8104	+ if (vcstate->dsc_enable) {
	8105	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	8106	+ vop2_crtc_enable_dsc(crtc, old_state, 0);
	8107	+ vop2_crtc_enable_dsc(crtc, old_state, 1);
	8108	+ } else {
	8109	+ vop2_crtc_enable_dsc(crtc, old_state, vcstate->dsc_id);
	8110	+ }
	8111	+ }
	8112	+ /* For RK3588, the reset value of background is 0xa0080200,
	8113	+ * which will enable background and output a grey image. But
	8114	+ * the reset value is just valid in first frame and disable
	8115	+ * in follow frames. If the panel backlight is valid before
	8116	+ * follow frames. The screen may flick a grey image. To avoid
	8117	+ * this phenomenon appear, setting black background after
	8118	+ * reset vop
	8119	+ */
	8120	+ if (vop2->version == VOP_VERSION_RK3588)
	8121	+ VOP_MODULE_SET(vop2, vp, dsp_background, 0x80000000);
	8122	+ if (is_vop3(vop2))
	8123	+ vop3_setup_pipe_dly(vp, NULL);
5111	8124
5112	8125	vop2_cfg_done(crtc);
5113	8126
..	..	@@ -5128,14 +8141,25 @@
5128	8141	*/
5129	8142	VOP_MODULE_SET(vop2, vp, standby, 0);
5130	8143
5131		- drm_crtc_vblank_on(crtc);
	8144	+ if (vp->mcu_timing.mcu_pix_total) {
	8145	+ vop3_set_out_mode(crtc, vcstate->output_mode);
	8146	+ vop3_mcu_mode_setup(crtc);
	8147	+ }
5132	8148
	8149	+ if (!vp->loader_protect)
	8150	+ vop2_clk_reset(vp->dclk_rst);
	8151	+ if (vcstate->dsc_enable)
	8152	+ rk3588_vop2_dsc_cfg_done(crtc);
	8153	+ drm_crtc_vblank_on(crtc);
5133	8154	/*
5134	8155	* restore the lut table.
5135	8156	*/
5136		- if (vp->gamma_lut_active)
	8157	+ if (vp->gamma_lut_active) {
5137	8158	vop2_crtc_load_lut(crtc);
5138		-
	8159	+ vop2_cfg_done(crtc);
	8160	+ vop2_wait_for_fs_by_done_bit_status(vp);
	8161	+ }
	8162	+out:
5139	8163	vop2_unlock(vop2);
5140	8164	}
5141	8165
..	..	@@ -5153,7 +8177,261 @@
5153	8177	static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
5154	8178	struct drm_crtc_state *crtc_state)
5155	8179	{
	8180	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	8181	+ struct vop2_video_port *splice_vp;
	8182	+ struct vop2 *vop2 = vp->vop2;
	8183	+ const struct vop2_data *vop2_data = vop2->data;
	8184	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	8185	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	8186	+ struct rockchip_crtc_state *new_vcstate = to_rockchip_crtc_state(crtc_state);
	8187	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	8188	+
	8189	+ if (vop2_has_feature(vop2, VOP_FEATURE_SPLICE)) {
	8190	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	8191	+ vcstate->splice_mode = true;
	8192	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	8193	+ splice_vp->splice_mode_right = true;
	8194	+ splice_vp->left_vp = vp;
	8195	+ }
	8196	+ }
	8197	+
	8198	+ if ((vcstate->request_refresh_rate != new_vcstate->request_refresh_rate) \|\|
	8199	+ crtc_state->active_changed \|\| crtc_state->mode_changed)
	8200	+ vp->refresh_rate_change = true;
	8201	+ else
	8202	+ vp->refresh_rate_change = false;
	8203	+
5156	8204	return 0;
	8205	+}
	8206	+
	8207	+static void vop3_disable_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
	8208	+{
	8209	+ struct vop2 *vop2 = vp->vop2;
	8210	+ struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
	8211	+ struct drm_plane *plane = &win->base;
	8212	+ struct drm_plane_state *pstate = plane->state;
	8213	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	8214	+
	8215	+ VOP_MODULE_SET(vop2, vp, hdr10_en, 0);
	8216	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, 0);
	8217	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_bypass_en, 0);
	8218	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
	8219	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_en, 0);
	8220	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, 0);
	8221	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_auto_gating_en, 1);
	8222	+
	8223	+ vp->hdr_en = false;
	8224	+ vp->hdr_in = false;
	8225	+ vp->hdr_out = false;
	8226	+ vp->sdr2hdr_en = false;
	8227	+ vpstate->hdr_in = false;
	8228	+ vpstate->hdr2sdr_en = false;
	8229	+}
	8230	+
	8231	+static void vop3_setup_hdrvivid(struct vop2_video_port *vp, uint8_t win_phys_id)
	8232	+{
	8233	+ struct vop2 *vop2 = vp->vop2;
	8234	+ struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
	8235	+ struct drm_plane *plane = &win->base;
	8236	+ struct drm_plane_state *pstate = plane->state;
	8237	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	8238	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
	8239	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8240	+ unsigned long win_mask = vp->win_mask;
	8241	+ int phys_id;
	8242	+ struct hdrvivid_regs *hdrvivid_data;
	8243	+ struct hdr_extend *hdr_data;
	8244	+ struct rockchip_gem_object *lut_gem_obj;
	8245	+ bool have_sdr_layer = false;
	8246	+ uint32_t hdr_mode;
	8247	+ int i;
	8248	+ u32 *tone_lut_kvaddr;
	8249	+ dma_addr_t tone_lut_mst;
	8250	+
	8251	+ vp->hdr_en = false;
	8252	+ vp->hdr_in = false;
	8253	+ vp->hdr_out = false;
	8254	+ vp->sdr2hdr_en = false;
	8255	+ vpstate->hdr_in = false;
	8256	+ vpstate->hdr2sdr_en = false;
	8257	+
	8258	+ hdr_data = (struct hdr_extend *)vcstate->hdr_ext_data->data;
	8259	+ hdrvivid_data = &hdr_data->hdrvivid_data;
	8260	+
	8261	+ hdr_mode = hdrvivid_data->hdr_mode;
	8262	+
	8263	+ if (hdr_mode > SDR2HLG && hdr_mode != SDR2HDR10_USERSPACE &&
	8264	+ hdr_mode != SDR2HLG_USERSPACE) {
	8265	+ DRM_ERROR("Invalid HDR mode:%d, beyond the mode range\n", hdr_mode);
	8266	+ return;
	8267	+ }
	8268	+
	8269	+ /* adjust userspace hdr mode value to kernel value */
	8270	+ if (hdr_mode == SDR2HDR10_USERSPACE)
	8271	+ hdr_mode = SDR2HDR10;
	8272	+ if (hdr_mode == SDR2HLG_USERSPACE)
	8273	+ hdr_mode = SDR2HLG;
	8274	+
	8275	+ if (hdr_mode <= HDR102SDR && vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 && vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
	8276	+ DRM_ERROR("Invalid HDR mode:%d, mismatch plane eotf:%d\n", hdr_mode,
	8277	+ vpstate->eotf);
	8278	+ return;
	8279	+ }
	8280	+
	8281	+ vp->hdrvivid_mode = hdr_mode;
	8282	+ vcstate->yuv_overlay = false;
	8283	+
	8284	+ if (hdr_mode <= HDR102SDR) {
	8285	+ vp->hdr_en = true;
	8286	+ vp->hdr_in = true;
	8287	+ vpstate->hdr_in = true;
	8288	+ } else {
	8289	+ vp->sdr2hdr_en = true;
	8290	+ }
	8291	+
	8292	+ /*
	8293	+ * To confirm whether need to enable sdr2hdr.
	8294	+ */
	8295	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8296	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8297	+ plane = &win->base;
	8298	+ pstate = plane->state;
	8299	+ vpstate = to_vop2_plane_state(pstate);
	8300	+
	8301	+ /* skip inactive plane */
	8302	+ if (!vop2_plane_active(pstate))
	8303	+ continue;
	8304	+
	8305	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 &&
	8306	+ vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
	8307	+ have_sdr_layer = true;
	8308	+ break;
	8309	+ }
	8310	+ }
	8311	+
	8312	+ if (hdr_mode == PQHDR2SDR_WITH_DYNAMIC \|\| hdr_mode == HLG2SDR_WITH_DYNAMIC \|\|
	8313	+ hdr_mode == HLG2SDR_WITHOUT_DYNAMIC \|\| hdr_mode == HDR102SDR) {
	8314	+ vpstate->hdr2sdr_en = true;
	8315	+ } else {
	8316	+ vp->hdr_out = true;
	8317	+ if (have_sdr_layer)
	8318	+ vp->sdr2hdr_en = true;
	8319	+ }
	8320	+
	8321	+ /**
	8322	+ * Config hdr ctrl registers
	8323	+ */
	8324	+ vop2_writel(vop2, RK3528_SDR2HDR_CTRL, hdrvivid_data->sdr2hdr_ctrl);
	8325	+ vop2_writel(vop2, RK3528_HDRVIVID_CTRL, hdrvivid_data->hdrvivid_ctrl);
	8326	+
	8327	+ VOP_MODULE_SET(vop2, vp, hdr10_en, vp->hdr_en);
	8328	+ if (vp->hdr_en) {
	8329	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, (hdr_mode == HDR_BYPASS) ? 0 : 1);
	8330	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_path_mode,
	8331	+ (hdr_mode == HDR102SDR) ? PQHDR2SDR_WITH_DYNAMIC : hdr_mode);
	8332	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_bypass_en, (hdr_mode == HDR_BYPASS) ? 1 : 0);
	8333	+ } else {
	8334	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, 0);
	8335	+ }
	8336	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_en, vp->sdr2hdr_en);
	8337	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, vp->sdr2hdr_en);
	8338	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_auto_gating_en, vp->sdr2hdr_en ? 0 : 1);
	8339	+
	8340	+ vop2_writel(vop2, RK3528_SDR_CFG_COE0, hdrvivid_data->sdr2hdr_coe0);
	8341	+ vop2_writel(vop2, RK3528_SDR_CFG_COE1, hdrvivid_data->sdr2hdr_coe1);
	8342	+ vop2_writel(vop2, RK3528_SDR_CSC_COE00_01, hdrvivid_data->sdr2hdr_csc_coe00_01);
	8343	+ vop2_writel(vop2, RK3528_SDR_CSC_COE02_10, hdrvivid_data->sdr2hdr_csc_coe02_10);
	8344	+ vop2_writel(vop2, RK3528_SDR_CSC_COE11_12, hdrvivid_data->sdr2hdr_csc_coe11_12);
	8345	+ vop2_writel(vop2, RK3528_SDR_CSC_COE20_21, hdrvivid_data->sdr2hdr_csc_coe20_21);
	8346	+ vop2_writel(vop2, RK3528_SDR_CSC_COE22, hdrvivid_data->sdr2hdr_csc_coe22);
	8347	+
	8348	+ vop2_writel(vop2, RK3528_HDR_PQ_GAMMA, hdrvivid_data->hdr_pq_gamma);
	8349	+ vop2_writel(vop2, RK3528_HLG_RFIX_SCALEFAC, hdrvivid_data->hlg_rfix_scalefac);
	8350	+ vop2_writel(vop2, RK3528_HLG_MAXLUMA, hdrvivid_data->hlg_maxluma);
	8351	+ vop2_writel(vop2, RK3528_HLG_R_TM_LIN2NON, hdrvivid_data->hlg_r_tm_lin2non);
	8352	+
	8353	+ vop2_writel(vop2, RK3528_HDR_CSC_COE00_01, hdrvivid_data->hdr_csc_coe00_01);
	8354	+ vop2_writel(vop2, RK3528_HDR_CSC_COE02_10, hdrvivid_data->hdr_csc_coe02_10);
	8355	+ vop2_writel(vop2, RK3528_HDR_CSC_COE11_12, hdrvivid_data->hdr_csc_coe11_12);
	8356	+ vop2_writel(vop2, RK3528_HDR_CSC_COE20_21, hdrvivid_data->hdr_csc_coe20_21);
	8357	+ vop2_writel(vop2, RK3528_HDR_CSC_COE22, hdrvivid_data->hdr_csc_coe22);
	8358	+
	8359	+ if (!vp->hdr_lut_gem_obj) {
	8360	+ lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev,
	8361	+ RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0);
	8362	+ if (IS_ERR(lut_gem_obj)) {
	8363	+ DRM_ERROR("create hdr lut obj failed\n");
	8364	+ return;
	8365	+ }
	8366	+ vp->hdr_lut_gem_obj = lut_gem_obj;
	8367	+ }
	8368	+
	8369	+ tone_lut_kvaddr = (u32 *)vp->hdr_lut_gem_obj->kvaddr;
	8370	+ tone_lut_mst = vp->hdr_lut_gem_obj->dma_addr;
	8371	+
	8372	+ for (i = 0; i < RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH; i++)
	8373	+ *tone_lut_kvaddr++ = hdrvivid_data->tone_sca_axi_tab[i];
	8374	+
	8375	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid - vp->id);
	8376	+ VOP_MODULE_SET(vop2, vp, hdr_lut_mode, 1);
	8377	+ VOP_MODULE_SET(vop2, vp, hdr_lut_mst, tone_lut_mst);
	8378	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 1);
	8379	+ VOP_CTRL_SET(vop2, lut_dma_en, 1);
	8380	+
	8381	+ for (i = 0; i < RK_HDRVIVID_GAMMA_CURVE_LENGTH; i++)
	8382	+ vop2_writel(vop2, RK3528_HDRGAMMA_CURVE + i * 4, hdrvivid_data->hdrgamma_curve[i]);
	8383	+
	8384	+ for (i = 0; i < RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH; i++)
	8385	+ vop2_writel(vop2, RK3528_HDRGAMMA_MDFVALUE + i * 4,
	8386	+ hdrvivid_data->hdrgamma_mdfvalue[i]);
	8387	+
	8388	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_CURVE_LENGTH; i++)
	8389	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_CURVE + i * 4,
	8390	+ hdrvivid_data->sdrinvgamma_curve[i]);
	8391	+
	8392	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH; i++)
	8393	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_STARTIDX + i * 4,
	8394	+ hdrvivid_data->sdrinvgamma_startidx[i]);
	8395	+
	8396	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH; i++)
	8397	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_CHANGEIDX + i * 4,
	8398	+ hdrvivid_data->sdrinvgamma_changeidx[i]);
	8399	+
	8400	+ for (i = 0; i < RK_SDR2HDR_SMGAIN_LENGTH; i++)
	8401	+ vop2_writel(vop2, RK3528_SDR_SMGAIN + i * 4, hdrvivid_data->sdr_smgain[i]);
	8402	+}
	8403	+
	8404	+static void vop3_setup_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
	8405	+{
	8406	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
	8407	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8408	+ struct hdr_extend *hdr_data;
	8409	+ uint32_t hdr_format;
	8410	+
	8411	+ /* If hdr extend data is null, exit hdr mode */
	8412	+ if (!vcstate->hdr_ext_data) {
	8413	+ vop3_disable_dynamic_hdr(vp, win_phys_id);
	8414	+ return;
	8415	+ }
	8416	+
	8417	+ hdr_data = (struct hdr_extend *)vcstate->hdr_ext_data->data;
	8418	+ hdr_format = hdr_data->hdr_type;
	8419	+
	8420	+ switch (hdr_format) {
	8421	+ case HDR_NONE:
	8422	+ case HDR_HDR10:
	8423	+ case HDR_HLGSTATIC:
	8424	+ case HDR_HDRVIVID:
	8425	+ /*
	8426	+ * hdr module support hdr10, hlg, vividhdr
	8427	+ * sdr2hdr module support hdrnone for sdr2hdr
	8428	+ */
	8429	+ vop3_setup_hdrvivid(vp, win_phys_id);
	8430	+ break;
	8431	+ default:
	8432	+ DRM_DEBUG("unsupprot hdr format:%u\n", hdr_format);
	8433	+ break;
	8434	+ }
5157	8435	}
5158	8436
5159	8437	static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id)
..	..	@@ -5161,13 +8439,13 @@
5161	8439	struct vop2 *vop2 = vp->vop2;
5162	8440	struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5163	8441	struct drm_plane *plane = &win->base;
5164		- struct drm_plane_state *pstate = plane->state;
5165		- struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
5166		- struct drm_crtc_state *cstate = vp->crtc.state;
5167		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8442	+ struct drm_plane_state *pstate;
	8443	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
5168	8444	const struct vop2_data *vop2_data = vop2->data;
5169	8445	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5170	8446	const struct vop_hdr_table *hdr_table = vp_data->hdr_table;
	8447	+ struct rockchip_crtc_state *vcstate;
	8448	+ struct vop2_plane_state *vpstate;
5171	8449	uint32_t lut_mode = VOP2_HDR_LUT_MODE_AHB;
5172	8450	uint32_t sdr2hdr_r2r_mode = 0;
5173	8451	bool hdr_en = 0;
..	..	@@ -5187,14 +8465,27 @@
5187	8465	return;
5188	8466
5189	8467	/*
	8468	+ * right vp share the same crtc/plane state in splice mode
	8469	+ */
	8470	+ if (vp->splice_mode_right) {
	8471	+ vcstate = to_rockchip_crtc_state(vp->left_vp->rockchip_crtc.crtc.state);
	8472	+ pstate = win->left_win->base.state;
	8473	+ } else {
	8474	+ vcstate = to_rockchip_crtc_state(cstate);
	8475	+ pstate = plane->state;
	8476	+ }
	8477	+
	8478	+ vpstate = to_vop2_plane_state(pstate);
	8479	+
	8480	+ /*
5190	8481	* HDR video plane input
5191	8482	*/
5192		- if (vpstate->eotf == SMPTE_ST2084)
	8483	+ if (vpstate->eotf == HDMI_EOTF_SMPTE_ST2084)
5193	8484	hdr_en = 1;
5194	8485
5195	8486	vp->hdr_en = hdr_en;
5196	8487	vp->hdr_in = hdr_en;
5197		- vp->hdr_out = (vcstate->eotf == SMPTE_ST2084) ? true : false;
	8488	+ vp->hdr_out = (vcstate->eotf == HDMI_EOTF_SMPTE_ST2084) ? true : false;
5198	8489
5199	8490	/*
5200	8491	* only laryer0 support hdr2sdr
..	..	@@ -5212,15 +8503,21 @@
5212	8503	*/
5213	8504	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
5214	8505	win = vop2_find_win_by_phys_id(vop2, phys_id);
5215		- plane = &win->base;
5216		- pstate = plane->state;
5217		- vpstate = to_vop2_plane_state(pstate);
	8506	+ if (vp->splice_mode_right) {
	8507	+ if (win->left_win)
	8508	+ pstate = win->left_win->base.state;
	8509	+ else
	8510	+ pstate = NULL; /* this win is not activated */
	8511	+ } else {
	8512	+ pstate = win->base.state;
	8513	+ }
5218	8514
5219		- /* skip inactive plane */
	8515	+ vpstate = pstate ? to_vop2_plane_state(pstate) : NULL;
	8516	+
5220	8517	if (!vop2_plane_active(pstate))
5221	8518	continue;
5222	8519
5223		- if (vpstate->eotf != SMPTE_ST2084) {
	8520	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084) {
5224	8521	have_sdr_layer = true;
5225	8522	break;
5226	8523	}
..	..	@@ -5367,7 +8664,15 @@
5367	8664
5368	8665	if (!sub_win) {
5369	8666	/* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
5370		- plane = &main_win->base;
	8667	+
	8668	+ /*
	8669	+ * right cluster share the same plane state in splice mode
	8670	+ */
	8671	+ if (cluster->splice_mode)
	8672	+ plane = &main_win->left_win->base;
	8673	+ else
	8674	+ plane = &main_win->base;
	8675	+
5371	8676	top_win_vpstate = NULL;
5372	8677	bottom_win_vpstate = to_vop2_plane_state(plane->state);
5373	8678	src_glb_alpha_val = 0;
..	..	@@ -5426,25 +8731,35 @@
5426	8731	uint32_t dst_color_ctrl_offset = vop2->data->ctrl->dst_color_ctrl.offset;
5427	8732	uint32_t src_alpha_ctrl_offset = vop2->data->ctrl->src_alpha_ctrl.offset;
5428	8733	uint32_t dst_alpha_ctrl_offset = vop2->data->ctrl->dst_alpha_ctrl.offset;
	8734	+ unsigned long win_mask = vp->win_mask;
5429	8735	const struct vop2_zpos *zpos;
5430		- struct drm_framebuffer *fb;
	8736	+ struct vop2_plane_state *vpstate;
5431	8737	struct vop2_alpha_config alpha_config;
5432	8738	struct vop2_alpha alpha;
5433	8739	struct vop2_win *win;
5434		- struct drm_plane *plane;
5435		- struct vop2_plane_state *vpstate;
	8740	+ struct drm_plane_state *pstate;
	8741	+ struct drm_framebuffer *fb;
5436	8742	int pixel_alpha_en;
5437		- int premulti_en;
	8743	+ int premulti_en = 1;
5438	8744	int mixer_id;
	8745	+ int phys_id;
5439	8746	uint32_t offset;
5440	8747	int i;
5441	8748	bool bottom_layer_alpha_en = false;
5442	8749	u32 dst_global_alpha = 0xff;
5443	8750
5444		- drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
5445		- struct vop2_win *win = to_vop2_win(plane);
	8751	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8752	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8753	+ if (win->splice_mode_right)
	8754	+ pstate = win->left_win->base.state;
	8755	+ else
	8756	+ pstate = win->base.state;
5446	8757
5447		- vpstate = to_vop2_plane_state(plane->state);
	8758	+ vpstate = to_vop2_plane_state(pstate);
	8759	+
	8760	+ if (!vop2_plane_active(pstate))
	8761	+ continue;
	8762	+
5448	8763	if (vpstate->zpos == 0 && vpstate->global_alpha != 0xff &&
5449	8764	!vop2_cluster_window(win)) {
5450	8765	/*
..	..	@@ -5454,19 +8769,33 @@
5454	8769	*/
5455	8770	bottom_layer_alpha_en = true;
5456	8771	dst_global_alpha = vpstate->global_alpha;
	8772	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8773	+ premulti_en = 1;
	8774	+ else
	8775	+ premulti_en = 0;
	8776	+
5457	8777	break;
5458	8778	}
5459	8779	}
5460	8780
5461	8781	mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
	8782	+
	8783	+ if (vop2->version == VOP_VERSION_RK3588 &&
	8784	+ vp->hdr10_at_splice_mode && vp->id == 0)
	8785	+ mixer_id++;/* fixed path for rk3588: layer1 -> hdr10_1 */
	8786	+
5462	8787	alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
5463	8788	for (i = 1; i < vp->nr_layers; i++) {
5464	8789	zpos = &vop2_zpos[i];
5465	8790	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5466		- plane = &win->base;
5467		- vpstate = to_vop2_plane_state(plane->state);
5468		- fb = plane->state->fb;
5469		- if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8791	+ if (win->splice_mode_right)
	8792	+ pstate = win->left_win->base.state;
	8793	+ else
	8794	+ pstate = win->base.state;
	8795	+
	8796	+ vpstate = to_vop2_plane_state(pstate);
	8797	+ fb = pstate->fb;
	8798	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
5470	8799	premulti_en = 1;
5471	8800	else
5472	8801	premulti_en = 0;
..	..	@@ -5496,29 +8825,27 @@
5496	8825	vop2_writel(vop2, dst_color_ctrl_offset + offset, alpha.dst_color_ctrl.val);
5497	8826	vop2_writel(vop2, src_alpha_ctrl_offset + offset, alpha.src_alpha_ctrl.val);
5498	8827	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
	8828	+ }
5499	8829
5500		- if (i == 1) {
5501		- if (bottom_layer_alpha_en \|\| vp->hdr_en) {
5502		- /* Transfer pixel alpha to hdr mix */
5503		- alpha_config.src_premulti_en = premulti_en;
5504		- alpha_config.dst_premulti_en = true;
5505		- alpha_config.src_pixel_alpha_en = true;
5506		- alpha_config.src_glb_alpha_value = 0xff;
5507		- alpha_config.dst_glb_alpha_value = 0xff;
5508		- vop2_parse_alpha(&alpha_config, &alpha);
	8830	+ if (bottom_layer_alpha_en \|\| vp->hdr_en) {
	8831	+ /* Transfer pixel alpha to hdr mix */
	8832	+ alpha_config.src_premulti_en = premulti_en;
	8833	+ alpha_config.dst_premulti_en = true;
	8834	+ alpha_config.src_pixel_alpha_en = true;
	8835	+ alpha_config.src_glb_alpha_value = 0xff;
	8836	+ alpha_config.dst_glb_alpha_value = 0xff;
	8837	+ vop2_parse_alpha(&alpha_config, &alpha);
5509	8838
5510		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
5511		- alpha.src_color_ctrl.val);
5512		- VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
5513		- alpha.dst_color_ctrl.val);
5514		- VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
5515		- alpha.src_alpha_ctrl.val);
5516		- VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
5517		- alpha.dst_alpha_ctrl.val);
5518		- } else {
5519		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5520		- }
5521		- }
	8839	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
	8840	+ alpha.src_color_ctrl.val);
	8841	+ VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
	8842	+ alpha.dst_color_ctrl.val);
	8843	+ VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
	8844	+ alpha.src_alpha_ctrl.val);
	8845	+ VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
	8846	+ alpha.dst_alpha_ctrl.val);
	8847	+ } else {
	8848	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5522	8849	}
5523	8850
5524	8851	/* Transfer pixel alpha value to next mix */
..	..	@@ -5648,7 +8975,7 @@
5648	8975	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
5649	8976	}
5650	8977
5651		- if (vp_data->feature & VOP_FEATURE_HDR10) {
	8978	+ if (vp_data->feature & (VOP_FEATURE_HDR10 \| VOP_FEATURE_VIVID_HDR)) {
5652	8979	src_color_ctrl_offset = ovl_regs->hdr_mix_regs->src_color_ctrl.offset;
5653	8980	dst_color_ctrl_offset = ovl_regs->hdr_mix_regs->dst_color_ctrl.offset;
5654	8981	src_alpha_ctrl_offset = ovl_regs->hdr_mix_regs->src_alpha_ctrl.offset;
..	..	@@ -5679,21 +9006,6 @@
5679	9006	VOP_MODULE_SET(vop2, vp, bg_mix_ctrl, bg_alpha_ctrl.val);
5680	9007	}
5681	9008
5682		-static void vop2_setup_port_mux(struct vop2_video_port *vp, uint16_t port_mux_cfg)
5683		-{
5684		- struct vop2 *vop2 = vp->vop2;
5685		-
5686		- spin_lock(&vop2->reg_lock);
5687		- if (vop2->port_mux_cfg != port_mux_cfg) {
5688		- VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
5689		- vp->skip_vsync = true;
5690		- vop2_cfg_done(&vp->crtc);
5691		- vop2->port_mux_cfg = port_mux_cfg;
5692		- vop2_wait_for_port_mux_done(vop2);
5693		- }
5694		- spin_unlock(&vop2->reg_lock);
5695		-}
5696		-
5697	9009	static u32 vop2_layer_cfg_update(struct vop2_layer *layer, u32 old_layer_cfg, u8 win_layer_id)
5698	9010	{
5699	9011	const struct vop_reg *reg = &layer->regs->layer_sel;
..	..	@@ -5716,6 +9028,12 @@
5716	9028	for (i = 0; i < vop2_data->nr_vps - 1; i++) {
5717	9029	prev_vp = &vop2->vps[i];
5718	9030	used_layers += hweight32(prev_vp->win_mask);
	9031	+ if (vop2->version == VOP_VERSION_RK3588) {
	9032	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 0)
	9033	+ used_layers += 1;
	9034	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 1)
	9035	+ used_layers -= 1;
	9036	+ }
5719	9037	/*
5720	9038	* when a window move from vp0 to vp1, or vp0 to vp2,
5721	9039	* it should flow these steps:
..	..	@@ -5741,10 +9059,26 @@
5741	9059	prev_vp->bg_ovl_dly = (vop2_data->nr_mixers - port_mux) << 1;
5742	9060	}
5743	9061
5744		- if (vop2->data->nr_vps >= 1)
5745		- port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
	9062	+ port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
5746	9063
5747	9064	return port_mux_cfg;
	9065	+}
	9066	+
	9067	+static void vop2_setup_port_mux(struct vop2_video_port *vp)
	9068	+{
	9069	+ struct vop2 *vop2 = vp->vop2;
	9070	+ u16 port_mux_cfg;
	9071	+
	9072	+ port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
	9073	+ spin_lock(&vop2->reg_lock);
	9074	+ if (vop2->port_mux_cfg != port_mux_cfg) {
	9075	+ VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
	9076	+ vp->skip_vsync = true;
	9077	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	9078	+ vop2->port_mux_cfg = port_mux_cfg;
	9079	+ vop2_wait_for_port_mux_done(vop2);
	9080	+ }
	9081	+ spin_unlock(&vop2->reg_lock);
5748	9082	}
5749	9083
5750	9084	static void vop2_setup_layer_mixer_for_vp(struct vop2_video_port *vp,
..	..	@@ -5758,15 +9092,12 @@
5758	9092	struct vop2_win *win;
5759	9093	u8 used_layers = 0;
5760	9094	u8 layer_id, win_phys_id;
5761		- u16 port_mux_cfg;
5762	9095	u32 layer_cfg_reg_offset = layer->regs->layer_sel.offset;
5763	9096	u8 nr_layers = vp->nr_layers;
5764	9097	u32 old_layer_cfg = 0;
5765	9098	u32 new_layer_cfg = 0;
5766	9099	u32 atv_layer_cfg;
5767	9100	int i;
5768		-
5769		- port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
5770	9101
5771	9102	/*
5772	9103	* Win and layer must map one by one, if a win is selected
..	..	@@ -5782,6 +9113,10 @@
5782	9113
5783	9114	old_layer_cfg = vop2->regsbak[layer_cfg_reg_offset >> 2];
5784	9115	new_layer_cfg = old_layer_cfg;
	9116	+
	9117	+ if (vp->hdr10_at_splice_mode)
	9118	+ nr_layers *= 2;
	9119	+
5785	9120	for (i = 0; i < nr_layers; i++) {
5786	9121	layer = &vop2->layers[used_layers + i];
5787	9122	zpos = &vop2_zpos[i];
..	..	@@ -5795,21 +9130,21 @@
5795	9130	layer = &vop2->layers[layer_id];
5796	9131	win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5797	9132	new_layer_cfg = vop2_layer_cfg_update(layer, new_layer_cfg, win->layer_sel_id[vp->id]);
5798		- win->layer_id = layer->id;
5799	9133	win->layer_id = layer_id;
5800	9134	layer->win_phys_id = win_phys_id;
5801	9135	}
5802	9136
5803	9137	atv_layer_cfg = vop2_read_layer_cfg(vop2);
5804		- if ((new_layer_cfg != old_layer_cfg) &&
5805		- (atv_layer_cfg != old_layer_cfg)) {
	9138	+ if (new_layer_cfg != old_layer_cfg &&
	9139	+ atv_layer_cfg != old_layer_cfg &&
	9140	+ !vp->splice_mode_right) {
5806	9141	dev_dbg(vop2->dev, "wait old_layer_sel: 0x%x\n", old_layer_cfg);
5807	9142	vop2_wait_for_layer_cfg_done(vop2, old_layer_cfg);
5808	9143	}
5809	9144	vop2_writel(vop2, RK3568_OVL_LAYER_SEL, new_layer_cfg);
5810		- VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
	9145	+ if (new_layer_cfg != old_layer_cfg)
	9146	+ VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
5811	9147	VOP_CTRL_SET(vop2, ovl_port_mux_cfg_done_imd, 0);
5812		- vop2_setup_port_mux(vp, port_mux_cfg);
5813	9148	}
5814	9149
5815	9150	static void vop3_setup_layer_sel_for_vp(struct vop2_video_port *vp,
..	..	@@ -5852,7 +9187,9 @@
5852	9187	struct vop2 *vop2 = vp->vop2;
5853	9188	const struct vop2_data *vop2_data = vop2->data;
5854	9189	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5855		- struct drm_crtc *crtc = &vp->crtc;
	9190	+ struct vop2_video_port *left_vp = vp->left_vp;
	9191	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	9192	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5856	9193	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
5857	9194	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
5858	9195	u16 hdisplay = adjusted_mode->crtc_hdisplay;
..	..	@@ -5871,13 +9208,30 @@
5871	9208	}
5872	9209	}
5873	9210
5874		- if (!vp->hdr_in)
	9211	+ if (!vp->hdr_in \|\|
	9212	+ (vop2->version == VOP_VERSION_RK3588 && vp->hdr_out))
5875	9213	bg_dly -= vp->bg_ovl_dly;
5876	9214
5877		- pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
5878		- if (vop2->version >= VOP_VERSION_RK3588 && hsync_len < 8)
	9215	+ /*
	9216	+ * right vp share the same crtc state in splice mode
	9217	+ */
	9218	+ if (vp->splice_mode_right) {
	9219	+ vcstate = to_rockchip_crtc_state(left_vp->rockchip_crtc.crtc.state);
	9220	+ adjusted_mode = &left_vp->rockchip_crtc.crtc.state->adjusted_mode;
	9221	+ hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	9222	+ hdisplay = adjusted_mode->crtc_hdisplay;
	9223	+ }
	9224	+
	9225	+ if (vcstate->splice_mode)
	9226	+ pre_scan_dly = bg_dly + (hdisplay >> 2) - 1;
	9227	+ else
	9228	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	9229	+
	9230	+ if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8)
5879	9231	hsync_len = 8;
	9232	+
5880	9233	pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	9234	+
5881	9235	VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
5882	9236	VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
5883	9237	}
..	..	@@ -5895,8 +9249,17 @@
5895	9249	for (i = 0; i < vp->nr_layers; i++) {
5896	9250	zpos = &vop2_zpos[i];
5897	9251	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5898		- plane = &win->base;
5899		- vpstate = to_vop2_plane_state(plane->state);
	9252	+ /*
	9253	+ * right vp share the same plane state in splice mode
	9254	+ */
	9255	+ if (vp->splice_mode_right) {
	9256	+ plane = &win->left_win->base;
	9257	+ vpstate = to_vop2_plane_state(plane->state);
	9258	+ } else {
	9259	+ plane = &win->base;
	9260	+ vpstate = to_vop2_plane_state(plane->state);
	9261	+ }
	9262	+
5900	9263	if (vp->hdr_in && !vp->hdr_out && !vpstate->hdr_in) {
5901	9264	dly = win->dly[VOP2_DLY_MODE_HISO_S];
5902	9265	dly += vp->bg_ovl_dly;
..	..	@@ -5913,21 +9276,128 @@
5913	9276	}
5914	9277	}
5915	9278
	9279	+static void rk3588_vop2_setup_hdr10_splice_layer_mixer(struct drm_crtc *crtc,
	9280	+ struct vop2_zpos *vop2_zpos,
	9281	+ struct vop2_zpos *vop2_zpos_splice)
	9282	+{
	9283	+ int zpos_id, i;
	9284	+ struct vop2_zpos *vop2_zpos_splice_hdr;
	9285	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9286	+ struct vop2 *vop2 = vp->vop2;
	9287	+
	9288	+ vop2_zpos_splice_hdr = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9289	+ GFP_KERNEL);
	9290	+ if (!vop2_zpos_splice_hdr)
	9291	+ goto out;
	9292	+
	9293	+ zpos_id = 0;
	9294	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9295	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[0].win_phys_id;
	9296	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[0].plane;
	9297	+
	9298	+ zpos_id++;
	9299	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9300	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[0].win_phys_id;
	9301	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[0].plane;
	9302	+
	9303	+ for (i = 1; i < vp->nr_layers; i++) {
	9304	+ zpos_id++;
	9305	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9306	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[i].win_phys_id;
	9307	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[i].plane;
	9308	+ }
	9309	+
	9310	+ for (i = 1; i < vp->nr_layers; i++) {
	9311	+ zpos_id++;
	9312	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9313	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[i].win_phys_id;
	9314	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[i].plane;
	9315	+ }
	9316	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos_splice_hdr);
	9317	+
	9318	+out:
	9319	+ kfree(vop2_zpos_splice_hdr);
	9320	+}
	9321	+
	9322	+static void vop2_crtc_update_vrr(struct drm_crtc *crtc)
	9323	+{
	9324	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9325	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9326	+ struct vop2 *vop2 = vp->vop2;
	9327	+ struct drm_display_mode *adjust_mode = &crtc->state->adjusted_mode;
	9328	+
	9329	+ unsigned int vrefresh;
	9330	+ unsigned int new_vtotal, vfp, new_vfp;
	9331	+
	9332	+ if (!vp->refresh_rate_change)
	9333	+ return;
	9334	+
	9335	+ if (!vcstate->min_refresh_rate \|\| !vcstate->max_refresh_rate)
	9336	+ return;
	9337	+
	9338	+ if (vcstate->request_refresh_rate < vcstate->min_refresh_rate \|\|
	9339	+ vcstate->request_refresh_rate > vcstate->max_refresh_rate) {
	9340	+ DRM_ERROR("invalid rate:%d\n", vcstate->request_refresh_rate);
	9341	+ return;
	9342	+ }
	9343	+
	9344	+ vrefresh = drm_mode_vrefresh(adjust_mode);
	9345	+
	9346	+ /* calculate new vfp for new refresh rate */
	9347	+ new_vtotal = adjust_mode->vtotal * vrefresh / vcstate->request_refresh_rate;
	9348	+ vfp = adjust_mode->vsync_start - adjust_mode->vdisplay;
	9349	+ new_vfp = vfp + new_vtotal - adjust_mode->vtotal;
	9350	+
	9351	+ /* config vop2 vtotal register */
	9352	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, new_vtotal);
	9353	+
	9354	+ /* config dsc vtotal register */
	9355	+ if (vcstate->dsc_enable) {
	9356	+ struct vop2_dsc *dsc;
	9357	+
	9358	+ dsc = &vop2->dscs[vcstate->dsc_id];
	9359	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9360	+
	9361	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	9362	+ dsc = &vop2->dscs[vcstate->dsc_id ? 0 : 1];
	9363	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9364	+ }
	9365	+ }
	9366	+
	9367	+ /* config all connectors attach to this crtc */
	9368	+ rockchip_connector_update_vfp_for_vrr(crtc, adjust_mode, new_vfp);
	9369	+}
	9370	+
5916	9371	static void vop2_crtc_atomic_begin(struct drm_crtc crtc, struct drm_crtc_state old_crtc_state)
5917	9372	{
5918	9373	struct vop2_video_port *vp = to_vop2_video_port(crtc);
5919	9374	struct vop2 *vop2 = vp->vop2;
	9375	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9376	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
5920	9377	struct drm_plane *plane;
5921	9378	struct vop2_plane_state *vpstate;
5922	9379	struct vop2_zpos *vop2_zpos;
	9380	+ struct vop2_zpos *vop2_zpos_splice;
5923	9381	struct vop2_cluster cluster;
5924	9382	uint8_t nr_layers = 0;
	9383	+ uint8_t splice_nr_layers = 0;
	9384	+ bool hdr10_in = false;
	9385	+ bool hdr10_at_splice_mode = false;
5925	9386	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5926	9387
5927	9388	vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
5928	9389	vop2_zpos = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos), GFP_KERNEL);
5929	9390	if (!vop2_zpos)
5930	9391	return;
	9392	+ if (vcstate->splice_mode) {
	9393	+ vop2_zpos_splice = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9394	+ GFP_KERNEL);
	9395	+ if (!vop2_zpos_splice)
	9396	+ goto out;
	9397	+ }
	9398	+
	9399	+ if (vop2->version == VOP_VERSION_RK3588)
	9400	+ vop2_crtc_update_vrr(crtc);
5931	9401
5932	9402	/* Process cluster sub windows overlay. */
5933	9403	drm_atomic_crtc_for_each_plane(plane, crtc) {
..	..	@@ -5937,9 +9407,13 @@
5937	9407	win->two_win_mode = false;
5938	9408	if (!(win->feature & WIN_FEATURE_CLUSTER_SUB))
5939	9409	continue;
	9410	+ if (vcstate->splice_mode)
	9411	+ DRM_ERROR("vp%d %s not supported two win mode at splice mode\n",
	9412	+ vp->id, win->name);
5940	9413	main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
5941	9414	cluster.main = main_win;
5942	9415	cluster.sub = win;
	9416	+ cluster.splice_mode = false;
5943	9417	win->two_win_mode = true;
5944	9418	main_win->two_win_mode = true;
5945	9419	vop2_setup_cluster_alpha(vop2, &cluster);
..	..	@@ -5951,6 +9425,7 @@
5951	9425
5952	9426	drm_atomic_crtc_for_each_plane(plane, crtc) {
5953	9427	struct vop2_win *win = to_vop2_win(plane);
	9428	+ struct vop2_win *splice_win;
5954	9429	struct vop2_video_port *old_vp;
5955	9430	uint8_t old_vp_id;
5956	9431
..	..	@@ -5970,38 +9445,102 @@
5970	9445	vop2_zpos[nr_layers].win_phys_id = win->phys_id;
5971	9446	vop2_zpos[nr_layers].zpos = vpstate->zpos;
5972	9447	vop2_zpos[nr_layers].plane = plane;
	9448	+
	9449	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "%s active zpos:%d for vp%d from vp%d\n",
	9450	+ win->name, vpstate->zpos, vp->id, old_vp->id);
	9451	+ /* left and right win may have different number */
	9452	+ if (vcstate->splice_mode) {
	9453	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	9454	+ splice_win->splice_mode_right = true;
	9455	+ splice_win->left_win = win;
	9456	+ win->splice_win = splice_win;
	9457	+
	9458	+ old_vp_id = ffs(splice_win->vp_mask);
	9459	+ old_vp_id = (old_vp_id == 0) ? 0 : old_vp_id - 1;
	9460	+ old_vp = &vop2->vps[old_vp_id];
	9461	+ old_vp->win_mask &= ~BIT(splice_win->phys_id);
	9462	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	9463	+ splice_win->vp_mask = BIT(splice_vp->id);
	9464	+ hdr10_in \|= vpstate->eotf == HDMI_EOTF_SMPTE_ST2084 ? true : false;
	9465	+ vop2_zpos_splice[splice_nr_layers].win_phys_id = splice_win->phys_id;
	9466	+ vop2_zpos_splice[splice_nr_layers].zpos = vpstate->zpos;
	9467	+ vop2_zpos_splice[splice_nr_layers].plane = &splice_win->base;
	9468	+ splice_nr_layers++;
	9469	+ DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
	9470	+ splice_win->name, vpstate->zpos, splice_vp->id, old_vp->id);
	9471	+ }
5973	9472	nr_layers++;
5974		- DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
5975		- win->name, vpstate->zpos, vp->id, old_vp->id);
5976	9473	}
5977	9474
5978		- DRM_DEV_DEBUG(vop2->dev, "vp%d: %d windows, active layers %d\n",
5979		- vp->id, hweight32(vp->win_mask), nr_layers);
	9475	+ if (vcstate->splice_mode) {
	9476	+ if (hdr10_in)
	9477	+ hdr10_at_splice_mode = true;
	9478	+
	9479	+ splice_vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9480	+ }
	9481	+ vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9482	+
	9483	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "vp%d: %d windows, active layers %d\n",
	9484	+ vp->id, hweight32(vp->win_mask), nr_layers);
5980	9485	if (nr_layers) {
5981	9486	vp->nr_layers = nr_layers;
5982	9487
5983	9488	sort(vop2_zpos, nr_layers, sizeof(vop2_zpos[0]), vop2_zpos_cmp, NULL);
5984	9489
5985		- if (is_vop3(vop2))
5986		- vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
5987		- else
5988		- vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
5989		- vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
5990		- if (is_vop3(vop2))
	9490	+ if (!vp->hdr10_at_splice_mode) {
	9491	+ if (is_vop3(vop2)) {
	9492	+ vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
	9493	+ } else {
	9494	+ vop2_setup_port_mux(vp);
	9495	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
	9496	+ }
	9497	+ }
	9498	+
	9499	+ if (is_vop3(vop2)) {
	9500	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	9501	+ vop3_setup_dynamic_hdr(vp, vop2_zpos[0].win_phys_id);
5991	9502	vop3_setup_alpha(vp, vop2_zpos);
5992		- else
	9503	+ vop3_setup_pipe_dly(vp, vop2_zpos);
	9504	+ } else {
	9505	+ vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
5993	9506	vop2_setup_alpha(vp, vop2_zpos);
5994		- vop2_setup_dly_for_vp(vp);
5995		- vop2_setup_dly_for_window(vp, vop2_zpos);
	9507	+ vop2_setup_dly_for_vp(vp);
	9508	+ vop2_setup_dly_for_window(vp, vop2_zpos);
	9509	+ }
	9510	+
	9511	+ if (vcstate->splice_mode) {/* Fixme for VOP3 8K */
	9512	+ splice_vp->nr_layers = splice_nr_layers;
	9513	+
	9514	+ sort(vop2_zpos_splice, splice_nr_layers, sizeof(vop2_zpos_splice[0]),
	9515	+ vop2_zpos_cmp, NULL);
	9516	+
	9517	+ vop2_setup_port_mux(splice_vp);
	9518	+ if (!vp->hdr10_at_splice_mode)
	9519	+ vop2_setup_layer_mixer_for_vp(splice_vp, vop2_zpos_splice);
	9520	+ vop2_setup_hdr10(splice_vp, vop2_zpos_splice[0].win_phys_id);
	9521	+ vop2_setup_alpha(splice_vp, vop2_zpos_splice);
	9522	+ vop2_setup_dly_for_vp(splice_vp);
	9523	+ vop2_setup_dly_for_window(splice_vp, vop2_zpos_splice);
	9524	+
	9525	+ if (vop2->version == VOP_VERSION_RK3588 &&
	9526	+ vp->hdr10_at_splice_mode)
	9527	+ rk3588_vop2_setup_hdr10_splice_layer_mixer(crtc, vop2_zpos, vop2_zpos_splice);
	9528	+ }
5996	9529	} else {
5997		- if (!is_vop3(vop2))
	9530	+ if (!is_vop3(vop2)) {
5998	9531	vop2_calc_bg_ovl_and_port_mux(vp);
5999		- vop2_setup_dly_for_vp(vp);
	9532	+ vop2_setup_dly_for_vp(vp);
	9533	+ if (vcstate->splice_mode)
	9534	+ vop2_setup_dly_for_vp(splice_vp);
	9535	+ } else {
	9536	+ vop3_setup_pipe_dly(vp, NULL);
	9537	+ }
6000	9538	}
6001	9539
6002	9540	/* The pre alpha overlay of Cluster still need process in one win mode. */
6003	9541	drm_atomic_crtc_for_each_plane(plane, crtc) {
6004	9542	struct vop2_win *win = to_vop2_win(plane);
	9543	+ struct vop2_win *splice_win;
6005	9544
6006	9545	if (!(win->feature & WIN_FEATURE_CLUSTER_MAIN))
6007	9546	continue;
..	..	@@ -6009,9 +9548,19 @@
6009	9548	continue;
6010	9549	cluster.main = win;
6011	9550	cluster.sub = NULL;
	9551	+ cluster.splice_mode = false;
6012	9552	vop2_setup_cluster_alpha(vop2, &cluster);
	9553	+ if (vcstate->splice_mode) {
	9554	+ splice_win = win->splice_win;
	9555	+ cluster.main = splice_win;
	9556	+ cluster.splice_mode = true;
	9557	+ vop2_setup_cluster_alpha(vop2, &cluster);
	9558	+ }
6013	9559	}
6014	9560
	9561	+ if (vcstate->splice_mode)
	9562	+ kfree(vop2_zpos_splice);
	9563	+out:
6015	9564	kfree(vop2_zpos);
6016	9565	}
6017	9566
..	..	@@ -6122,6 +9671,171 @@
6122	9671	bcsh_state.cos_hue = cos_hue;
6123	9672
6124	9673	vop2_bcsh_reg_update(vcstate, vp, &bcsh_state);
	9674	+ if (vcstate->splice_mode) {
	9675	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9676	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	9677	+
	9678	+ vop2_bcsh_reg_update(vcstate, splice_vp, &bcsh_state);
	9679	+ }
	9680	+}
	9681	+
	9682	+static void vop3_post_csc_config(struct drm_crtc crtc, struct post_acm acm, struct post_csc *csc)
	9683	+{
	9684	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9685	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9686	+ struct vop2 *vop2 = vp->vop2;
	9687	+ struct post_csc_coef csc_coef;
	9688	+ bool acm_enable;
	9689	+ bool is_input_yuv = false;
	9690	+ bool is_output_yuv = false;
	9691	+ bool post_r2y_en = false;
	9692	+ bool post_csc_en = false;
	9693	+ int range_type;
	9694	+
	9695	+ if (!acm)
	9696	+ acm_enable = false;
	9697	+ else
	9698	+ acm_enable = acm->acm_enable;
	9699	+
	9700	+ if (acm_enable) {
	9701	+ if (!vcstate->yuv_overlay)
	9702	+ post_r2y_en = true;
	9703	+
	9704	+ /* do y2r in csc module */
	9705	+ if (!is_yuv_output(vcstate->bus_format))
	9706	+ post_csc_en = true;
	9707	+ } else {
	9708	+ if (!vcstate->yuv_overlay && is_yuv_output(vcstate->bus_format))
	9709	+ post_r2y_en = true;
	9710	+
	9711	+ /* do y2r in csc module */
	9712	+ if (vcstate->yuv_overlay && !is_yuv_output(vcstate->bus_format))
	9713	+ post_csc_en = true;
	9714	+ }
	9715	+
	9716	+ if (csc && csc->csc_enable)
	9717	+ post_csc_en = true;
	9718	+
	9719	+ if (vcstate->yuv_overlay \|\| post_r2y_en)
	9720	+ is_input_yuv = true;
	9721	+
	9722	+ if (is_yuv_output(vcstate->bus_format))
	9723	+ is_output_yuv = true;
	9724	+
	9725	+ vcstate->post_csc_mode = vop2_convert_csc_mode(vcstate->color_space, CSC_13BIT_DEPTH);
	9726	+
	9727	+ if (post_csc_en) {
	9728	+ rockchip_calc_post_csc(csc, &csc_coef, vcstate->post_csc_mode, is_input_yuv,
	9729	+ is_output_yuv);
	9730	+
	9731	+ VOP_MODULE_SET(vop2, vp, csc_coe00, csc_coef.csc_coef00);
	9732	+ VOP_MODULE_SET(vop2, vp, csc_coe01, csc_coef.csc_coef01);
	9733	+ VOP_MODULE_SET(vop2, vp, csc_coe02, csc_coef.csc_coef02);
	9734	+ VOP_MODULE_SET(vop2, vp, csc_coe10, csc_coef.csc_coef10);
	9735	+ VOP_MODULE_SET(vop2, vp, csc_coe11, csc_coef.csc_coef11);
	9736	+ VOP_MODULE_SET(vop2, vp, csc_coe12, csc_coef.csc_coef12);
	9737	+ VOP_MODULE_SET(vop2, vp, csc_coe20, csc_coef.csc_coef20);
	9738	+ VOP_MODULE_SET(vop2, vp, csc_coe21, csc_coef.csc_coef21);
	9739	+ VOP_MODULE_SET(vop2, vp, csc_coe22, csc_coef.csc_coef22);
	9740	+ VOP_MODULE_SET(vop2, vp, csc_offset0, csc_coef.csc_dc0);
	9741	+ VOP_MODULE_SET(vop2, vp, csc_offset1, csc_coef.csc_dc1);
	9742	+ VOP_MODULE_SET(vop2, vp, csc_offset2, csc_coef.csc_dc2);
	9743	+
	9744	+ range_type = csc_coef.range_type ? 0 : 1;
	9745	+ range_type <<= is_input_yuv ? 0 : 1;
	9746	+ VOP_MODULE_SET(vop2, vp, csc_mode, range_type);
	9747	+ }
	9748	+
	9749	+ VOP_MODULE_SET(vop2, vp, acm_r2y_en, post_r2y_en ? 1 : 0);
	9750	+ VOP_MODULE_SET(vop2, vp, csc_en, post_csc_en ? 1 : 0);
	9751	+ VOP_MODULE_SET(vop2, vp, acm_r2y_mode, vcstate->post_csc_mode);
	9752	+}
	9753	+
	9754	+static void vop3_post_acm_config(struct drm_crtc crtc, struct post_acm acm)
	9755	+{
	9756	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9757	+ struct vop2 *vop2 = vp->vop2;
	9758	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	9759	+ s16 *lut_y;
	9760	+ s16 *lut_h;
	9761	+ s16 *lut_s;
	9762	+ u32 value;
	9763	+ int i;
	9764	+
	9765	+ writel(0, vop2->acm_regs + RK3528_ACM_CTRL);
	9766	+ VOP_MODULE_SET(vop2, vp, acm_bypass_en, 0);
	9767	+
	9768	+ if (!acm \|\| !acm->acm_enable)
	9769	+ return;
	9770	+
	9771	+ /*
	9772	+ * If acm update parameters, it need disable acm in the first frame,
	9773	+ * then update parameters and enable acm in second frame.
	9774	+ */
	9775	+ vop2_cfg_done(crtc);
	9776	+ readx_poll_timeout(readl, vop2->acm_regs + RK3528_ACM_CTRL, value, !value, 200, 50000);
	9777	+
	9778	+ value = RK3528_ACM_ENABLE + ((adjusted_mode->hdisplay & 0xfff) << 8) +
	9779	+ ((adjusted_mode->vdisplay & 0xfff) << 20);
	9780	+ writel(value, vop2->acm_regs + RK3528_ACM_CTRL);
	9781	+
	9782	+
	9783	+ writel(1, vop2->acm_regs + RK3528_ACM_FETCH_START);
	9784	+
	9785	+ value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
	9786	+ ((acm->s_gain << 20) & 0x3ff00000);
	9787	+ writel(value, vop2->acm_regs + RK3528_ACM_DELTA_RANGE);
	9788	+
	9789	+ lut_y = &acm->gain_lut_hy[0];
	9790	+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
	9791	+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
	9792	+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
	9793	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	9794	+ ((lut_s[i] << 16) & 0xff0000);
	9795	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
	9796	+ }
	9797	+
	9798	+ lut_y = &acm->gain_lut_hs[0];
	9799	+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
	9800	+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
	9801	+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
	9802	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	9803	+ ((lut_s[i] << 16) & 0xff0000);
	9804	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
	9805	+ }
	9806	+
	9807	+ lut_y = &acm->delta_lut_h[0];
	9808	+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
	9809	+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
	9810	+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
	9811	+ value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) +
	9812	+ ((lut_s[i] << 20) & 0x3ff00000);
	9813	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
	9814	+ }
	9815	+
	9816	+ writel(1, vop2->acm_regs + RK3528_ACM_FETCH_DONE);
	9817	+}
	9818	+
	9819	+static void vop3_post_config(struct drm_crtc *crtc)
	9820	+{
	9821	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9822	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9823	+ struct post_acm *acm;
	9824	+ struct post_csc *csc;
	9825	+
	9826	+ csc = vcstate->post_csc_data ? (struct post_csc *)vcstate->post_csc_data->data : NULL;
	9827	+ if (csc && memcmp(&vp->csc_info, csc, sizeof(struct post_csc)))
	9828	+ memcpy(&vp->csc_info, csc, sizeof(struct post_csc));
	9829	+ vop3_post_csc_config(crtc, &vp->acm_info, &vp->csc_info);
	9830	+
	9831	+ acm = vcstate->acm_lut_data ? (struct post_acm *)vcstate->acm_lut_data->data : NULL;
	9832	+
	9833	+ if (acm && memcmp(&vp->acm_info, acm, sizeof(struct post_acm))) {
	9834	+ memcpy(&vp->acm_info, acm, sizeof(struct post_acm));
	9835	+ vop3_post_acm_config(crtc, &vp->acm_info);
	9836	+ } else if (crtc->state->active_changed) {
	9837	+ vop3_post_acm_config(crtc, &vp->acm_info);
	9838	+ }
6125	9839	}
6126	9840
6127	9841	static void vop2_cfg_update(struct drm_crtc *crtc,
..	..	@@ -6130,10 +9844,28 @@
6130	9844	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6131	9845	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6132	9846	struct vop2 *vop2 = vp->vop2;
	9847	+ const struct vop2_data *vop2_data = vop2->data;
	9848	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	9849	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
6133	9850	uint32_t val;
6134	9851	uint32_t r, g, b;
	9852	+ uint8_t out_mode;
6135	9853
6136	9854	spin_lock(&vop2->reg_lock);
	9855	+
	9856	+ if ((vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
	9857	+ !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
	9858	+ vcstate->output_if & VOP_OUTPUT_IF_BT656)
	9859	+ out_mode = ROCKCHIP_OUT_MODE_P888;
	9860	+ else
	9861	+ out_mode = vcstate->output_mode;
	9862	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	9863	+
	9864	+ vop2_post_color_swap(crtc);
	9865	+
	9866	+ vop2_dither_setup(vcstate, crtc);
	9867	+ if (vcstate->splice_mode)
	9868	+ vop2_dither_setup(vcstate, &splice_vp->rockchip_crtc.crtc);
6137	9869
6138	9870	VOP_MODULE_SET(vop2, vp, overlay_mode, vcstate->yuv_overlay);
6139	9871
..	..	@@ -6156,12 +9888,86 @@
6156	9888	}
6157	9889
6158	9890	VOP_MODULE_SET(vop2, vp, dsp_background, val);
	9891	+ if (vcstate->splice_mode) {
	9892	+ VOP_MODULE_SET(vop2, splice_vp, overlay_mode, vcstate->yuv_overlay);
	9893	+ VOP_MODULE_SET(vop2, splice_vp, dsp_background, val);
	9894	+ }
6159	9895
6160	9896	vop2_tv_config_update(crtc, old_crtc_state);
6161	9897
6162		- vop2_post_config(crtc);
	9898	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	9899	+ vop2_post_config(crtc);
6163	9900
6164	9901	spin_unlock(&vop2->reg_lock);
	9902	+
	9903	+ if (vp_data->feature & (VOP_FEATURE_POST_ACM \| VOP_FEATURE_POST_CSC))
	9904	+ vop3_post_config(crtc);
	9905	+}
	9906	+
	9907	+static void vop2_sleep_scan_line_time(struct vop2_video_port *vp, int scan_line)
	9908	+{
	9909	+ struct vop2 *vop2 = vp->vop2;
	9910	+ struct drm_display_mode *mode = &vp->rockchip_crtc.crtc.state->adjusted_mode;
	9911	+
	9912	+ if (scan_line <= 0)
	9913	+ return;
	9914	+
	9915	+ if (IS_ENABLED(CONFIG_HIGH_RES_TIMERS) &&
	9916	+ (!IS_ENABLED(CONFIG_NO_GKI) \|\| (hrtimer_resolution != LOW_RES_NSEC))) {
	9917	+ u16 htotal = VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16;
	9918	+ u32 linedur_ns = div_u64((u64) htotal * 1000000, mode->crtc_clock);
	9919	+ u64 sleep_time = linedur_ns * scan_line;
	9920	+
	9921	+ sleep_time = div_u64((sleep_time + 1000), 1000);
	9922	+ if (sleep_time > 200)
	9923	+ usleep_range(sleep_time, sleep_time);
	9924	+ }
	9925	+}
	9926	+
	9927	+/*
	9928	+ * return scan timing from FS to the assigned wait line
	9929	+ */
	9930	+static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp,
	9931	+ u32 current_line,
	9932	+ u32 wait_line)
	9933	+
	9934	+{
	9935	+ struct vop2 *vop2 = vp->vop2;
	9936	+ u32 vcnt;
	9937	+ int ret;
	9938	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	9939	+ int delta_line = vtotal - current_line;
	9940	+
	9941	+ vop2_sleep_scan_line_time(vp, delta_line);
	9942	+ if (vop2_read_vcnt(vp) < wait_line)
	9943	+ return;
	9944	+
	9945	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt < wait_line, 0, 50 * 1000);
	9946	+ if (ret)
	9947	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from FS to the assigned wait line: %d, vcnt:%d, ret:%d\n",
	9948	+ wait_line, vcnt, ret);
	9949	+}
	9950	+
	9951	+/*
	9952	+ * return scan timing from the assigned wait line
	9953	+ */
	9954	+static void vop2_wait_for_scan_timing_from_the_assigned_line(struct vop2_video_port *vp,
	9955	+ u32 current_line,
	9956	+ u32 wait_line)
	9957	+{
	9958	+ struct vop2 *vop2 = vp->vop2;
	9959	+ u32 vcnt;
	9960	+ int ret;
	9961	+ int delta_line = wait_line - current_line;
	9962	+
	9963	+ vop2_sleep_scan_line_time(vp, delta_line);
	9964	+ if (vop2_read_vcnt(vp) > wait_line)
	9965	+ return;
	9966	+
	9967	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt > wait_line, 0, 50 * 1000);
	9968	+ if (ret)
	9969	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from the assigned wait line: %d, vcnt:%d, ret:%d\n",
	9970	+ wait_line, vcnt, ret);
6165	9971	}
6166	9972
6167	9973	static void vop2_crtc_atomic_flush(struct drm_crtc crtc, struct drm_crtc_state old_cstate)
..	..	@@ -6169,11 +9975,26 @@
6169	9975	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6170	9976	struct drm_atomic_state *old_state = old_cstate->state;
6171	9977	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6172		- struct drm_plane_state *old_pstate;
6173	9978	struct vop2 *vop2 = vp->vop2;
	9979	+ struct drm_plane_state *old_pstate;
6174	9980	struct drm_plane *plane;
6175	9981	unsigned long flags;
6176	9982	int i, ret;
	9983	+ struct vop2_wb *wb = &vop2->wb;
	9984	+ struct drm_writeback_connector *wb_conn = &wb->conn;
	9985	+ struct drm_connector_state *conn_state = wb_conn->base.state;
	9986	+
	9987	+ if (conn_state && conn_state->writeback_job && conn_state->writeback_job->fb) {
	9988	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	9989	+ u32 current_line = vop2_read_vcnt(vp);
	9990	+
	9991	+ if (current_line > vtotal * 7 >> 3)
	9992	+ vop2_wait_for_scan_timing_max_to_assigned_line(vp, current_line, vtotal * 7 >> 3);
	9993	+
	9994	+ current_line = vop2_read_vcnt(vp);
	9995	+ if (current_line < vtotal >> 3)
	9996	+ vop2_wait_for_scan_timing_from_the_assigned_line(vp, current_line, vtotal >> 3);
	9997	+ }
6177	9998
6178	9999	vop2_cfg_update(crtc, old_cstate);
6179	10000
..	..	@@ -6199,10 +10020,9 @@
6199	10020	vp->gamma_lut = crtc->state->gamma_lut->data;
6200	10021	vop2_crtc_atomic_gamma_set(crtc, crtc->state);
6201	10022	}
6202		-
6203		- if (crtc->state->cubic_lut \|\| vp->cubic_lut) {
6204		- if (crtc->state->cubic_lut)
6205		- vp->cubic_lut = crtc->state->cubic_lut->data;
	10023	+ if (vcstate->cubic_lut_data \|\| vp->cubic_lut) {
	10024	+ if (vcstate->cubic_lut_data)
	10025	+ vp->cubic_lut = vcstate->cubic_lut_data->data;
6206	10026	vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state);
6207	10027	}
6208	10028	} else {
..	..	@@ -6217,6 +10037,9 @@
6217	10037	spin_lock_irqsave(&vop2->irq_lock, flags);
6218	10038	vop2_wb_commit(crtc);
6219	10039	vop2_cfg_done(crtc);
	10040	+
	10041	+ if (vp->mcu_timing.mcu_pix_total)
	10042	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0);
6220	10043
6221	10044	spin_unlock_irqrestore(&vop2->irq_lock, flags);
6222	10045
..	..	@@ -6258,6 +10081,7 @@
6258	10081	}
6259	10082
6260	10083	static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
	10084	+ .mode_valid = vop2_crtc_mode_valid,
6261	10085	.mode_fixup = vop2_crtc_mode_fixup,
6262	10086	.atomic_check = vop2_crtc_atomic_check,
6263	10087	.atomic_begin = vop2_crtc_atomic_begin,
..	..	@@ -6298,12 +10122,24 @@
6298	10122	struct rockchip_crtc_state vcstate, old_vcstate;
6299	10123	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6300	10124
	10125	+ if (WARN_ON(!crtc->state))
	10126	+ return NULL;
	10127	+
6301	10128	old_vcstate = to_rockchip_crtc_state(crtc->state);
6302	10129	vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
6303	10130	if (!vcstate)
6304	10131	return NULL;
6305	10132
6306	10133	vcstate->vp_id = vp->id;
	10134	+ if (vcstate->hdr_ext_data)
	10135	+ drm_property_blob_get(vcstate->hdr_ext_data);
	10136	+ if (vcstate->acm_lut_data)
	10137	+ drm_property_blob_get(vcstate->acm_lut_data);
	10138	+ if (vcstate->post_csc_data)
	10139	+ drm_property_blob_get(vcstate->post_csc_data);
	10140	+ if (vcstate->cubic_lut_data)
	10141	+ drm_property_blob_get(vcstate->cubic_lut_data);
	10142	+
6307	10143	__drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
6308	10144	return &vcstate->base;
6309	10145	}
..	..	@@ -6314,6 +10150,10 @@
6314	10150	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
6315	10151
6316	10152	__drm_atomic_helper_crtc_destroy_state(&vcstate->base);
	10153	+ drm_property_blob_put(vcstate->hdr_ext_data);
	10154	+ drm_property_blob_put(vcstate->acm_lut_data);
	10155	+ drm_property_blob_put(vcstate->post_csc_data);
	10156	+ drm_property_blob_put(vcstate->cubic_lut_data);
6317	10157	kfree(vcstate);
6318	10158	}
6319	10159
..	..	@@ -6414,25 +10254,54 @@
6414	10254	return 0;
6415	10255	}
6416	10256
6417		- if (property == private->alpha_scale_prop) {
6418		- *val = (vop2->data->feature & VOP_FEATURE_ALPHA_SCALE) ? 1 : 0;
6419		- return 0;
6420		- }
6421		-
6422		- if (property == vop2->aclk_prop) {
	10257	+ if (property == private->aclk_prop) {
6423	10258	/* KHZ, keep align with mode->clock */
6424	10259	*val = clk_get_rate(vop2->aclk) / 1000;
6425	10260	return 0;
6426	10261	}
6427	10262
6428		-
6429		- if (property == vop2->bg_prop) {
	10263	+ if (property == private->bg_prop) {
6430	10264	*val = vcstate->background;
6431	10265	return 0;
6432	10266	}
6433	10267
6434		- if (property == vop2->line_flag_prop) {
	10268	+ if (property == private->line_flag_prop) {
6435	10269	*val = vcstate->line_flag;
	10270	+ return 0;
	10271	+ }
	10272	+
	10273	+ if (property == vp->variable_refresh_rate_prop) {
	10274	+ *val = vcstate->request_refresh_rate;
	10275	+ return 0;
	10276	+ }
	10277	+
	10278	+ if (property == vp->max_refresh_rate_prop) {
	10279	+ *val = vcstate->max_refresh_rate;
	10280	+ return 0;
	10281	+ }
	10282	+
	10283	+ if (property == vp->min_refresh_rate_prop) {
	10284	+ *val = vcstate->min_refresh_rate;
	10285	+ return 0;
	10286	+ }
	10287	+
	10288	+ if (property == vp->hdr_ext_data_prop) {
	10289	+ *val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0;
	10290	+ return 0;
	10291	+ }
	10292	+
	10293	+ if (property == vp->acm_lut_data_prop) {
	10294	+ *val = vcstate->acm_lut_data ? vcstate->acm_lut_data->base.id : 0;
	10295	+ return 0;
	10296	+ }
	10297	+
	10298	+ if (property == vp->post_csc_data_prop) {
	10299	+ *val = vcstate->post_csc_data ? vcstate->post_csc_data->base.id : 0;
	10300	+ return 0;
	10301	+ }
	10302	+
	10303	+ if (property == private->cubic_lut_prop) {
	10304	+ *val = (vcstate->cubic_lut_data) ? vcstate->cubic_lut_data->base.id : 0;
6436	10305	return 0;
6437	10306	}
6438	10307
..	..	@@ -6441,16 +10310,52 @@
6441	10310	return -EINVAL;
6442	10311	}
6443	10312
	10313	+/* copied from drm_atomic.c */
	10314	+static int
	10315	+vop2_atomic_replace_property_blob_from_id(struct drm_device *dev,
	10316	+ struct drm_property_blob **blob,
	10317	+ uint64_t blob_id,
	10318	+ ssize_t expected_size,
	10319	+ ssize_t expected_elem_size,
	10320	+ bool *replaced)
	10321	+{
	10322	+ struct drm_property_blob *new_blob = NULL;
	10323	+
	10324	+ if (blob_id != 0) {
	10325	+ new_blob = drm_property_lookup_blob(dev, blob_id);
	10326	+ if (new_blob == NULL)
	10327	+ return -EINVAL;
	10328	+
	10329	+ if (expected_size > 0 &&
	10330	+ new_blob->length != expected_size) {
	10331	+ drm_property_blob_put(new_blob);
	10332	+ return -EINVAL;
	10333	+ }
	10334	+ if (expected_elem_size > 0 &&
	10335	+ new_blob->length % expected_elem_size != 0) {
	10336	+ drm_property_blob_put(new_blob);
	10337	+ return -EINVAL;
	10338	+ }
	10339	+ }
	10340	+
	10341	+ *replaced \|= drm_property_replace_blob(blob, new_blob);
	10342	+ drm_property_blob_put(new_blob);
	10343	+
	10344	+ return 0;
	10345	+}
	10346	+
6444	10347	static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
6445	10348	struct drm_crtc_state *state,
6446	10349	struct drm_property *property,
6447	10350	uint64_t val)
6448	10351	{
6449	10352	struct drm_device *drm_dev = crtc->dev;
	10353	+ struct rockchip_drm_private *private = drm_dev->dev_private;
6450	10354	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
6451	10355	struct drm_mode_config *mode_config = &drm_dev->mode_config;
6452	10356	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6453		- struct vop2 *vop2 = vp->vop2;
	10357	+ bool replaced = false;
	10358	+ int ret;
6454	10359
6455	10360	if (property == mode_config->tv_left_margin_property) {
6456	10361	vcstate->left_margin = val;
..	..	@@ -6473,14 +10378,66 @@
6473	10378	}
6474	10379
6475	10380
6476		- if (property == vop2->bg_prop) {
	10381	+ if (property == private->bg_prop) {
6477	10382	vcstate->background = val;
6478	10383	return 0;
6479	10384	}
6480	10385
6481		- if (property == vop2->line_flag_prop) {
	10386	+ if (property == private->line_flag_prop) {
6482	10387	vcstate->line_flag = val;
6483	10388	return 0;
	10389	+ }
	10390	+
	10391	+ if (property == vp->variable_refresh_rate_prop) {
	10392	+ vcstate->request_refresh_rate = val;
	10393	+ return 0;
	10394	+ }
	10395	+
	10396	+ if (property == vp->max_refresh_rate_prop) {
	10397	+ vcstate->max_refresh_rate = val;
	10398	+ return 0;
	10399	+ }
	10400	+
	10401	+ if (property == vp->min_refresh_rate_prop) {
	10402	+ vcstate->min_refresh_rate = val;
	10403	+ return 0;
	10404	+ }
	10405	+
	10406	+ if (property == vp->hdr_ext_data_prop) {
	10407	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10408	+ &vcstate->hdr_ext_data,
	10409	+ val,
	10410	+ -1, -1,
	10411	+ &replaced);
	10412	+ return ret;
	10413	+ }
	10414	+
	10415	+ if (property == vp->acm_lut_data_prop) {
	10416	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10417	+ &vcstate->acm_lut_data,
	10418	+ val,
	10419	+ sizeof(struct post_acm), -1,
	10420	+ &replaced);
	10421	+ return ret;
	10422	+ }
	10423	+
	10424	+ if (property == vp->post_csc_data_prop) {
	10425	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10426	+ &vcstate->post_csc_data,
	10427	+ val,
	10428	+ sizeof(struct post_csc), -1,
	10429	+ &replaced);
	10430	+ return ret;
	10431	+ }
	10432	+
	10433	+ if (property == private->cubic_lut_prop) {
	10434	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10435	+ &vcstate->cubic_lut_data,
	10436	+ val,
	10437	+ -1, sizeof(struct drm_color_lut),
	10438	+ &replaced);
	10439	+ state->color_mgmt_changed \|= replaced;
	10440	+ return ret;
6484	10441	}
6485	10442
6486	10443	DRM_ERROR("failed to set vop2 crtc property %s\n", property->name);
..	..	@@ -6509,7 +10466,7 @@
6509	10466	struct vop2_video_port *vp = container_of(work, struct vop2_video_port, fb_unref_work);
6510	10467	struct drm_framebuffer *fb = val;
6511	10468
6512		- drm_crtc_vblank_put(&vp->crtc);
	10469	+ drm_crtc_vblank_put(&vp->rockchip_crtc.crtc);
6513	10470	if (!vp->vop2->skip_ref_fb)
6514	10471	drm_framebuffer_put(fb);
6515	10472	}
..	..	@@ -6580,6 +10537,7 @@
6580	10537	struct vop2_wb *wb = &vop2->wb;
6581	10538
6582	10539	VOP_MODULE_SET(vop2, wb, enable, 0);
	10540	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 0);
6583	10541	vop2_wb_cfg_done(vp);
6584	10542	}
6585	10543
..	..	@@ -6618,6 +10576,43 @@
6618	10576	}
6619	10577	}
6620	10578	spin_unlock_irqrestore(&wb->job_lock, flags);
	10579	+}
	10580	+
	10581	+static void vop2_dsc_isr(struct vop2 *vop2)
	10582	+{
	10583	+ const struct vop2_data *vop2_data = vop2->data;
	10584	+ struct vop2_dsc *dsc;
	10585	+ const struct dsc_error_info *dsc_error_ecw = vop2_data->dsc_error_ecw;
	10586	+ const struct dsc_error_info *dsc_error_buffer_flow = vop2_data->dsc_error_buffer_flow;
	10587	+ u32 dsc_error_status = 0, dsc_ecw = 0;
	10588	+ int i = 0, j = 0;
	10589	+
	10590	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	10591	+ dsc = &vop2->dscs[i];
	10592	+
	10593	+ if (!dsc->enabled)
	10594	+ continue;
	10595	+
	10596	+ dsc_error_status = VOP_MODULE_GET(vop2, dsc, dsc_error_status);
	10597	+ if (!dsc_error_status)
	10598	+ continue;
	10599	+ dsc_ecw = VOP_MODULE_GET(vop2, dsc, dsc_ecw);
	10600	+
	10601	+ for (j = 0; j < vop2_data->nr_dsc_ecw; j++) {
	10602	+ if (dsc_ecw == dsc_error_ecw[j].dsc_error_val) {
	10603	+ DRM_ERROR("dsc%d %s\n", dsc->id, dsc_error_ecw[j].dsc_error_info);
	10604	+ break;
	10605	+ }
	10606	+ }
	10607	+
	10608	+ if (dsc_ecw == 0x0120ffff) {
	10609	+ u32 offset = dsc->regs->dsc_status.offset;
	10610	+
	10611	+ for (j = 0; j < vop2_data->nr_dsc_buffer_flow; j++)
	10612	+ DRM_ERROR("dsc%d %s:0x%x\n", dsc->id, dsc_error_buffer_flow[j].dsc_error_info,
	10613	+ vop2_readl(vop2, offset + (j << 2)));
	10614	+ }
	10615	+ }
6621	10616	}
6622	10617
6623	10618	static irqreturn_t vop2_isr(int irq, void *data)
..	..	@@ -6674,7 +10669,7 @@
6674	10669
6675	10670	for (i = 0; i < vp_max; i++) {
6676	10671	vp = &vop2->vps[i];
6677		- crtc = &vp->crtc;
	10672	+ crtc = &vp->rockchip_crtc.crtc;
6678	10673	active_irqs = vp_irqs[i];
6679	10674	if (active_irqs & DSP_HOLD_VALID_INTR) {
6680	10675	complete(&vp->dsp_hold_completion);
..	..	@@ -6694,7 +10689,18 @@
6694	10689	ret = IRQ_HANDLED;
6695	10690	}
6696	10691
	10692	+ if (vop2->version == VOP_VERSION_RK3528 && vp->id == 1) {
	10693	+ if (active_irqs & POST_BUF_EMPTY_INTR)
	10694	+ atomic_inc(&vp->post_buf_empty_flag);
	10695	+
	10696	+ if (active_irqs & FS_FIELD_INTR &&
	10697	+ (atomic_read(&vp->post_buf_empty_flag) > 0 \|\|
	10698	+ vp->need_reset_p2i_flag == true))
	10699	+ queue_work(vop2->workqueue, &vop2->post_buf_empty_work);
	10700	+ }
	10701	+
6697	10702	if (active_irqs & FS_FIELD_INTR) {
	10703	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_VSYNC, "vsync_vp%d\n", vp->id);
6698	10704	vop2_wb_handler(vp);
6699	10705	if (likely(!vp->skip_vsync) \|\| (vp->layer_sel_update == false)) {
6700	10706	drm_crtc_handle_vblank(crtc);
..	..	@@ -6726,6 +10732,9 @@
6726	10732	if (active_irqs)
6727	10733	DRM_ERROR("Unknown axi_bus%d IRQs: %02x\n", i, active_irqs);
6728	10734	}
	10735	+
	10736	+ if (vop2->data->nr_dscs)
	10737	+ vop2_dsc_isr(vop2);
6729	10738
6730	10739	vop2_core_clks_disable(vop2);
6731	10740	out:
..	..	@@ -6784,6 +10793,51 @@
6784	10793	return 0;
6785	10794	}
6786	10795
	10796	+static bool vop3_ignore_plane(struct vop2 vop2, struct vop2_win win)
	10797	+{
	10798	+ if (!is_vop3(vop2))
	10799	+ return false;
	10800	+
	10801	+ if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE &&
	10802	+ win->phys_id != ROCKCHIP_VOP2_ESMART0)
	10803	+ return true;
	10804	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE &&
	10805	+ (win->phys_id == ROCKCHIP_VOP2_ESMART1 \|\| win->phys_id == ROCKCHIP_VOP2_ESMART3))
	10806	+ return true;
	10807	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE &&
	10808	+ win->phys_id == ROCKCHIP_VOP2_ESMART1)
	10809	+ return true;
	10810	+ else
	10811	+ return false;
	10812	+}
	10813	+
	10814	+static u32 vop3_esmart_linebuffer_size(struct vop2 vop2, struct vop2_win win)
	10815	+{
	10816	+ if (!is_vop3(vop2) \|\| vop2_cluster_window(win))
	10817	+ return vop2->data->max_output.width;
	10818	+
	10819	+ if (vop2->esmart_lb_mode == VOP3_ESMART_2K_2K_2K_2K_MODE \|\|
	10820	+ (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE && win->phys_id != ROCKCHIP_VOP2_ESMART0))
	10821	+ return vop2->data->max_output.width / 2;
	10822	+ else
	10823	+ return vop2->data->max_output.width;
	10824	+}
	10825	+
	10826	+static void vop3_init_esmart_scale_engine(struct vop2 *vop2)
	10827	+{
	10828	+ u8 scale_engine_num = 0;
	10829	+ struct drm_plane *plane = NULL;
	10830	+
	10831	+ drm_for_each_plane(plane, vop2->drm_dev) {
	10832	+ struct vop2_win *win = to_vop2_win(plane);
	10833	+
	10834	+ if (win->parent \|\| vop2_cluster_window(win))
	10835	+ continue;
	10836	+
	10837	+ win->scale_engine_num = scale_engine_num++;
	10838	+ }
	10839	+}
	10840	+
6787	10841	static int vop2_plane_init(struct vop2 vop2, struct vop2_win win, unsigned long possible_crtcs)
6788	10842	{
6789	10843	struct rockchip_drm_private *private = vop2->drm_dev->dev_private;
..	..	@@ -6807,6 +10861,10 @@
6807	10861	if (win->feature & WIN_FEATURE_CLUSTER_SUB)
6808	10862	return -EACCES;
6809	10863	}
	10864	+
	10865	+ /* ignore some plane register according vop3 esmart lb mode */
	10866	+ if (vop3_ignore_plane(vop2, win))
	10867	+ return -EACCES;
6810	10868
6811	10869	ret = drm_universal_plane_init(vop2->drm_dev, &win->base, possible_crtcs,
6812	10870	&vop2_plane_funcs, win->formats, win->nformats,
..	..	@@ -6847,7 +10905,7 @@
6847	10905	"INPUT_WIDTH", 0, max_width);
6848	10906	win->input_height_prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE,
6849	10907	"INPUT_HEIGHT", 0, max_height);
6850		- max_width = vop2->data->max_output.width;
	10908	+ max_width = vop3_esmart_linebuffer_size(vop2, win);
6851	10909	max_height = vop2->data->max_output.height;
6852	10910	if (win->feature & WIN_FEATURE_CLUSTER_SUB)
6853	10911	max_width >>= 1;
..	..	@@ -6883,15 +10941,27 @@
6883	10941	return 0;
6884	10942	}
6885	10943
6886		-static struct drm_plane vop2_cursor_plane_init(struct vop2_video_port vp,
6887		- unsigned long possible_crtcs)
	10944	+static struct drm_plane vop2_cursor_plane_init(struct vop2_video_port vp)
6888	10945	{
6889	10946	struct vop2 *vop2 = vp->vop2;
6890	10947	struct drm_plane *cursor = NULL;
6891	10948	struct vop2_win *win;
	10949	+ unsigned long possible_crtcs = 0;
6892	10950
6893	10951	win = vop2_find_win_by_phys_id(vop2, vp->cursor_win_id);
6894	10952	if (win) {
	10953	+ if (vop2->disable_win_move) {
	10954	+ const struct vop2_data *vop2_data = vop2->data;
	10955	+ struct drm_crtc *crtc = vop2_find_crtc_by_plane_mask(vop2, win->phys_id);
	10956	+
	10957	+ if (crtc)
	10958	+ possible_crtcs = drm_crtc_mask(crtc);
	10959	+ else
	10960	+ possible_crtcs = (1 << vop2_data->nr_vps) - 1;
	10961	+ }
	10962	+
	10963	+ if (win->possible_crtcs)
	10964	+ possible_crtcs = win->possible_crtcs;
6895	10965	win->type = DRM_PLANE_TYPE_CURSOR;
6896	10966	win->zpos = vop2->registered_num_wins - 1;
6897	10967	if (!vop2_plane_init(vop2, win, possible_crtcs))
..	..	@@ -6917,7 +10987,7 @@
6917	10987
6918	10988	for (i = 0; i < vop2_data->nr_vps; i++) {
6919	10989	vp = &vop2->vps[i];
6920		- crtc = &vp->crtc;
	10990	+ crtc = &vp->rockchip_crtc.crtc;
6921	10991	if (!crtc->dev)
6922	10992	continue;
6923	10993	vp_data = &vop2_data->vp[vp->id];
..	..	@@ -6925,6 +10995,7 @@
6925	10995	if (!lut_len)
6926	10996	continue;
6927	10997	vp->gamma_lut_len = vp_data->gamma_lut_len;
	10998	+ vp->lut_dma_rid = vp_data->lut_dma_rid;
6928	10999	vp->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vp->lut),
6929	11000	GFP_KERNEL);
6930	11001	if (!vp->lut)
..	..	@@ -6951,27 +11022,6 @@
6951	11022	}
6952	11023
6953	11024	return 0;
6954		-}
6955		-
6956		-static void vop2_cubic_lut_init(struct vop2 *vop2)
6957		-{
6958		- const struct vop2_data *vop2_data = vop2->data;
6959		- const struct vop2_video_port_data *vp_data;
6960		- struct vop2_video_port *vp;
6961		- struct drm_crtc *crtc;
6962		- int i;
6963		-
6964		- for (i = 0; i < vop2_data->nr_vps; i++) {
6965		- vp = &vop2->vps[i];
6966		- crtc = &vp->crtc;
6967		- if (!crtc->dev)
6968		- continue;
6969		- vp_data = &vop2_data->vp[vp->id];
6970		- vp->cubic_lut_len = vp_data->cubic_lut_len;
6971		-
6972		- if (vp->cubic_lut_len)
6973		- drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
6974		- }
6975	11025	}
6976	11026
6977	11027	static int vop2_crtc_create_plane_mask_property(struct vop2 *vop2,
..	..	@@ -7009,6 +11059,142 @@
7009	11059	return 0;
7010	11060	}
7011	11061
	11062	+static int vop2_crtc_create_feature_property(struct vop2 vop2, struct drm_crtc crtc)
	11063	+{
	11064	+ const struct vop2_data *vop2_data = vop2->data;
	11065	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11066	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	11067	+ struct drm_property *prop;
	11068	+ u64 feature = 0;
	11069	+
	11070	+ static const struct drm_prop_enum_list props[] = {
	11071	+ { ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE, "ALPHA_SCALE" },
	11072	+ { ROCKCHIP_DRM_CRTC_FEATURE_HDR10, "HDR10" },
	11073	+ { ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR, "NEXT_HDR" },
	11074	+ { ROCKCHIP_DRM_CRTC_FEATURE_VIVID_HDR, "VIVID_HDR" },
	11075	+ };
	11076	+
	11077	+ if (vp_data->feature & VOP_FEATURE_ALPHA_SCALE)
	11078	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE);
	11079	+ if (vp_data->feature & VOP_FEATURE_HDR10)
	11080	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_HDR10);
	11081	+ if (vp_data->feature & VOP_FEATURE_NEXT_HDR)
	11082	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR);
	11083	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	11084	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_VIVID_HDR);
	11085	+
	11086	+ prop = drm_property_create_bitmask(vop2->drm_dev,
	11087	+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
	11088	+ props, ARRAY_SIZE(props),
	11089	+ 0xffffffff);
	11090	+ if (!prop) {
	11091	+ DRM_DEV_ERROR(vop2->dev, "create FEATURE prop for vp%d failed\n", vp->id);
	11092	+ return -ENOMEM;
	11093	+ }
	11094	+
	11095	+ vp->feature_prop = prop;
	11096	+ drm_object_attach_property(&crtc->base, vp->feature_prop, feature);
	11097	+
	11098	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_WIDTH",
	11099	+ 0, vop2->data->vp[vp->id].max_output.width);
	11100	+ if (!prop) {
	11101	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_WIDTH prop for vp%d failed\n", vp->id);
	11102	+ return -ENOMEM;
	11103	+ }
	11104	+ vp->output_width_prop = prop;
	11105	+ drm_object_attach_property(&crtc->base, vp->output_width_prop, 0);
	11106	+
	11107	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK",
	11108	+ 0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000);
	11109	+ if (!prop) {
	11110	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id);
	11111	+ return -ENOMEM;
	11112	+ }
	11113	+ vp->output_dclk_prop = prop;
	11114	+ drm_object_attach_property(&crtc->base, vp->output_dclk_prop, 0);
	11115	+
	11116	+ return 0;
	11117	+}
	11118	+
	11119	+static int vop2_crtc_create_vrr_property(struct vop2 vop2, struct drm_crtc crtc)
	11120	+{
	11121	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11122	+ struct drm_property *prop;
	11123	+
	11124	+ prop = drm_property_create_range(vop2->drm_dev, 0, "variable refresh rate", 0, 144);
	11125	+ if (!prop) {
	11126	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	11127	+ return -ENOMEM;
	11128	+ }
	11129	+ vp->variable_refresh_rate_prop = prop;
	11130	+ drm_object_attach_property(&crtc->base, vp->variable_refresh_rate_prop, 0);
	11131	+
	11132	+ prop = drm_property_create_range(vop2->drm_dev, 0, "max refresh rate", 0, 144);
	11133	+ if (!prop) {
	11134	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	11135	+ return -ENOMEM;
	11136	+ }
	11137	+ vp->max_refresh_rate_prop = prop;
	11138	+ drm_object_attach_property(&crtc->base, vp->max_refresh_rate_prop, 0);
	11139	+
	11140	+ prop = drm_property_create_range(vop2->drm_dev, 0, "min refresh rate", 0, 144);
	11141	+ if (!prop) {
	11142	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	11143	+ return -ENOMEM;
	11144	+ }
	11145	+ vp->min_refresh_rate_prop = prop;
	11146	+ drm_object_attach_property(&crtc->base, vp->min_refresh_rate_prop, 0);
	11147	+
	11148	+ return 0;
	11149	+}
	11150	+
	11151	+static int vop2_crtc_create_hdr_property(struct vop2 vop2, struct drm_crtc crtc)
	11152	+{
	11153	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11154	+ struct drm_property *prop;
	11155	+
	11156	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "HDR_EXT_DATA", 0);
	11157	+ if (!prop) {
	11158	+ DRM_DEV_ERROR(vop2->dev, "create hdr ext data prop for vp%d failed\n", vp->id);
	11159	+ return -ENOMEM;
	11160	+ }
	11161	+ vp->hdr_ext_data_prop = prop;
	11162	+ drm_object_attach_property(&crtc->base, vp->hdr_ext_data_prop, 0);
	11163	+
	11164	+ return 0;
	11165	+}
	11166	+
	11167	+static int vop2_crtc_create_post_acm_property(struct vop2 vop2, struct drm_crtc crtc)
	11168	+{
	11169	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11170	+ struct drm_property *prop;
	11171	+
	11172	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "ACM_LUT_DATA", 0);
	11173	+ if (!prop) {
	11174	+ DRM_DEV_ERROR(vop2->dev, "create acm lut data prop for vp%d failed\n", vp->id);
	11175	+ return -ENOMEM;
	11176	+ }
	11177	+ vp->acm_lut_data_prop = prop;
	11178	+ drm_object_attach_property(&crtc->base, vp->acm_lut_data_prop, 0);
	11179	+
	11180	+ return 0;
	11181	+}
	11182	+
	11183	+static int vop2_crtc_create_post_csc_property(struct vop2 vop2, struct drm_crtc crtc)
	11184	+{
	11185	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11186	+ struct drm_property *prop;
	11187	+
	11188	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "POST_CSC_DATA", 0);
	11189	+ if (!prop) {
	11190	+ DRM_DEV_ERROR(vop2->dev, "create post csc data prop for vp%d failed\n", vp->id);
	11191	+ return -ENOMEM;
	11192	+ }
	11193	+ vp->post_csc_data_prop = prop;
	11194	+ drm_object_attach_property(&crtc->base, vp->post_csc_data_prop, 0);
	11195	+
	11196	+ return 0;
	11197	+}
7012	11198	#define RK3566_MIRROR_PLANE_MASK (BIT(ROCKCHIP_VOP2_CLUSTER1) \| BIT(ROCKCHIP_VOP2_ESMART1) \| \
7013	11199	BIT(ROCKCHIP_VOP2_SMART1))
7014	11200
..	..	@@ -7021,7 +11207,7 @@
7021	11207	const struct vop2_data *vop2_data = vop2->data;
7022	11208	struct drm_device *drm_dev = vop2->drm_dev;
7023	11209	struct device *dev = vop2->dev;
7024		- struct drm_plane *plane;
	11210	+ struct drm_plane *primary;
7025	11211	struct drm_plane *cursor = NULL;
7026	11212	struct drm_crtc *crtc;
7027	11213	struct device_node *port;
..	..	@@ -7032,12 +11218,13 @@
7032	11218	uint64_t soc_id;
7033	11219	uint32_t registered_num_crtcs = 0;
7034	11220	uint32_t plane_mask = 0;
7035		- char dclk_name[9];
	11221	+ char clk_name[16];
7036	11222	int i = 0, j = 0, k = 0;
7037	11223	int ret = 0;
7038	11224	bool be_used_for_primary_plane = false;
7039	11225	bool find_primary_plane = false;
7040	11226	bool bootloader_initialized = false;
	11227	+ struct rockchip_drm_private *private = drm_dev->dev_private;
7041	11228
7042	11229	/* all planes can attach to any crtc */
7043	11230	possible_crtcs = (1 << vop2_data->nr_vps) - 1;
..	..	@@ -7069,6 +11256,9 @@
7069	11256	vp->id = vp_data->id;
7070	11257	vp->regs = vp_data->regs;
7071	11258	vp->cursor_win_id = -1;
	11259	+ primary = NULL;
	11260	+ cursor = NULL;
	11261	+
7072	11262	if (vop2->disable_win_move)
7073	11263	possible_crtcs = BIT(registered_num_crtcs);
7074	11264
..	..	@@ -7084,14 +11274,27 @@
7084	11274	else
7085	11275	soc_id = vp_data->soc_id[0];
7086	11276
7087		- snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
7088		- vp->dclk = devm_clk_get(vop2->dev, dclk_name);
	11277	+ snprintf(clk_name, sizeof(clk_name), "dclk_vp%d", vp->id);
	11278	+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, clk_name);
	11279	+ if (IS_ERR(vp->dclk_rst)) {
	11280	+ DRM_DEV_ERROR(vop2->dev, "failed to get dclk reset\n");
	11281	+ return PTR_ERR(vp->dclk_rst);
	11282	+ }
	11283	+
	11284	+ vp->dclk = devm_clk_get(vop2->dev, clk_name);
7089	11285	if (IS_ERR(vp->dclk)) {
7090		- DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", dclk_name);
	11286	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
7091	11287	return PTR_ERR(vp->dclk);
7092	11288	}
7093	11289
7094		- crtc = &vp->crtc;
	11290	+ snprintf(clk_name, sizeof(clk_name), "dclk_src_vp%d", vp->id);
	11291	+ vp->dclk_parent = devm_clk_get_optional(vop2->dev, clk_name);
	11292	+ if (IS_ERR(vp->dclk)) {
	11293	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
	11294	+ return PTR_ERR(vp->dclk);
	11295	+ }
	11296	+
	11297	+ crtc = &vp->rockchip_crtc.crtc;
7095	11298
7096	11299	port = of_graph_get_port_by_id(dev->of_node, i);
7097	11300	if (!port) {
..	..	@@ -7116,6 +11319,7 @@
7116	11319	win->type = DRM_PLANE_TYPE_PRIMARY;
7117	11320	}
7118	11321	} else {
	11322	+ j = 0;
7119	11323	while (j < vop2->registered_num_wins) {
7120	11324	be_used_for_primary_plane = false;
7121	11325	win = &vop2->win[j];
..	..	@@ -7157,24 +11361,43 @@
7157	11361	DRM_DEV_ERROR(vop2->dev, "failed to init primary plane\n");
7158	11362	break;
7159	11363	}
7160		- plane = &win->base;
	11364	+ primary = &win->base;
7161	11365	}
7162	11366
7163	11367	/* some times we want a cursor window for some vp */
	11368	+ if (vp->cursor_win_id < 0) {
	11369	+ bool be_used_for_cursor_plane = false;
	11370	+
	11371	+ j = 0;
	11372	+ while (j < vop2->registered_num_wins) {
	11373	+ win = &vop2->win[j++];
	11374	+
	11375	+ if (win->parent \|\| (win->feature & WIN_FEATURE_CLUSTER_SUB))
	11376	+ continue;
	11377	+
	11378	+ if (win->type != DRM_PLANE_TYPE_CURSOR)
	11379	+ continue;
	11380	+
	11381	+ for (k = 0; k < vop2_data->nr_vps; k++) {
	11382	+ if (vop2->vps[k].cursor_win_id == win->phys_id)
	11383	+ be_used_for_cursor_plane = true;
	11384	+ }
	11385	+ if (be_used_for_cursor_plane)
	11386	+ continue;
	11387	+ vp->cursor_win_id = win->phys_id;
	11388	+ }
	11389	+ }
	11390	+
7164	11391	if (vp->cursor_win_id >= 0) {
7165		- if (win->possible_crtcs)
7166		- possible_crtcs = win->possible_crtcs;
7167		- cursor = vop2_cursor_plane_init(vp, possible_crtcs);
	11392	+ cursor = vop2_cursor_plane_init(vp);
7168	11393	if (!cursor)
7169	11394	DRM_WARN("failed to init cursor plane for vp%d\n", vp->id);
7170	11395	else
7171	11396	DRM_DEV_INFO(vop2->dev, "%s as cursor plane for vp%d\n",
7172	11397	cursor->name, vp->id);
7173		- } else {
7174		- cursor = NULL;
7175	11398	}
7176	11399
7177		- ret = drm_crtc_init_with_planes(drm_dev, crtc, plane, cursor, &vop2_crtc_funcs,
	11400	+ ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, &vop2_crtc_funcs,
7178	11401	"video_port%d", vp->id);
7179	11402	if (ret) {
7180	11403	DRM_DEV_ERROR(vop2->dev, "crtc init for video_port%d failed\n", i);
..	..	@@ -7189,20 +11412,39 @@
7189	11412	init_completion(&vp->line_flag_completion);
7190	11413	rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
7191	11414	soc_id = vop2_soc_id_fixup(soc_id);
7192		- drm_object_attach_property(&crtc->base, vop2->soc_id_prop, soc_id);
7193		- drm_object_attach_property(&crtc->base, vop2->vp_id_prop, vp->id);
7194		- drm_object_attach_property(&crtc->base, vop2->aclk_prop, 0);
7195		- drm_object_attach_property(&crtc->base, vop2->bg_prop, 0);
7196		- drm_object_attach_property(&crtc->base, vop2->line_flag_prop, 0);
7197		- drm_object_attach_property(&crtc->base,
7198		- drm_dev->mode_config.tv_left_margin_property, 100);
7199		- drm_object_attach_property(&crtc->base,
7200		- drm_dev->mode_config.tv_right_margin_property, 100);
7201		- drm_object_attach_property(&crtc->base,
7202		- drm_dev->mode_config.tv_top_margin_property, 100);
7203		- drm_object_attach_property(&crtc->base,
7204		- drm_dev->mode_config.tv_bottom_margin_property, 100);
7205		- vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11415	+ drm_object_attach_property(&crtc->base, private->soc_id_prop, soc_id);
	11416	+ drm_object_attach_property(&crtc->base, private->port_id_prop, vp->id);
	11417	+ drm_object_attach_property(&crtc->base, private->aclk_prop, 0);
	11418	+ drm_object_attach_property(&crtc->base, private->bg_prop, 0);
	11419	+ drm_object_attach_property(&crtc->base, private->line_flag_prop, 0);
	11420	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN) {
	11421	+ drm_object_attach_property(&crtc->base,
	11422	+ drm_dev->mode_config.tv_left_margin_property, 100);
	11423	+ drm_object_attach_property(&crtc->base,
	11424	+ drm_dev->mode_config.tv_right_margin_property, 100);
	11425	+ drm_object_attach_property(&crtc->base,
	11426	+ drm_dev->mode_config.tv_top_margin_property, 100);
	11427	+ drm_object_attach_property(&crtc->base,
	11428	+ drm_dev->mode_config.tv_bottom_margin_property, 100);
	11429	+ }
	11430	+ if (plane_mask)
	11431	+ vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11432	+ vop2_crtc_create_feature_property(vop2, crtc);
	11433	+ vop2_crtc_create_vrr_property(vop2, crtc);
	11434	+
	11435	+ ret = drm_self_refresh_helper_init(crtc);
	11436	+ if (ret)
	11437	+ DRM_DEV_DEBUG_KMS(vop2->dev,
	11438	+ "Failed to init %s with SR helpers %d, ignoring\n",
	11439	+ crtc->name, ret);
	11440	+
	11441	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	11442	+ vop2_crtc_create_hdr_property(vop2, crtc);
	11443	+ if (vp_data->feature & VOP_FEATURE_POST_ACM)
	11444	+ vop2_crtc_create_post_acm_property(vop2, crtc);
	11445	+ if (vp_data->feature & VOP_FEATURE_POST_CSC)
	11446	+ vop2_crtc_create_post_csc_property(vop2, crtc);
	11447	+
7206	11448	registered_num_crtcs++;
7207	11449	}
7208	11450
..	..	@@ -7257,8 +11499,11 @@
7257	11499
7258	11500	ret = vop2_plane_init(vop2, win, possible_crtcs);
7259	11501	if (ret)
7260		- DRM_WARN("failed to init overlay plane %s, ret:%d\n", win->name, ret);
	11502	+ DRM_WARN("failed to init overlay plane %s\n", win->name);
7261	11503	}
	11504	+
	11505	+ if (is_vop3(vop2))
	11506	+ vop3_init_esmart_scale_engine(vop2);
7262	11507
7263	11508	return registered_num_crtcs;
7264	11509	}
..	..	@@ -7266,6 +11511,10 @@
7266	11511	static void vop2_destroy_crtc(struct drm_crtc *crtc)
7267	11512	{
7268	11513	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11514	+
	11515	+ drm_self_refresh_helper_cleanup(crtc);
	11516	+ if (vp->hdr_lut_gem_obj)
	11517	+ rockchip_gem_free_object(&vp->hdr_lut_gem_obj->base);
7269	11518
7270	11519	of_node_put(crtc->port);
7271	11520
..	..	@@ -7277,6 +11526,59 @@
7277	11526	drm_flip_work_cleanup(&vp->fb_unref_work);
7278	11527	}
7279	11528
	11529	+static int vop2_pd_data_init(struct vop2 *vop2)
	11530	+{
	11531	+ const struct vop2_data *vop2_data = vop2->data;
	11532	+ const struct vop2_power_domain_data *pd_data;
	11533	+ struct vop2_power_domain *pd;
	11534	+ int i;
	11535	+
	11536	+ INIT_LIST_HEAD(&vop2->pd_list_head);
	11537	+
	11538	+ for (i = 0; i < vop2_data->nr_pds; i++) {
	11539	+ pd_data = &vop2_data->pd[i];
	11540	+ pd = devm_kzalloc(vop2->dev, sizeof(*pd), GFP_KERNEL);
	11541	+ if (!pd)
	11542	+ return -ENOMEM;
	11543	+ pd->vop2 = vop2;
	11544	+ pd->data = pd_data;
	11545	+ pd->vp_mask = 0;
	11546	+ spin_lock_init(&pd->lock);
	11547	+ list_add_tail(&pd->list, &vop2->pd_list_head);
	11548	+ INIT_DELAYED_WORK(&pd->power_off_work, vop2_power_domain_off_work);
	11549	+ if (pd_data->parent_id) {
	11550	+ pd->parent = vop2_find_pd_by_id(vop2, pd_data->parent_id);
	11551	+ if (!pd->parent) {
	11552	+ DRM_DEV_ERROR(vop2->dev, "no parent pd find for pd%d\n", pd->data->id);
	11553	+ return -EINVAL;
	11554	+ }
	11555	+ }
	11556	+ }
	11557	+
	11558	+ return 0;
	11559	+}
	11560	+
	11561	+static void vop2_dsc_data_init(struct vop2 *vop2)
	11562	+{
	11563	+ const struct vop2_data *vop2_data = vop2->data;
	11564	+ const struct vop2_dsc_data *dsc_data;
	11565	+ struct vop2_dsc *dsc;
	11566	+ int i;
	11567	+
	11568	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	11569	+ dsc = &vop2->dscs[i];
	11570	+ dsc_data = &vop2_data->dsc[i];
	11571	+ dsc->id = dsc_data->id;
	11572	+ dsc->max_slice_num = dsc_data->max_slice_num;
	11573	+ dsc->max_linebuf_depth = dsc_data->max_linebuf_depth;
	11574	+ dsc->min_bits_per_pixel = dsc_data->min_bits_per_pixel;
	11575	+ dsc->regs = dsc_data->regs;
	11576	+ dsc->attach_vp_id = -1;
	11577	+ if (dsc_data->pd_id)
	11578	+ dsc->pd = vop2_find_pd_by_id(vop2, dsc_data->pd_id);
	11579	+ }
	11580	+}
	11581	+
7280	11582	static int vop2_win_init(struct vop2 *vop2)
7281	11583	{
7282	11584	const struct vop2_data *vop2_data = vop2->data;
..	..	@@ -7284,7 +11586,6 @@
7284	11586	struct drm_prop_enum_list *plane_name_list;
7285	11587	struct vop2_win *win;
7286	11588	struct vop2_layer *layer;
7287		- struct drm_property *prop;
7288	11589	char name[DRM_PROP_NAME_LEN];
7289	11590	unsigned int num_wins = 0;
7290	11591	uint8_t plane_id = 0;
..	..	@@ -7313,6 +11614,7 @@
7313	11614	win->dly = win_data->dly;
7314	11615	win->feature = win_data->feature;
7315	11616	win->phys_id = win_data->phys_id;
	11617	+ win->splice_win_id = win_data->splice_win_id;
7316	11618	win->layer_sel_id = win_data->layer_sel_id;
7317	11619	win->win_id = i;
7318	11620	win->plane_id = plane_id++;
..	..	@@ -7322,8 +11624,10 @@
7322	11624	win->axi_id = win_data->axi_id;
7323	11625	win->axi_yrgb_id = win_data->axi_yrgb_id;
7324	11626	win->axi_uv_id = win_data->axi_uv_id;
7325		- win->scale_engine_num = win_data->scale_engine_num;
7326	11627	win->possible_crtcs = win_data->possible_crtcs;
	11628	+
	11629	+ if (win_data->pd_id)
	11630	+ win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id);
7327	11631
7328	11632	num_wins++;
7329	11633
..	..	@@ -7351,6 +11655,7 @@
7351	11655	area->vsd_filter_mode = win_data->vsd_filter_mode;
7352	11656	area->hsd_pre_filter_mode = win_data->hsd_pre_filter_mode;
7353	11657	area->vsd_pre_filter_mode = win_data->vsd_pre_filter_mode;
	11658	+ area->possible_crtcs = win->possible_crtcs;
7354	11659
7355	11660	area->vop2 = vop2;
7356	11661	area->win_id = i;
..	..	@@ -7363,6 +11668,7 @@
7363	11668	num_wins++;
7364	11669	}
7365	11670	}
	11671	+
7366	11672	vop2->registered_num_wins = num_wins;
7367	11673
7368	11674	if (!is_vop3(vop2)) {
..	..	@@ -7390,28 +11696,136 @@
7390	11696
7391	11697	vop2->plane_name_list = plane_name_list;
7392	11698
7393		- prop = drm_property_create_object(vop2->drm_dev,
7394		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
7395		- "SOC_ID", DRM_MODE_OBJECT_CRTC);
7396		- vop2->soc_id_prop = prop;
	11699	+ return 0;
	11700	+}
7397	11701
7398		- prop = drm_property_create_object(vop2->drm_dev,
7399		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
7400		- "PORT_ID", DRM_MODE_OBJECT_CRTC);
7401		- vop2->vp_id_prop = prop;
	11702	+#include "rockchip_vop2_clk.c"
	11703	+static void post_buf_empty_work_event(struct work_struct *work)
	11704	+{
	11705	+ struct vop2 *vop2 = container_of(work, struct vop2, post_buf_empty_work);
	11706	+ struct rockchip_drm_private *private = vop2->drm_dev->dev_private;
	11707	+ struct vop2_video_port *vp = &vop2->vps[1];
7402	11708
7403		- vop2->aclk_prop = drm_property_create_range(vop2->drm_dev, 0, "ACLK", 0, UINT_MAX);
7404		- vop2->bg_prop = drm_property_create_range(vop2->drm_dev, 0, "BACKGROUND", 0, UINT_MAX);
	11709	+ /*
	11710	+ * For RK3528, VP1 only supports NTSC and PAL mode(both interlace). If
	11711	+ * POST_BUF_EMPTY_INTR comes, it is needed to reset the p2i_en bit, in
	11712	+ * order to update the line parity flag, which ensures the correct order
	11713	+ * of odd and even lines.
	11714	+ */
	11715	+ if (vop2->version == VOP_VERSION_RK3528) {
	11716	+ if (atomic_read(&vp->post_buf_empty_flag) > 0) {
	11717	+ atomic_set(&vp->post_buf_empty_flag, 0);
7405	11718
7406		- vop2->line_flag_prop = drm_property_create_range(vop2->drm_dev, 0, "LINE_FLAG1", 0, UINT_MAX);
	11719	+ mutex_lock(&private->ovl_lock);
	11720	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11721	+ VOP_MODULE_SET(vop2, vp, p2i_en, 0);
	11722	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	11723	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11724	+ mutex_unlock(&private->ovl_lock);
7407	11725
7408		- if (!vop2->soc_id_prop \|\| !vop2->vp_id_prop \|\| !vop2->aclk_prop \|\| !vop2->bg_prop \|\|
7409		- !vop2->line_flag_prop) {
7410		- DRM_DEV_ERROR(vop2->dev, "failed to create soc_id/vp_id/aclk property\n");
7411		- return -ENOMEM;
	11726	+ vp->need_reset_p2i_flag = true;
	11727	+ } else if (vp->need_reset_p2i_flag == true) {
	11728	+ mutex_lock(&private->ovl_lock);
	11729	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11730	+ VOP_MODULE_SET(vop2, vp, p2i_en, 1);
	11731	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	11732	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11733	+ mutex_unlock(&private->ovl_lock);
	11734	+
	11735	+ vp->need_reset_p2i_flag = false;
	11736	+ }
	11737	+ }
	11738	+}
	11739	+
	11740	+static bool vop2_plane_mask_check(struct vop2 *vop2)
	11741	+{
	11742	+ const struct vop2_data *vop2_data = vop2->data;
	11743	+ u32 plane_mask = 0;
	11744	+ int i;
	11745	+
	11746	+ /*
	11747	+ * For RK3568 and RK3588, all windows need to be assigned to
	11748	+ * one of all vps, and two of vps can not share the same window.
	11749	+ */
	11750	+ if (vop2->version != VOP_VERSION_RK3568 && vop2->version != VOP_VERSION_RK3588)
	11751	+ return true;
	11752	+
	11753	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	11754	+ if (plane_mask & vop2->vps[i].plane_mask) {
	11755	+ DRM_WARN("the same window can't be assigned to two vp\n");
	11756	+ return false;
	11757	+ }
	11758	+ plane_mask \|= vop2->vps[i].plane_mask;
7412	11759	}
7413	11760
7414		- return 0;
	11761	+ if (hweight32(plane_mask) != vop2_data->nr_layers \|\|
	11762	+ plane_mask != vop2_data->plane_mask_base) {
	11763	+ DRM_WARN("all windows should be assigned, full plane mask: 0x%x, current plane mask: 0x%x\n",
	11764	+ vop2_data->plane_mask_base, plane_mask);
	11765	+ return false;
	11766	+ }
	11767	+
	11768	+ return true;
	11769	+}
	11770	+
	11771	+static uint32_t vop2_vp_plane_mask_to_bitmap(const struct vop2_vp_plane_mask *vp_plane_mask)
	11772	+{
	11773	+ int layer_phy_id = 0;
	11774	+ int plane_mask = 0;
	11775	+ int i;
	11776	+
	11777	+ for (i = 0; i < vp_plane_mask->attached_layers_nr; i++) {
	11778	+ layer_phy_id = vp_plane_mask->attached_layers[i];
	11779	+ plane_mask \|= BIT(layer_phy_id);
	11780	+ }
	11781	+
	11782	+ return plane_mask;
	11783	+}
	11784	+
	11785	+static bool vop2_get_vp_of_status(struct device_node *vp_node)
	11786	+{
	11787	+ struct device_node *vp_sub_node;
	11788	+ struct device_node *remote_node;
	11789	+ bool vp_enable = false;
	11790	+
	11791	+ for_each_child_of_node(vp_node, vp_sub_node) {
	11792	+ remote_node = of_graph_get_remote_endpoint(vp_sub_node);
	11793	+ vp_enable \|= of_device_is_available(remote_node);
	11794	+ }
	11795	+
	11796	+ return vp_enable;
	11797	+}
	11798	+
	11799	+static void vop2_plane_mask_assign(struct vop2 vop2, struct device_node vop_out_node)
	11800	+{
	11801	+ const struct vop2_data *vop2_data = vop2->data;
	11802	+ const struct vop2_vp_plane_mask *plane_mask;
	11803	+ struct device_node *child;
	11804	+ int active_vp_num = 0;
	11805	+ int vp_id;
	11806	+ int i = 0;
	11807	+
	11808	+ for_each_child_of_node(vop_out_node, child) {
	11809	+ if (vop2_get_vp_of_status(child))
	11810	+ active_vp_num++;
	11811	+ }
	11812	+
	11813	+ if (vop2_soc_is_rk3566() && active_vp_num > 2)
	11814	+ DRM_WARN("RK3566 only support 2 vps\n");
	11815	+ plane_mask = vop2_data->plane_mask;
	11816	+ plane_mask += (active_vp_num - 1) * ROCKCHIP_MAX_CRTC;
	11817	+
	11818	+ for_each_child_of_node(vop_out_node, child) {
	11819	+ of_property_read_u32(child, "reg", &vp_id);
	11820	+ if (vop2_get_vp_of_status(child)) {
	11821	+ vop2->vps[vp_id].plane_mask = vop2_vp_plane_mask_to_bitmap(&plane_mask[i]);
	11822	+ vop2->vps[vp_id].primary_plane_phy_id = plane_mask[i].primary_plane_id;
	11823	+ i++;
	11824	+ } else {
	11825	+ vop2->vps[vp_id].plane_mask = 0;
	11826	+ vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
	11827	+ }
	11828	+ }
7415	11829	}
7416	11830
7417	11831	static int vop2_bind(struct device dev, struct device master, void *data)
..	..	@@ -7426,6 +11840,7 @@
7426	11840	int num_wins = 0;
7427	11841	int registered_num_crtcs;
7428	11842	struct device_node *vop_out_node;
	11843	+ struct device_node *mcu_timing_node;
7429	11844
7430	11845	vop2_data = of_device_get_match_data(dev);
7431	11846	if (!vop2_data)
..	..	@@ -7454,6 +11869,26 @@
7454	11869	vop2->disable_afbc_win = of_property_read_bool(dev->of_node, "disable-afbc-win");
7455	11870	vop2->disable_win_move = of_property_read_bool(dev->of_node, "disable-win-move");
7456	11871	vop2->skip_ref_fb = of_property_read_bool(dev->of_node, "skip-ref-fb");
	11872	+
	11873	+ ret = vop2_pd_data_init(vop2);
	11874	+ if (ret)
	11875	+ return ret;
	11876	+ /*
	11877	+ * esmart lb mode default config at vop2_reg.c vop2_data.esmart_lb_mode,
	11878	+ * you can rewrite at dts vop node:
	11879	+ *
	11880	+ * VOP3_ESMART_8K_MODE = 0,
	11881	+ * VOP3_ESMART_4K_4K_MODE = 1,
	11882	+ * VOP3_ESMART_4K_2K_2K_MODE = 2,
	11883	+ * VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
	11884	+ *
	11885	+ * &vop {
	11886	+ * esmart_lb_mode = /bits/ 8 <2>;
	11887	+ * };
	11888	+ */
	11889	+ ret = of_property_read_u8(dev->of_node, "esmart_lb_mode", &vop2->esmart_lb_mode);
	11890	+ if (ret < 0)
	11891	+ vop2->esmart_lb_mode = vop2->data->esmart_lb_mode;
7457	11892
7458	11893	ret = vop2_win_init(vop2);
7459	11894	if (ret)
..	..	@@ -7488,7 +11923,10 @@
7488	11923	return PTR_ERR(vop2->acm_regs);
7489	11924	}
7490	11925
7491		- vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11926	+ vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11927	+ vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
	11928	+ vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
	11929	+ vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
7492	11930
7493	11931	vop2->hclk = devm_clk_get(vop2->dev, "hclk_vop");
7494	11932	if (IS_ERR(vop2->hclk)) {
..	..	@@ -7499,6 +11937,24 @@
7499	11937	if (IS_ERR(vop2->aclk)) {
7500	11938	DRM_DEV_ERROR(vop2->dev, "failed to get aclk source\n");
7501	11939	return PTR_ERR(vop2->aclk);
	11940	+ }
	11941	+
	11942	+ vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
	11943	+ if (IS_ERR(vop2->pclk)) {
	11944	+ DRM_DEV_ERROR(vop2->dev, "failed to get pclk source\n");
	11945	+ return PTR_ERR(vop2->pclk);
	11946	+ }
	11947	+
	11948	+ vop2->ahb_rst = devm_reset_control_get_optional(vop2->dev, "ahb");
	11949	+ if (IS_ERR(vop2->ahb_rst)) {
	11950	+ DRM_DEV_ERROR(vop2->dev, "failed to get ahb reset\n");
	11951	+ return PTR_ERR(vop2->ahb_rst);
	11952	+ }
	11953	+
	11954	+ vop2->axi_rst = devm_reset_control_get_optional(vop2->dev, "axi");
	11955	+ if (IS_ERR(vop2->axi_rst)) {
	11956	+ DRM_DEV_ERROR(vop2->dev, "failed to get axi reset\n");
	11957	+ return PTR_ERR(vop2->axi_rst);
7502	11958	}
7503	11959
7504	11960	vop2->irq = platform_get_irq(pdev, 0);
..	..	@@ -7515,6 +11971,7 @@
7515	11971	u32 plane_mask = 0;
7516	11972	u32 primary_plane_phy_id = 0;
7517	11973	u32 vp_id = 0;
	11974	+ u32 val = 0;
7518	11975
7519	11976	of_property_read_u32(child, "rockchip,plane-mask", &plane_mask);
7520	11977	of_property_read_u32(child, "rockchip,primary-plane", &primary_plane_phy_id);
..	..	@@ -7528,26 +11985,66 @@
7528	11985
7529	11986	vop2->vps[vp_id].xmirror_en = of_property_read_bool(child, "xmirror-enable");
7530	11987
	11988	+ ret = of_clk_set_defaults(child, false);
	11989	+ if (ret) {
	11990	+ DRM_DEV_ERROR(dev, "Failed to set clock defaults %d\n", ret);
	11991	+ return ret;
	11992	+ }
	11993	+
	11994	+ mcu_timing_node = of_get_child_by_name(child, "mcu-timing");
	11995	+ if (mcu_timing_node) {
	11996	+ if (!of_property_read_u32(mcu_timing_node, "mcu-pix-total", &val))
	11997	+ vop2->vps[vp_id].mcu_timing.mcu_pix_total = val;
	11998	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pst", &val))
	11999	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pst = val;
	12000	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pend", &val))
	12001	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pend = val;
	12002	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pst", &val))
	12003	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pst = val;
	12004	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pend", &val))
	12005	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pend = val;
	12006	+ if (!of_property_read_u32(mcu_timing_node, "mcu-hold-mode", &val))
	12007	+ vop2->vps[vp_id].mcu_timing.mcu_hold_mode = val;
	12008	+ }
	12009	+ }
	12010	+
	12011	+ if (!vop2_plane_mask_check(vop2)) {
	12012	+ DRM_WARN("use default plane mask\n");
	12013	+ vop2_plane_mask_assign(vop2, vop_out_node);
	12014	+ }
	12015	+
	12016	+ for (i = 0; i < vop2->data->nr_vps; i++) {
7531	12017	DRM_DEV_INFO(dev, "vp%d assign plane mask: 0x%x, primary plane phy id: %d\n",
7532		- vp_id, vop2->vps[vp_id].plane_mask,
7533		- vop2->vps[vp_id].primary_plane_phy_id);
	12018	+ i, vop2->vps[i].plane_mask,
	12019	+ vop2->vps[i].primary_plane_phy_id);
7534	12020	}
7535	12021	}
7536	12022
	12023	+ vop2_extend_clk_init(vop2);
7537	12024	spin_lock_init(&vop2->reg_lock);
7538	12025	spin_lock_init(&vop2->irq_lock);
7539	12026	mutex_init(&vop2->vop2_lock);
	12027	+
	12028	+ if (vop2->version == VOP_VERSION_RK3528) {
	12029	+ atomic_set(&vop2->vps[1].post_buf_empty_flag, 0);
	12030	+ vop2->workqueue = create_workqueue("post_buf_empty_wq");
	12031	+ INIT_WORK(&vop2->post_buf_empty_work, post_buf_empty_work_event);
	12032	+ }
7540	12033
7541	12034	ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
7542	12035	if (ret)
7543	12036	return ret;
7544	12037
	12038	+ vop2_dsc_data_init(vop2);
	12039	+
7545	12040	registered_num_crtcs = vop2_create_crtc(vop2);
7546	12041	if (registered_num_crtcs <= 0)
7547	12042	return -ENODEV;
	12043	+
7548	12044	ret = vop2_gamma_init(vop2);
7549	12045	if (ret)
7550	12046	return ret;
	12047	+ vop2_clk_init(vop2);
7551	12048	vop2_cubic_lut_init(vop2);
7552	12049	vop2_wb_connector_init(vop2, registered_num_crtcs);
7553	12050	pm_runtime_enable(&pdev->dev);