~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,47 +1,64 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3	4	* Author:Mark Yao <mark.yao@rock-chips.com>
4		- *
5		- * This software is licensed under the terms of the GNU General Public
6		- * License version 2, as published by the Free Software Foundation, and
7		- * may be copied, distributed, and modified under those terms.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#ifndef _ROCKCHIP_DRM_VOP_H
16	8	#define _ROCKCHIP_DRM_VOP_H
	9	+
	10	+#include <drm/drm_plane.h>
	11	+#include <drm/drm_modes.h>
	12	+
17	13	#include "rockchip_drm_drv.h"
18	14
19	15	/*
20	16	* major: IP major version, used for IP structure
21	17	* minor: big feature change under same structure
	18	+ * build: RTL current SVN number
22	19	*/
23	20	#define VOP_VERSION(major, minor) ((major) << 8 \| (minor))
24	21	#define VOP_MAJOR(version) ((version) >> 8)
25	22	#define VOP_MINOR(version) ((version) & 0xff)
26	23
27		-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
28		-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
	24	+#define VOP2_VERSION(major, minor, build) ((major) << 24 \| (minor) << 16 \| (build))
	25	+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
	26	+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
	27	+#define VOP2_BUILD(version) ((version) & 0xffff)
29	28
	29	+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
	30	+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
	31	+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
	32	+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
	33	+
	34	+/* register one connector */
30	35	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
	36	+/* register one connector */
31	37	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
32	38	#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
	39	+/* MIPI DSI DataStream(cmd) mode on rk3588 */
	40	+#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
	41	+/* register two connector */
	42	+#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
33	43
34	44	#define AFBDC_FMT_RGB565 0x0
35	45	#define AFBDC_FMT_U8U8U8U8 0x5
36	46	#define AFBDC_FMT_U8U8U8 0x4
37		-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
38		-#define VOP_FEATURE_AFBDC BIT(1)
	47	+
	48	+#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
	49	+#define VOP_FEATURE_INTERNAL_RGB BIT(1)
39	50	#define VOP_FEATURE_ALPHA_SCALE BIT(2)
40	51	#define VOP_FEATURE_HDR10 BIT(3)
41	52	#define VOP_FEATURE_NEXT_HDR BIT(4)
42	53	/* a feature to splice two windows and two vps to support resolution > 4096 */
43	54	#define VOP_FEATURE_SPLICE BIT(5)
44	55	#define VOP_FEATURE_OVERSCAN BIT(6)
	56	+#define VOP_FEATURE_VIVID_HDR BIT(7)
	57	+#define VOP_FEATURE_POST_ACM BIT(8)
	58	+#define VOP_FEATURE_POST_CSC BIT(9)
	59	+
	60	+#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
	61	+
45	62
46	63	#define WIN_FEATURE_HDR2SDR BIT(0)
47	64	#define WIN_FEATURE_SDR2HDR BIT(1)
..	..	@@ -49,6 +66,8 @@
49	66	#define WIN_FEATURE_AFBDC BIT(3)
50	67	#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
51	68	#define WIN_FEATURE_CLUSTER_SUB BIT(5)
	69	+/* Left win in splice mode */
	70	+#define WIN_FEATURE_SPLICE_LEFT BIT(6)
52	71	/* a mirror win can only get fb address
53	72	* from source win:
54	73	* Cluster1---->Cluster0
..	..	@@ -62,6 +81,23 @@
62	81
63	82
64	83	#define VOP2_SOC_VARIANT 4
	84	+
	85	+#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
	86	+
	87	+enum vop_vp_id {
	88	+ ROCKCHIP_VOP_VP0 = 0,
	89	+ ROCKCHIP_VOP_VP1,
	90	+ ROCKCHIP_VOP_VP2,
	91	+ ROCKCHIP_VOP_VP3,
	92	+};
	93	+
	94	+enum vop_win_phy_id {
	95	+ ROCKCHIP_VOP_WIN0 = 0,
	96	+ ROCKCHIP_VOP_WIN1,
	97	+ ROCKCHIP_VOP_WIN2,
	98	+ ROCKCHIP_VOP_WIN3,
	99	+ ROCKCHIP_VOP_PHY_ID_INVALID = -1,
	100	+};
65	101
66	102	enum bcsh_out_mode {
67	103	BCSH_OUT_MODE_BLACK,
..	..	@@ -84,7 +120,7 @@
84	120	/*
85	121	* the delay number of a window in different mode.
86	122	*/
87		-enum win_dly_mode {
	123	+enum vop2_win_dly_mode {
88	124	VOP2_DLY_MODE_DEFAULT, /*< default mode /
89	125	VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
90	126	VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
..	..	@@ -92,11 +128,44 @@
92	128	};
93	129
94	130	enum vop3_esmart_lb_mode {
95		- VOP3_ESMART_ONE_8K_MODE,
96		- VOP3_ESMART_TWO_4K_MODE,
97		- VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
98		- VOP3_ESMART_FOUR_2K_MODE,
	131	+ VOP3_ESMART_8K_MODE,
	132	+ VOP3_ESMART_4K_4K_MODE,
	133	+ VOP3_ESMART_4K_2K_2K_MODE,
	134	+ VOP3_ESMART_2K_2K_2K_2K_MODE,
99	135	};
	136	+
	137	+/*
	138	+ * vop2 dsc id
	139	+ */
	140	+#define ROCKCHIP_VOP2_DSC_8K 0
	141	+#define ROCKCHIP_VOP2_DSC_4K 1
	142	+
	143	+/*
	144	+ * vop2 internal power domain id,
	145	+ * should be all none zero, 0 will be
	146	+ * treat as invalid;
	147	+ */
	148	+#define VOP2_PD_CLUSTER0 BIT(0)
	149	+#define VOP2_PD_CLUSTER1 BIT(1)
	150	+#define VOP2_PD_CLUSTER2 BIT(2)
	151	+#define VOP2_PD_CLUSTER3 BIT(3)
	152	+#define VOP2_PD_DSC_8K BIT(5)
	153	+#define VOP2_PD_DSC_4K BIT(6)
	154	+#define VOP2_PD_ESMART BIT(7)
	155	+
	156	+/*
	157	+ * vop2 submem power gate,
	158	+ * should be all none zero, 0 will be
	159	+ * treat as invalid;
	160	+ */
	161	+#define VOP2_MEM_PG_VP0 BIT(0)
	162	+#define VOP2_MEM_PG_VP1 BIT(1)
	163	+#define VOP2_MEM_PG_VP2 BIT(2)
	164	+#define VOP2_MEM_PG_VP3 BIT(3)
	165	+#define VOP2_MEM_PG_DB0 BIT(4)
	166	+#define VOP2_MEM_PG_DB1 BIT(5)
	167	+#define VOP2_MEM_PG_DB2 BIT(6)
	168	+#define VOP2_MEM_PG_WB BIT(7)
100	169
101	170	#define DSP_BG_SWAP 0x1
102	171	#define DSP_RB_SWAP 0x2
..	..	@@ -135,6 +204,13 @@
135	204	VOP_FMT_YUV420SP = 4,
136	205	VOP_FMT_YUV422SP,
137	206	VOP_FMT_YUV444SP,
	207	+};
	208	+
	209	+enum vop_dsc_interface_mode {
	210	+ VOP_DSC_IF_DISABLE = 0,
	211	+ VOP_DSC_IF_HDMI = 1,
	212	+ VOP_DSC_IF_MIPI_DS_MODE = 2,
	213	+ VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
138	214	};
139	215
140	216	struct vop_reg_data {
..	..	@@ -187,6 +263,7 @@
187	263	struct vop_reg post_scl_factor;
188	264	struct vop_reg post_scl_ctrl;
189	265	struct vop_reg dsp_interlace;
	266	+ struct vop_reg dsp_interlace_pol;
190	267	struct vop_reg global_regdone_en;
191	268	struct vop_reg auto_gate_en;
192	269	struct vop_reg post_lb_mode;
..	..	@@ -232,6 +309,11 @@
232	309	struct vop_reg sw_uv_offset_en;
233	310	struct vop_reg dsp_out_yuv;
234	311	struct vop_reg dsp_data_swap;
	312	+ struct vop_reg dsp_bg_swap;
	313	+ struct vop_reg dsp_rb_swap;
	314	+ struct vop_reg dsp_rg_swap;
	315	+ struct vop_reg dsp_delta_swap;
	316	+ struct vop_reg dsp_dummy_swap;
235	317	struct vop_reg yuv_clip;
236	318	struct vop_reg dsp_ccir656_avg;
237	319	struct vop_reg dsp_black;
..	..	@@ -439,6 +521,104 @@
439	521	const uint32_t *sdr2hdr_st2084oetf_xn;
440	522	};
441	523
	524	+#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH 257
	525	+#define RK_HDRVIVID_GAMMA_CURVE_LENGTH 81
	526	+#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH 9
	527	+#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH 69
	528	+#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH 6
	529	+#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH 6
	530	+#define RK_SDR2HDR_SMGAIN_LENGTH 64
	531	+#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH 264
	532	+
	533	+struct hdrvivid_regs {
	534	+ uint32_t sdr2hdr_ctrl;
	535	+ uint32_t sdr2hdr_coe0;
	536	+ uint32_t sdr2hdr_coe1;
	537	+ uint32_t sdr2hdr_csc_coe00_01;
	538	+ uint32_t sdr2hdr_csc_coe02_10;
	539	+ uint32_t sdr2hdr_csc_coe11_12;
	540	+ uint32_t sdr2hdr_csc_coe20_21;
	541	+ uint32_t sdr2hdr_csc_coe22;
	542	+ uint32_t hdrvivid_ctrl;
	543	+ uint32_t hdr_pq_gamma;
	544	+ uint32_t hlg_rfix_scalefac;
	545	+ uint32_t hlg_maxluma;
	546	+ uint32_t hlg_r_tm_lin2non;
	547	+ uint32_t hdr_csc_coe00_01;
	548	+ uint32_t hdr_csc_coe02_10;
	549	+ uint32_t hdr_csc_coe11_12;
	550	+ uint32_t hdr_csc_coe20_21;
	551	+ uint32_t hdr_csc_coe22;
	552	+ uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
	553	+ uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
	554	+ uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
	555	+ uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
	556	+ uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
	557	+ uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
	558	+ uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
	559	+ uint32_t hdr_mode;
	560	+ uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
	561	+};
	562	+
	563	+struct hdr_extend {
	564	+ uint32_t hdr_type;
	565	+ uint32_t length;
	566	+ union {
	567	+ struct hdrvivid_regs hdrvivid_data;
	568	+ };
	569	+};
	570	+
	571	+enum _vop_hdrvivid_mode {
	572	+ PQHDR2HDR_WITH_DYNAMIC = 0,
	573	+ PQHDR2SDR_WITH_DYNAMIC,
	574	+ HLG2PQHDR_WITH_DYNAMIC,
	575	+ HLG2SDR_WITH_DYNAMIC,
	576	+ HLG2PQHDR_WITHOUT_DYNAMIC,
	577	+ HLG2SDR_WITHOUT_DYNAMIC,
	578	+ HDR_BYPASS,
	579	+ HDR102SDR,
	580	+ SDR2HDR10,
	581	+ SDR2HLG,
	582	+ SDR2HDR10_USERSPACE = 100,
	583	+ SDR2HLG_USERSPACE = 101,
	584	+};
	585	+
	586	+enum vop_hdr_format {
	587	+ HDR_NONE = 0,
	588	+ HDR_HDR10 = 1,
	589	+ HDR_HLGSTATIC = 2,
	590	+ RESERVED3 = 3, /* reserved for more future static hdr format */
	591	+ RESERVED4 = 4, /* reserved for more future static hdr format */
	592	+ HDR_HDRVIVID = 5,
	593	+ RESERVED6 = 6, /* reserved for hdr vivid */
	594	+ RESERVED7 = 7, /* reserved for hdr vivid */
	595	+ HDR_HDR10PLUS = 8,
	596	+ RESERVED9 = 9, /* reserved for hdr hdr10+ */
	597	+ RESERVED10 = 10, /* reserved for hdr hdr10+ */
	598	+ HDR_NEXT = 11,
	599	+ RESERVED12 = 12, /* reserved for other dynamic hdr format */
	600	+ RESERVED13 = 13, /* reserved for other dynamic hdr format */
	601	+ HDR_FORMAT_MAX,
	602	+};
	603	+
	604	+struct post_csc_coef {
	605	+ s32 csc_coef00;
	606	+ s32 csc_coef01;
	607	+ s32 csc_coef02;
	608	+ s32 csc_coef10;
	609	+ s32 csc_coef11;
	610	+ s32 csc_coef12;
	611	+ s32 csc_coef20;
	612	+ s32 csc_coef21;
	613	+ s32 csc_coef22;
	614	+
	615	+ s32 csc_dc0;
	616	+ s32 csc_dc1;
	617	+ s32 csc_dc2;
	618	+
	619	+ u32 range_type;
	620	+};
	621	+
442	622	enum {
443	623	VOP_CSC_Y2R_BT601,
444	624	VOP_CSC_Y2R_BT709,
..	..	@@ -480,6 +660,7 @@
480	660	struct vop_reg gate;
481	661	struct vop_reg enable;
482	662	struct vop_reg format;
	663	+ struct vop_reg interlace_read;
483	664	struct vop_reg fmt_10;
484	665	struct vop_reg fmt_yuyv;
485	666	struct vop_reg csc_mode;
..	..	@@ -505,10 +686,23 @@
505	686	struct vop_reg color_key_en;
506	687	};
507	688
	689	+struct vop_win_data {
	690	+ uint32_t base;
	691	+ enum drm_plane_type type;
	692	+ const struct vop_win_phy *phy;
	693	+ const struct vop_win_phy **area;
	694	+ const uint64_t *format_modifiers;
	695	+ const struct vop_csc *csc;
	696	+ unsigned int area_size;
	697	+ u64 feature;
	698	+};
	699	+
508	700	struct vop2_cluster_regs {
509	701	struct vop_reg enable;
510	702	struct vop_reg afbc_enable;
511	703	struct vop_reg lb_mode;
	704	+ struct vop_reg scl_lb_mode;
	705	+ struct vop_reg frm_reset_en;
512	706
513	707	struct vop_reg src_color_ctrl;
514	708	struct vop_reg dst_color_ctrl;
..	..	@@ -597,7 +791,9 @@
597	791	struct vop_reg pre_scan_htiming;
598	792	struct vop_reg htotal_pw;
599	793	struct vop_reg hact_st_end;
600		- struct vop_reg vtotal_pw;
	794	+ struct vop_reg dsp_vtotal;
	795	+ struct vop_reg sw_dsp_vtotal_imd;
	796	+ struct vop_reg dsp_vs_end;
601	797	struct vop_reg vact_st_end;
602	798	struct vop_reg vact_st_end_f1;
603	799	struct vop_reg vs_st_end_f1;
..	..	@@ -615,8 +811,8 @@
615	811
616	812	struct vop_reg core_dclk_div;
617	813	struct vop_reg p2i_en;
618		- struct vop_reg mipi_dual_en;
619		- struct vop_reg mipi_dual_channel_swap;
	814	+ struct vop_reg dual_channel_en;
	815	+ struct vop_reg dual_channel_swap;
620	816	struct vop_reg dsp_lut_en;
621	817
622	818	struct vop_reg dclk_div2;
..	..	@@ -626,6 +822,13 @@
626	822	struct vop_reg hdr_lut_update_en;
627	823	struct vop_reg hdr_lut_mode;
628	824	struct vop_reg hdr_lut_mst;
	825	+ struct vop_reg hdr_lut_fetch_done;
	826	+ struct vop_reg hdr_vivid_en;
	827	+ struct vop_reg hdr_vivid_bypass_en;
	828	+ struct vop_reg hdr_vivid_path_mode;
	829	+ struct vop_reg hdr_vivid_dstgamut;
	830	+ struct vop_reg sdr2hdr_en;
	831	+ struct vop_reg sdr2hdr_dstmode;
629	832	struct vop_reg sdr2hdr_eotf_en;
630	833	struct vop_reg sdr2hdr_r2r_en;
631	834	struct vop_reg sdr2hdr_r2r_mode;
..	..	@@ -672,11 +875,108 @@
672	875	struct vop_reg cubic_lut_update_en;
673	876	struct vop_reg cubic_lut_mst;
674	877
	878	+ /* cru */
	879	+ struct vop_reg dclk_core_div;
	880	+ struct vop_reg dclk_out_div;
	881	+ struct vop_reg dclk_src_sel;
	882	+
	883	+ struct vop_reg splice_en;
	884	+
675	885	struct vop_reg edpi_wms_hold_en;
676	886	struct vop_reg edpi_te_en;
677	887	struct vop_reg edpi_wms_fs;
678	888	struct vop_reg gamma_update_en;
679	889	struct vop_reg lut_dma_rid;
	890	+
	891	+ /* MCU output */
	892	+ struct vop_reg mcu_pix_total;
	893	+ struct vop_reg mcu_cs_pst;
	894	+ struct vop_reg mcu_cs_pend;
	895	+ struct vop_reg mcu_rw_pst;
	896	+ struct vop_reg mcu_rw_pend;
	897	+ struct vop_reg mcu_clk_sel;
	898	+ struct vop_reg mcu_hold_mode;
	899	+ struct vop_reg mcu_frame_st;
	900	+ struct vop_reg mcu_rs;
	901	+ struct vop_reg mcu_bypass;
	902	+ struct vop_reg mcu_type;
	903	+ struct vop_reg mcu_rw_bypass_port;
	904	+
	905	+ /* for DCF */
	906	+ struct vop_reg line_flag_or_en;
	907	+ struct vop_reg dsp_hold_or_en;
	908	+ struct vop_reg almost_full_or_en;
	909	+
	910	+ /* CSC */
	911	+ struct vop_reg acm_bypass_en;
	912	+ struct vop_reg csc_en;
	913	+ struct vop_reg acm_r2y_en;
	914	+ struct vop_reg csc_mode;
	915	+ struct vop_reg acm_r2y_mode;
	916	+ struct vop_reg csc_coe00;
	917	+ struct vop_reg csc_coe01;
	918	+ struct vop_reg csc_coe02;
	919	+ struct vop_reg csc_coe10;
	920	+ struct vop_reg csc_coe11;
	921	+ struct vop_reg csc_coe12;
	922	+ struct vop_reg csc_coe20;
	923	+ struct vop_reg csc_coe21;
	924	+ struct vop_reg csc_coe22;
	925	+ struct vop_reg csc_offset0;
	926	+ struct vop_reg csc_offset1;
	927	+ struct vop_reg csc_offset2;
	928	+
	929	+ /* color bar */
	930	+ struct vop_reg color_bar_en;
	931	+ struct vop_reg color_bar_mode;
	932	+};
	933	+
	934	+struct vop2_power_domain_regs {
	935	+ struct vop_reg pd;
	936	+ struct vop_reg status;
	937	+ struct vop_reg bisr_en_status;
	938	+ struct vop_reg pmu_status;
	939	+};
	940	+
	941	+struct vop2_dsc_regs {
	942	+ /* DSC SYS CTRL */
	943	+ struct vop_reg dsc_port_sel;
	944	+ struct vop_reg dsc_man_mode;
	945	+ struct vop_reg dsc_interface_mode;
	946	+ struct vop_reg dsc_pixel_num;
	947	+ struct vop_reg dsc_pxl_clk_div;
	948	+ struct vop_reg dsc_cds_clk_div;
	949	+ struct vop_reg dsc_txp_clk_div;
	950	+ struct vop_reg dsc_init_dly_mode;
	951	+ struct vop_reg dsc_scan_en;
	952	+ struct vop_reg dsc_halt_en;
	953	+ struct vop_reg rst_deassert;
	954	+ struct vop_reg dsc_flush;
	955	+ struct vop_reg dsc_cfg_done;
	956	+ struct vop_reg dsc_init_dly_num;
	957	+ struct vop_reg scan_timing_para_imd_en;
	958	+ struct vop_reg dsc_htotal_pw;
	959	+ struct vop_reg dsc_hact_st_end;
	960	+ struct vop_reg dsc_vtotal;
	961	+ struct vop_reg dsc_vs_end;
	962	+ struct vop_reg dsc_vact_st_end;
	963	+ struct vop_reg dsc_error_status;
	964	+
	965	+ /* DSC encoder */
	966	+ struct vop_reg dsc_pps0_3;
	967	+ struct vop_reg dsc_en;
	968	+ struct vop_reg dsc_rbit;
	969	+ struct vop_reg dsc_rbyt;
	970	+ struct vop_reg dsc_flal;
	971	+ struct vop_reg dsc_mer;
	972	+ struct vop_reg dsc_epb;
	973	+ struct vop_reg dsc_epl;
	974	+ struct vop_reg dsc_nslc;
	975	+ struct vop_reg dsc_sbo;
	976	+ struct vop_reg dsc_ifep;
	977	+ struct vop_reg dsc_pps_upd;
	978	+ struct vop_reg dsc_status;
	979	+ struct vop_reg dsc_ecw;
680	980	};
681	981
682	982	struct vop2_wb_regs {
..	..	@@ -695,23 +995,42 @@
695	995	struct vop_reg axi_uv_id;
696	996	};
697	997
698		-struct vop_win_data {
699		- uint32_t base;
700		- enum drm_plane_type type;
701		- const struct vop_win_phy *phy;
702		- const struct vop_win_phy **area;
703		- const struct vop_csc *csc;
704		- unsigned int area_size;
705		- u64 feature;
	998	+struct vop2_power_domain_data {
	999	+ uint8_t id;
	1000	+ uint8_t parent_id;
	1001	+ /*
	1002	+ * @module_id_mask: module id of which module this power domain is belongs to.
	1003	+ * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
	1004	+ */
	1005	+ uint32_t module_id_mask;
	1006	+
	1007	+ const struct vop2_power_domain_regs *regs;
	1008	+};
	1009	+
	1010	+/*
	1011	+ * connector interface(RGB/HDMI/eDP/DP/MIPI) data
	1012	+ */
	1013	+struct vop2_connector_if_data {
	1014	+ u32 id;
	1015	+ const char *clk_src_name;
	1016	+ const char *clk_parent_name;
	1017	+ const char *pixclk_name;
	1018	+ const char *dclk_name;
	1019	+ u32 post_proc_div_shift;
	1020	+ u32 if_div_shift;
	1021	+ u32 if_div_yuv420_shift;
	1022	+ u32 bus_div_shift;
	1023	+ u32 pixel_clk_div_shift;
706	1024	};
707	1025
708	1026	struct vop2_win_data {
709	1027	const char *name;
710	1028	uint8_t phys_id;
	1029	+ uint8_t splice_win_id;
	1030	+ uint8_t pd_id;
711	1031	uint8_t axi_id;
712	1032	uint8_t axi_yrgb_id;
713	1033	uint8_t axi_uv_id;
714		- uint8_t scale_engine_num;
715	1034	uint8_t possible_crtcs;
716	1035
717	1036	uint32_t base;
..	..	@@ -746,6 +1065,24 @@
746	1065	const uint8_t dly[VOP2_DLY_MODE_MAX];
747	1066	};
748	1067
	1068	+struct dsc_error_info {
	1069	+ u32 dsc_error_val;
	1070	+ char dsc_error_info[50];
	1071	+};
	1072	+
	1073	+struct vop2_dsc_data {
	1074	+ uint8_t id;
	1075	+ uint8_t pd_id;
	1076	+ uint8_t max_slice_num;
	1077	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	1078	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	1079	+ const char *dsc_txp_clk_src_name;
	1080	+ const char *dsc_txp_clk_name;
	1081	+ const char *dsc_pxl_clk_name;
	1082	+ const char *dsc_cds_clk_name;
	1083	+ const struct vop2_dsc_regs *regs;
	1084	+};
	1085	+
749	1086	struct vop2_wb_data {
750	1087	uint32_t nformats;
751	1088	const uint32_t *formats;
..	..	@@ -768,13 +1105,20 @@
768	1105
769	1106	struct vop2_video_port_data {
770	1107	char id;
	1108	+ uint8_t splice_vp_id;
771	1109	uint16_t lut_dma_rid;
772	1110	uint32_t feature;
773	1111	uint64_t soc_id[VOP2_SOC_VARIANT];
774	1112	uint16_t gamma_lut_len;
775	1113	uint16_t cubic_lut_len;
	1114	+ unsigned long dclk_max;
776	1115	struct vop_rect max_output;
777	1116	const u8 pre_scan_max_dly[4];
	1117	+ const u8 hdrvivid_dly[10];
	1118	+ const u8 sdr2hdr_dly;
	1119	+ const u8 layer_mix_dly;
	1120	+ const u8 hdr_mix_dly;
	1121	+ const u8 win_dly;
778	1122	const struct vop_intr *intr;
779	1123	const struct vop_hdr_table *hdr_table;
780	1124	const struct vop2_video_port_regs *regs;
..	..	@@ -818,6 +1162,14 @@
818	1162	struct vop_reg grf_dclk_inv;
819	1163	struct vop_reg grf_bt1120_clk_inv;
820	1164	struct vop_reg grf_bt656_clk_inv;
	1165	+ struct vop_reg grf_edp0_en;
	1166	+ struct vop_reg grf_edp1_en;
	1167	+ struct vop_reg grf_hdmi0_en;
	1168	+ struct vop_reg grf_hdmi1_en;
	1169	+ struct vop_reg grf_hdmi0_dsc_en;
	1170	+ struct vop_reg grf_hdmi1_dsc_en;
	1171	+ struct vop_reg grf_hdmi0_pin_pol;
	1172	+ struct vop_reg grf_hdmi1_pin_pol;
821	1173	};
822	1174
823	1175	struct vop_data {
..	..	@@ -835,6 +1187,7 @@
835	1187	struct vop_rect max_output;
836	1188	u64 feature;
837	1189	u64 soc_id;
	1190	+ u8 vop_id;
838	1191	};
839	1192
840	1193	struct vop2_ctrl {
..	..	@@ -842,6 +1195,9 @@
842	1195	struct vop_reg wb_cfg_done;
843	1196	struct vop_reg auto_gating_en;
844	1197	struct vop_reg aclk_pre_auto_gating_en;
	1198	+ struct vop_reg dma_finish_mode;
	1199	+ struct vop_reg axi_dma_finish_and_en;
	1200	+ struct vop_reg wb_dma_finish_and_en;
845	1201	struct vop_reg ovl_cfg_done_port;
846	1202	struct vop_reg ovl_port_mux_cfg_done_imd;
847	1203	struct vop_reg ovl_port_mux_cfg;
..	..	@@ -849,6 +1205,7 @@
849	1205	struct vop_reg version;
850	1206	struct vop_reg standby;
851	1207	struct vop_reg dma_stop;
	1208	+ struct vop_reg dsp_vs_t_sel;
852	1209	struct vop_reg lut_dma_en;
853	1210	struct vop_reg axi_outstanding_max_num;
854	1211	struct vop_reg axi_max_outstanding_en;
..	..	@@ -880,9 +1237,12 @@
880	1237	struct vop_reg edp_pin_pol;
881	1238	struct vop_reg mipi_dclk_pol;
882	1239	struct vop_reg mipi_pin_pol;
883		- struct vop_reg dp_dclk_pol;
884		- struct vop_reg dp_pin_pol;
	1240	+ struct vop_reg dp0_dclk_pol;
	1241	+ struct vop_reg dp0_pin_pol;
	1242	+ struct vop_reg dp1_dclk_pol;
	1243	+ struct vop_reg dp1_pin_pol;
885	1244
	1245	+ /* This will be reference by win_phy_id */
886	1246	struct vop_reg win_vp_id[16];
887	1247	struct vop_reg win_dly[16];
888	1248
..	..	@@ -903,10 +1263,25 @@
903	1263	struct vop_reg lvds_dual_mode;
904	1264	struct vop_reg lvds_dual_channel_swap;
905	1265
906		- struct vop_reg cluster0_src_color_ctrl;
907		- struct vop_reg cluster0_dst_color_ctrl;
908		- struct vop_reg cluster0_src_alpha_ctrl;
909		- struct vop_reg cluster0_dst_alpha_ctrl;
	1266	+ struct vop_reg dp_dual_en;
	1267	+ struct vop_reg edp_dual_en;
	1268	+ struct vop_reg hdmi_dual_en;
	1269	+ struct vop_reg mipi_dual_en;
	1270	+
	1271	+ struct vop_reg hdmi0_dclk_div;
	1272	+ struct vop_reg hdmi0_pixclk_div;
	1273	+ struct vop_reg edp0_dclk_div;
	1274	+ struct vop_reg edp0_pixclk_div;
	1275	+
	1276	+ struct vop_reg hdmi1_dclk_div;
	1277	+ struct vop_reg hdmi1_pixclk_div;
	1278	+ struct vop_reg edp1_dclk_div;
	1279	+ struct vop_reg edp1_pixclk_div;
	1280	+
	1281	+ struct vop_reg mipi0_pixclk_div;
	1282	+ struct vop_reg mipi1_pixclk_div;
	1283	+ struct vop_reg mipi0_ds_mode;
	1284	+ struct vop_reg mipi1_ds_mode;
910	1285
911	1286	struct vop_reg src_color_ctrl;
912	1287	struct vop_reg dst_color_ctrl;
..	..	@@ -916,6 +1291,7 @@
916	1291	struct vop_reg bt1120_yc_swap;
917	1292	struct vop_reg bt656_yc_swap;
918	1293	struct vop_reg gamma_port_sel;
	1294	+ struct vop_reg pd_off_imd;
919	1295
920	1296	struct vop_reg otp_en;
921	1297	struct vop_reg esmart_lb_mode;
..	..	@@ -930,6 +1306,12 @@
930	1306	bool enable_state;
931	1307	};
932	1308
	1309	+struct vop2_vp_plane_mask {
	1310	+ u8 primary_plane_id;
	1311	+ u8 attached_layers_nr;
	1312	+ u8 attached_layers[ROCKCHIP_MAX_LAYER];
	1313	+};
	1314	+
933	1315	/**
934	1316	* VOP2 data structe
935	1317	*
..	..	@@ -939,25 +1321,43 @@
939	1321	struct vop2_data {
940	1322	uint32_t version;
941	1323	uint32_t feature;
	1324	+ uint8_t nr_dscs;
	1325	+ uint8_t nr_dsc_ecw;
	1326	+ uint8_t nr_dsc_buffer_flow;
942	1327	uint8_t nr_vps;
943	1328	uint8_t nr_mixers;
944	1329	uint8_t nr_layers;
945	1330	uint8_t nr_axi_intr;
946	1331	uint8_t nr_gammas;
	1332	+ uint8_t nr_conns;
	1333	+ uint8_t nr_pds;
	1334	+ uint8_t nr_mem_pgs;
947	1335	uint8_t esmart_lb_mode;
	1336	+ bool delayed_pd;
948	1337	const struct vop_intr *axi_intr;
949	1338	const struct vop2_ctrl *ctrl;
	1339	+ const struct vop2_dsc_data *dsc;
	1340	+ const struct dsc_error_info *dsc_error_ecw;
	1341	+ const struct dsc_error_info *dsc_error_buffer_flow;
950	1342	const struct vop2_win_data *win;
951	1343	const struct vop2_video_port_data *vp;
	1344	+ const struct vop2_connector_if_data *conn;
952	1345	const struct vop2_wb_data *wb;
953	1346	const struct vop2_layer_data *layer;
	1347	+ const struct vop2_power_domain_data *pd;
	1348	+ const struct vop2_power_domain_data *mem_pg;
954	1349	const struct vop_csc_table *csc_table;
955	1350	const struct vop_hdr_table *hdr_table;
956		- const struct vop_grf_ctrl *grf_ctrl;
	1351	+ const struct vop_grf_ctrl *sys_grf;
	1352	+ const struct vop_grf_ctrl *grf;
	1353	+ const struct vop_grf_ctrl *vo0_grf;
	1354	+ const struct vop_grf_ctrl *vo1_grf;
957	1355	const struct vop_dump_regs *dump_regs;
958	1356	uint32_t dump_regs_size;
959	1357	struct vop_rect max_input;
960	1358	struct vop_rect max_output;
	1359	+ const struct vop2_vp_plane_mask *plane_mask;
	1360	+ uint32_t plane_mask_base;
961	1361
962	1362	unsigned int win_size;
963	1363	};
..	..	@@ -1034,6 +1434,9 @@
1034	1434	#define ROCKCHIP_OUT_MODE_P565 2
1035	1435	#define ROCKCHIP_OUT_MODE_BT656 5
1036	1436	#define ROCKCHIP_OUT_MODE_S888 8
	1437	+#define ROCKCHIP_OUT_MODE_S666 9
	1438	+#define ROCKCHIP_OUT_MODE_YUV422 9
	1439	+#define ROCKCHIP_OUT_MODE_S565 10
1037	1440	#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1038	1441	#define ROCKCHIP_OUT_MODE_YUV420 14
1039	1442	/* for use special outface */
..	..	@@ -1150,6 +1553,7 @@
1150	1553	DCLK_INVERT = 3
1151	1554	};
1152	1555
	1556	+
1153	1557	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1154	1558	#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1155	1559	#define SCL_MAX_VSKIPLINES 4
..	..	@@ -1234,7 +1638,6 @@
1234	1638	return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1235	1639	}
1236	1640
1237		-extern void vop2_standby(struct drm_crtc *crtc, bool standby);
1238	1641	extern const struct component_ops vop_component_ops;
1239	1642	extern const struct component_ops vop2_component_ops;
1240	1643	#endif /* _ROCKCHIP_DRM_VOP_H */