~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,59 +1,56 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3	4	* Author:Mark Yao <mark.yao@rock-chips.com>
4		- *
5		- * This software is licensed under the terms of the GNU General Public
6		- * License version 2, as published by the Free Software Foundation, and
7		- * may be copied, distributed, and modified under those terms.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
	7	+#include <linux/clk.h>
	8	+#include <linux/component.h>
	9	+#include <linux/debugfs.h>
	10	+#include <linux/delay.h>
	11	+#include <linux/fixp-arith.h>
	12	+#include <linux/iopoll.h>
	13	+#include <linux/kernel.h>
	14	+#include <linux/mfd/syscon.h>
	15	+#include <linux/module.h>
	16	+#include <linux/of.h>
	17	+#include <linux/of_device.h>
	18	+#include <linux/overflow.h>
	19	+#include <linux/platform_device.h>
	20	+#include <linux/pm_runtime.h>
	21	+#include <linux/regmap.h>
	22	+#include <linux/reset.h>
	23	+#include <linux/sort.h>
	24	+
15	25	#include <drm/drm.h>
16		-#include <drm/drmP.h>
17	26	#include <drm/drm_atomic.h>
	27	+#include <drm/drm_atomic_uapi.h>
18	28	#include <drm/drm_crtc.h>
19	29	#include <drm/drm_crtc_helper.h>
	30	+#include <drm/drm_debugfs.h>
20	31	#include <drm/drm_flip_work.h>
	32	+#include <drm/drm_fourcc.h>
	33	+#include <drm/drm_gem_framebuffer_helper.h>
21	34	#include <drm/drm_plane_helper.h>
	35	+#include <drm/drm_probe_helper.h>
	36	+#include <drm/drm_self_refresh_helper.h>
	37	+#include <drm/drm_vblank.h>
	38	+
22	39	#ifdef CONFIG_DRM_ANALOGIX_DP
23	40	#include <drm/bridge/analogix_dp.h>
24	41	#endif
25	42	#include <dt-bindings/soc/rockchip-system-status.h>
26	43
27		-#include <linux/debugfs.h>
28		-#include <linux/fixp-arith.h>
29		-#include <linux/iopoll.h>
30		-#include <linux/kernel.h>
31		-#include <linux/module.h>
32		-#include <linux/platform_device.h>
33		-#include <linux/clk.h>
34		-#include <linux/iopoll.h>
35		-#include <linux/of.h>
36		-#include <linux/of_device.h>
37		-#include <linux/pm_runtime.h>
38		-#include <linux/component.h>
39		-#include <linux/overflow.h>
40		-#include <linux/regmap.h>
41		-#include <linux/mfd/syscon.h>
42		-
43		-#include <linux/reset.h>
44		-#include <linux/delay.h>
45		-#include <linux/sort.h>
46	44	#include <soc/rockchip/rockchip_dmc.h>
47	45	#include <soc/rockchip/rockchip-system-status.h>
48	46	#include <uapi/linux/videodev2.h>
49		-
50		-#include "../drm_internal.h"
	47	+#include "../drm_crtc_internal.h"
51	48
52	49	#include "rockchip_drm_drv.h"
53	50	#include "rockchip_drm_gem.h"
54	51	#include "rockchip_drm_fb.h"
55		-#include "rockchip_drm_psr.h"
56	52	#include "rockchip_drm_vop.h"
	53	+#include "rockchip_rgb.h"
57	54
58	55	#define VOP_REG_SUPPORT(vop, reg) \
59	56	(reg.mask && \
..	..	@@ -151,7 +148,6 @@
151	148	} \
152	149	} while (0)
153	150
154		-#define to_vop(x) container_of(x, struct vop, crtc)
155	151	#define to_vop_win(x) container_of(x, struct vop_win, base)
156	152	#define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
157	153
..	..	@@ -172,7 +168,6 @@
172	168	struct drm_rect dest;
173	169	dma_addr_t yrgb_mst;
174	170	dma_addr_t uv_mst;
175		- void *yrgb_kvaddr;
176	171	const uint32_t *y2r_table;
177	172	const uint32_t *r2r_table;
178	173	const uint32_t *r2y_table;
..	..	@@ -181,7 +176,7 @@
181	176	bool r2r_en;
182	177	bool r2y_en;
183	178	int color_space;
184		- int color_key;
	179	+ u32 color_key;
185	180	unsigned int csc_mode;
186	181	int global_alpha;
187	182	int blend_mode;
..	..	@@ -191,21 +186,15 @@
191	186	struct vop_dump_list *planlist;
192	187	};
193	188
194		-struct rockchip_mcu_timing {
195		- int mcu_pix_total;
196		- int mcu_cs_pst;
197		- int mcu_cs_pend;
198		- int mcu_rw_pst;
199		- int mcu_rw_pend;
200		- int mcu_hold_mode;
201		-};
202		-
203	189	struct vop_win {
204	190	struct vop_win *parent;
205	191	struct drm_plane base;
206	192
207	193	int win_id;
208	194	int area_id;
	195	+ u8 plane_id; /* unique plane id */
	196	+ const char *name;
	197	+
209	198	int zpos;
210	199	uint32_t offset;
211	200	enum drm_plane_type type;
..	..	@@ -213,28 +202,45 @@
213	202	const struct vop_csc *csc;
214	203	const uint32_t *data_formats;
215	204	uint32_t nformats;
	205	+ const uint64_t *format_modifiers;
216	206	u64 feature;
217	207	struct vop *vop;
218	208	struct vop_plane_state state;
219	209
	210	+ struct drm_property *input_width_prop;
	211	+ struct drm_property *input_height_prop;
	212	+ struct drm_property *output_width_prop;
	213	+ struct drm_property *output_height_prop;
220	214	struct drm_property *color_key_prop;
	215	+ struct drm_property *scale_prop;
	216	+ struct drm_property *name_prop;
221	217	};
222	218
223	219	struct vop {
224		- struct drm_crtc crtc;
	220	+ struct rockchip_crtc rockchip_crtc;
225	221	struct device *dev;
226	222	struct drm_device *drm_dev;
227	223	struct dentry *debugfs;
228	224	struct drm_info_list *debugfs_files;
229		- struct drm_property *plane_zpos_prop;
230	225	struct drm_property *plane_feature_prop;
	226	+ struct drm_property *plane_mask_prop;
231	227	struct drm_property *feature_prop;
	228	+
232	229	bool is_iommu_enabled;
233	230	bool is_iommu_needed;
234	231	bool is_enabled;
235	232	bool support_multi_area;
236	233
	234	+ bool aclk_rate_reset;
	235	+ unsigned long aclk_rate;
	236	+
237	237	u32 version;
	238	+ u32 background;
	239	+ u32 line_flag;
	240	+ u8 id;
	241	+ u8 plane_mask;
	242	+ u64 soc_id;
	243	+ struct drm_prop_enum_list *plane_name_list;
238	244
239	245	struct drm_tv_connector_state active_tv_state;
240	246	bool pre_overlay;
..	..	@@ -308,13 +314,12 @@
308	314	{ MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
309	315	{ MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" },
310	316	{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
311		- { MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA, "RGB666_1X7X3_JEIDA" },
312	317	{ MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" },
313	318	{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
314	319	{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
315	320	{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
316		- { MEDIA_BUS_FMT_SRGB888_3X8, "SRGB888_3X8" },
317		- { MEDIA_BUS_FMT_SRGB888_DUMMY_4X8, "SRGB888_DUMMY_4X8" },
	321	+ { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
	322	+ { MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
318	323	{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
319	324	{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
320	325	{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
..	..	@@ -324,6 +329,15 @@
324	329	};
325	330
326	331	static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list)
	332	+
	333	+static inline struct vop to_vop(struct drm_crtc crtc)
	334	+{
	335	+ struct rockchip_crtc *rockchip_crtc;
	336	+
	337	+ rockchip_crtc = container_of(crtc, struct rockchip_crtc, crtc);
	338	+
	339	+ return container_of(rockchip_crtc, struct vop, rockchip_crtc);
	340	+}
327	341
328	342	static void vop_lock(struct vop *vop)
329	343	{
..	..	@@ -583,20 +597,46 @@
583	597	case DRM_FORMAT_BGR565:
584	598	return VOP_FMT_RGB565;
585	599	case DRM_FORMAT_NV12:
586		- case DRM_FORMAT_NV12_10:
	600	+ case DRM_FORMAT_NV15:
587	601	return VOP_FMT_YUV420SP;
588	602	case DRM_FORMAT_NV16:
589		- case DRM_FORMAT_NV16_10:
	603	+ case DRM_FORMAT_NV20:
590	604	return VOP_FMT_YUV422SP;
591	605	case DRM_FORMAT_NV24:
592		- case DRM_FORMAT_NV24_10:
	606	+ case DRM_FORMAT_NV30:
593	607	return VOP_FMT_YUV444SP;
	608	+ case DRM_FORMAT_YVYU:
	609	+ case DRM_FORMAT_VYUY:
594	610	case DRM_FORMAT_YUYV:
	611	+ case DRM_FORMAT_UYVY:
595	612	return VOP_FMT_YUYV;
596	613	default:
597	614	DRM_ERROR("unsupported format[%08x]\n", format);
598	615	return -EINVAL;
599	616	}
	617	+}
	618	+
	619	+static int vop_convert_afbc_format(uint32_t format)
	620	+{
	621	+ switch (format) {
	622	+ case DRM_FORMAT_XRGB8888:
	623	+ case DRM_FORMAT_ARGB8888:
	624	+ case DRM_FORMAT_XBGR8888:
	625	+ case DRM_FORMAT_ABGR8888:
	626	+ return AFBDC_FMT_U8U8U8U8;
	627	+ case DRM_FORMAT_RGB888:
	628	+ case DRM_FORMAT_BGR888:
	629	+ return AFBDC_FMT_U8U8U8;
	630	+ case DRM_FORMAT_RGB565:
	631	+ case DRM_FORMAT_BGR565:
	632	+ return AFBDC_FMT_RGB565;
	633	+ /* either of the below should not be reachable */
	634	+ default:
	635	+ DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format);
	636	+ return -EINVAL;
	637	+ }
	638	+
	639	+ return -EINVAL;
600	640	}
601	641
602	642	static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode)
..	..	@@ -618,6 +658,21 @@
618	658	bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
619	659	(output_mode == ROCKCHIP_OUT_MODE_AAAA \|\|
620	660	output_mode == ROCKCHIP_OUT_MODE_P888)))
	661	+ return true;
	662	+ else
	663	+ return false;
	664	+}
	665	+
	666	+static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
	667	+{
	668	+ /*
	669	+ * The default component order of serial formats
	670	+ * is BGR. So it is needed to enable RB swap.
	671	+ */
	672	+ if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 \|\|
	673	+ bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8 \|\|
	674	+ bus_format == MEDIA_BUS_FMT_RGB666_3X6 \|\|
	675	+ bus_format == MEDIA_BUS_FMT_RGB565_2X8_LE)
621	676	return true;
622	677	else
623	678	return false;
..	..	@@ -661,12 +716,15 @@
661	716	{
662	717	switch (format) {
663	718	case DRM_FORMAT_NV12:
664		- case DRM_FORMAT_NV12_10:
	719	+ case DRM_FORMAT_NV15:
665	720	case DRM_FORMAT_NV16:
666		- case DRM_FORMAT_NV16_10:
	721	+ case DRM_FORMAT_NV20:
667	722	case DRM_FORMAT_NV24:
668		- case DRM_FORMAT_NV24_10:
	723	+ case DRM_FORMAT_NV30:
	724	+ case DRM_FORMAT_YVYU:
	725	+ case DRM_FORMAT_VYUY:
669	726	case DRM_FORMAT_YUYV:
	727	+ case DRM_FORMAT_UYVY:
670	728	return true;
671	729	default:
672	730	return false;
..	..	@@ -676,7 +734,10 @@
676	734	static bool is_yuyv_format(uint32_t format)
677	735	{
678	736	switch (format) {
	737	+ case DRM_FORMAT_YVYU:
	738	+ case DRM_FORMAT_VYUY:
679	739	case DRM_FORMAT_YUYV:
	740	+ case DRM_FORMAT_UYVY:
680	741	return true;
681	742	default:
682	743	return false;
..	..	@@ -686,9 +747,9 @@
686	747	static bool is_yuv_10bit(uint32_t format)
687	748	{
688	749	switch (format) {
689		- case DRM_FORMAT_NV12_10:
690		- case DRM_FORMAT_NV16_10:
691		- case DRM_FORMAT_NV24_10:
	750	+ case DRM_FORMAT_NV15:
	751	+ case DRM_FORMAT_NV20:
	752	+ case DRM_FORMAT_NV30:
692	753	return true;
693	754	default:
694	755	return false;
..	..	@@ -704,6 +765,20 @@
704	765	default:
705	766	return false;
706	767	}
	768	+}
	769	+
	770	+static inline bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
	771	+{
	772	+ int i;
	773	+
	774	+ if (modifier == DRM_FORMAT_MOD_LINEAR)
	775	+ return false;
	776	+
	777	+ for (i = 0 ; i < plane->modifier_count; i++)
	778	+ if (plane->modifiers[i] == modifier)
	779	+ break;
	780	+
	781	+ return (i < plane->modifier_count) ? true : false;
707	782	}
708	783
709	784	static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
..	..	@@ -747,9 +822,9 @@
747	822	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
748	823	uint16_t cbcr_hor_scl_mode = SCALE_NONE;
749	824	uint16_t cbcr_ver_scl_mode = SCALE_NONE;
750		- int hsub = drm_format_horz_chroma_subsampling(pixel_format);
751		- int vsub = drm_format_vert_chroma_subsampling(pixel_format);
752		- const struct drm_format_info *info;
	825	+ const struct drm_format_info *info = drm_format_info(pixel_format);
	826	+ uint8_t hsub = info->hsub;
	827	+ uint8_t vsub = info->vsub;
753	828	bool is_yuv = false;
754	829	uint16_t cbcr_src_w = src_w / hsub;
755	830	uint16_t cbcr_src_h = src_h / vsub;
..	..	@@ -757,17 +832,27 @@
757	832	uint16_t lb_mode;
758	833	uint32_t val;
759	834	const struct vop_data *vop_data = vop->data;
	835	+ struct drm_display_mode *adjusted_mode = &vop->rockchip_crtc.crtc.state->adjusted_mode;
760	836	int vskiplines;
761	837
762	838	if (!win->phy->scl)
763	839	return;
	840	+
	841	+ if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2)) {
	842	+ VOP_SCL_SET(vop, win, scale_yrgb_x, ((src_w << 12) / dst_w));
	843	+ VOP_SCL_SET(vop, win, scale_yrgb_y, ((src_h << 12) / dst_h));
	844	+ if (is_yuv) {
	845	+ VOP_SCL_SET(vop, win, scale_cbcr_x, ((cbcr_src_w << 12) / dst_w));
	846	+ VOP_SCL_SET(vop, win, scale_cbcr_y, ((cbcr_src_h << 12) / dst_h));
	847	+ }
	848	+ return;
	849	+ }
764	850
765	851	if (!(vop_data->feature & VOP_FEATURE_ALPHA_SCALE)) {
766	852	if (is_alpha_support(pixel_format) &&
767	853	(src_w != dst_w \|\| src_h != dst_h))
768	854	DRM_ERROR("ERROR: unsupported ppixel alpha&scale\n");
769	855	}
770		- info = drm_format_info(pixel_format);
771	856
772	857	if (info->is_yuv)
773	858	is_yuv = true;
..	..	@@ -1193,7 +1278,7 @@
1193	1278	* UI(rgbx) -> yuv -> rgb ->hdr2sdr -> overlay -> output.
1194	1279	*/
1195	1280	if (s->hdr.hdr2sdr_en &&
1196		- vop_plane_state->eotf == SMPTE_ST2084 &&
	1281	+ vop_plane_state->eotf == HDMI_EOTF_SMPTE_ST2084 &&
1197	1282	!is_yuv_support(pstate->fb->format->format))
1198	1283	vop_plane_state->r2y_en = true;
1199	1284	if (win->feature & WIN_FEATURE_PRE_OVERLAY)
..	..	@@ -1533,6 +1618,18 @@
1533	1618	vop_enable_debug_irq(crtc);
1534	1619	}
1535	1620
	1621	+static void vop_crtc_atomic_disable_for_psr(struct drm_crtc *crtc,
	1622	+ struct drm_crtc_state *old_state)
	1623	+{
	1624	+ struct vop *vop = to_vop(crtc);
	1625	+
	1626	+ vop_disable_all_planes(vop);
	1627	+ drm_crtc_vblank_off(crtc);
	1628	+ vop->aclk_rate = clk_get_rate(vop->aclk);
	1629	+ clk_set_rate(vop->aclk, vop->aclk_rate / 3);
	1630	+ vop->aclk_rate_reset = true;
	1631	+}
	1632	+
1536	1633	static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
1537	1634	struct drm_crtc_state *old_state)
1538	1635	{
..	..	@@ -1541,6 +1638,11 @@
1541	1638	SYS_STATUS_LCDC1 : SYS_STATUS_LCDC0;
1542	1639
1543	1640	WARN_ON(vop->event);
	1641	+
	1642	+ if (crtc->state->self_refresh_active) {
	1643	+ vop_crtc_atomic_disable_for_psr(crtc, old_state);
	1644	+ goto out;
	1645	+ }
1544	1646
1545	1647	vop_lock(vop);
1546	1648	VOP_CTRL_SET(vop, reg_done_frm, 1);
..	..	@@ -1589,6 +1691,7 @@
1589	1691
1590	1692	rockchip_clear_system_status(sys_status);
1591	1693
	1694	+out:
1592	1695	if (crtc->state->event && !crtc->state->active) {
1593	1696	spin_lock_irq(&crtc->dev->event_lock);
1594	1697	drm_crtc_send_vblank_event(crtc, crtc->state->event);
..	..	@@ -1614,6 +1717,21 @@
1614	1717	drm_framebuffer_put(old_state->fb);
1615	1718	}
1616	1719
	1720	+static bool rockchip_vop_mod_supported(struct drm_plane *plane,
	1721	+ u32 format, u64 modifier)
	1722	+{
	1723	+ if (modifier == DRM_FORMAT_MOD_LINEAR)
	1724	+ return true;
	1725	+
	1726	+ if (!rockchip_afbc(plane, modifier)) {
	1727	+ DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
	1728	+
	1729	+ return false;
	1730	+ }
	1731	+
	1732	+ return vop_convert_afbc_format(format) >= 0;
	1733	+}
	1734	+
1617	1735	static int vop_plane_atomic_check(struct drm_plane *plane,
1618	1736	struct drm_plane_state *state)
1619	1737	{
..	..	@@ -1627,13 +1745,14 @@
1627	1745	int ret;
1628	1746	struct drm_rect *dest = &vop_plane_state->dest;
1629	1747	struct drm_rect *src = &vop_plane_state->src;
	1748	+ struct drm_gem_object obj, uv_obj;
	1749	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
1630	1750	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1631	1751	DRM_PLANE_HELPER_NO_SCALING;
1632	1752	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1633	1753	DRM_PLANE_HELPER_NO_SCALING;
1634	1754	unsigned long offset;
1635	1755	dma_addr_t dma_addr;
1636		- void *kvaddr;
1637	1756
1638	1757	crtc = crtc ? crtc : plane->state->crtc;
1639	1758	if (!crtc \|\| !fb) {
..	..	@@ -1645,14 +1764,8 @@
1645	1764	if (WARN_ON(!crtc_state))
1646	1765	return -EINVAL;
1647	1766
1648		- src->x1 = state->src_x;
1649		- src->y1 = state->src_y;
1650		- src->x2 = state->src_x + state->src_w;
1651		- src->y2 = state->src_y + state->src_h;
1652		- dest->x1 = state->crtc_x;
1653		- dest->y1 = state->crtc_y;
1654		- dest->x2 = state->crtc_x + state->crtc_w;
1655		- dest->y2 = state->crtc_y + state->crtc_h;
	1767	+ vop_plane_state->zpos = state->zpos;
	1768	+ vop_plane_state->blend_mode = state->pixel_blend_mode;
1656	1769
1657	1770	ret = drm_atomic_helper_check_plane_state(state, crtc_state,
1658	1771	min_scale, max_scale,
..	..	@@ -1660,8 +1773,22 @@
1660	1773	if (ret)
1661	1774	return ret;
1662	1775
1663		- if (!state->visible)
	1776	+ if (!state->visible) {
	1777	+ DRM_ERROR("%s is invisible(src: pos[%d, %d] rect[%d x %d] dst: pos[%d, %d] rect[%d x %d]\n",
	1778	+ plane->name, state->src_x >> 16, state->src_y >> 16, state->src_w >> 16,
	1779	+ state->src_h >> 16, state->crtc_x, state->crtc_y, state->crtc_w,
	1780	+ state->crtc_h);
1664	1781	return 0;
	1782	+ }
	1783	+
	1784	+ src->x1 = state->src.x1;
	1785	+ src->y1 = state->src.y1;
	1786	+ src->x2 = state->src.x2;
	1787	+ src->y2 = state->src.y2;
	1788	+ dest->x1 = state->dst.x1;
	1789	+ dest->y1 = state->dst.y1;
	1790	+ dest->x2 = state->dst.x2;
	1791	+ dest->y2 = state->dst.y2;
1665	1792
1666	1793	vop_plane_state->format = vop_convert_format(fb->format->format);
1667	1794	if (vop_plane_state->format < 0)
..	..	@@ -1676,12 +1803,13 @@
1676	1803	return -EINVAL;
1677	1804	}
1678	1805
1679		- if (state->src_w >> 16 < 4 \|\| state->src_h >> 16 < 4 \|\|
1680		- state->crtc_w < 4 \|\| state->crtc_h < 4) {
	1806	+ if (drm_rect_width(src) >> 16 < 4 \|\| drm_rect_height(src) >> 16 < 4 \|\|
	1807	+ drm_rect_width(dest) < 4 \|\| drm_rect_width(dest) < 4) {
1681	1808	DRM_ERROR("Invalid size: %dx%d->%dx%d, min size is 4x4\n",
1682		- state->src_w >> 16, state->src_h >> 16,
1683		- state->crtc_w, state->crtc_h);
1684		- return -EINVAL;
	1809	+ drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
	1810	+ drm_rect_width(dest), drm_rect_height(dest));
	1811	+ state->visible = false;
	1812	+ return 0;
1685	1813	}
1686	1814
1687	1815	if (drm_rect_width(src) >> 16 > vop_data->max_input.width \|\|
..	..	@@ -1708,26 +1836,27 @@
1708	1836	return -EINVAL;
1709	1837	}
1710	1838
1711		- offset = (src->x1 >> 16) * fb->format->bpp[0] / 8;
	1839	+ offset = (src->x1 >> 16) * fb->format->cpp[0];
1712	1840	vop_plane_state->offset = offset + fb->offsets[0];
1713	1841	if (state->rotation & DRM_MODE_REFLECT_Y)
1714	1842	offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1715	1843	else
1716	1844	offset += (src->y1 >> 16) * fb->pitches[0];
1717	1845
1718		- dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1719		- kvaddr = rockchip_fb_get_kvaddr(fb, 0);
1720		- vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1721		- vop_plane_state->yrgb_kvaddr = kvaddr + offset + fb->offsets[0];
	1846	+ obj = fb->obj[0];
	1847	+ rk_obj = to_rockchip_obj(obj);
	1848	+ vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1722	1849	if (fb->format->is_yuv) {
1723		- int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
1724		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
	1850	+ int hsub = fb->format->hsub;
	1851	+ int vsub = fb->format->vsub;
1725	1852
1726		- offset = (src->x1 >> 16) * fb->format->bpp[1] / hsub / 8;
	1853	+ offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1727	1854	offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1728	1855
1729		- dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1730		- dma_addr += offset + fb->offsets[1];
	1856	+ uv_obj = fb->obj[1];
	1857	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	1858	+
	1859	+ dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
1731	1860	vop_plane_state->uv_mst = dma_addr;
1732	1861	}
1733	1862
..	..	@@ -1743,6 +1872,9 @@
1743	1872	struct vop_plane_state *vop_plane_state =
1744	1873	to_vop_plane_state(plane->state);
1745	1874	#endif
	1875	+
	1876	+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE, "disable win%d-area%d by %s\n",
	1877	+ win->win_id, win->area_id, current->comm);
1746	1878
1747	1879	if (!old_state->crtc)
1748	1880	return;
..	..	@@ -1853,20 +1985,19 @@
1853	1985	uint32_t val;
1854	1986	bool rb_swap, global_alpha_en;
1855	1987	int is_yuv = fb->format->is_yuv;
	1988	+ struct drm_format_name_buf format_name;
1856	1989
1857	1990	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
1858	1991	bool AFBC_flag = false;
1859	1992	struct vop_dump_list *planlist;
1860	1993	unsigned long num_pages;
1861	1994	struct page **pages;
1862		- struct rockchip_drm_fb *rk_fb;
1863	1995	struct drm_gem_object *obj;
1864	1996	struct rockchip_gem_object *rk_obj;
1865	1997
1866	1998	num_pages = 0;
1867	1999	pages = NULL;
1868		- rk_fb = to_rockchip_fb(fb);
1869		- obj = rk_fb->obj[0];
	2000	+ obj = fb->obj[0];
1870	2001	rk_obj = to_rockchip_obj(obj);
1871	2002	if (rk_obj) {
1872	2003	num_pages = rk_obj->num_pages;
..	..	@@ -1914,6 +2045,8 @@
1914	2045	dsp_h = 4;
1915	2046	actual_h = dsp_h * actual_h / drm_rect_height(dest);
1916	2047	}
	2048	+ if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2))
	2049	+ dsp_h = dsp_h / 2;
1917	2050
1918	2051	act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
1919	2052
..	..	@@ -1922,12 +2055,18 @@
1922	2055
1923	2056	dsp_stx = dest->x1 + mode->crtc_htotal - mode->crtc_hsync_start;
1924	2057	dsp_sty = dest->y1 + mode->crtc_vtotal - mode->crtc_vsync_start;
	2058	+ if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2))
	2059	+ dsp_sty = dest->y1 / 2 + mode->crtc_vtotal - mode->crtc_vsync_start;
1925	2060	dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
1926	2061
1927	2062	s = to_rockchip_crtc_state(crtc->state);
1928	2063	spin_lock(&vop->reg_lock);
1929	2064
1930	2065	VOP_WIN_SET(vop, win, format, vop_plane_state->format);
	2066	+
	2067	+ VOP_WIN_SET(vop, win, interlace_read,
	2068	+ (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
	2069	+
1931	2070	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
1932	2071	VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1933	2072
..	..	@@ -1945,7 +2084,7 @@
1945	2084
1946	2085	if (win->phy->scl)
1947	2086	scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1948		- drm_rect_width(dest), drm_rect_height(dest),
	2087	+ drm_rect_width(dest), dsp_h,
1949	2088	fb->format->format);
1950	2089
1951	2090	if (VOP_WIN_SUPPORT(vop, win, color_key))
..	..	@@ -1976,7 +2115,6 @@
1976	2115	src_blend_m0 = ALPHA_PER_PIX;
1977	2116	else
1978	2117	src_blend_m0 = ALPHA_GLOBAL;
1979		-
1980	2118
1981	2119	if (vop_plane_state->blend_mode == 0 \|\| src_blend_m0 == ALPHA_GLOBAL)
1982	2120	pre_multi_alpha = ALPHA_SRC_NO_PRE_MUL;
..	..	@@ -2012,6 +2150,13 @@
2012	2150	VOP_WIN_SET(vop, win, enable, 1);
2013	2151	VOP_WIN_SET(vop, win, gate, 1);
2014	2152	spin_unlock(&vop->reg_lock);
	2153	+
	2154	+ drm_get_format_name(fb->format->format, &format_name);
	2155	+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE,
	2156	+ "update win%d-area%d [%dx%d->%dx%d@(%d, %d)] zpos:%d fmt[%s%s] addr[%pad] by %s\n",
	2157	+ win->win_id, win->area_id, actual_w, actual_h,
	2158	+ dsp_w, dsp_h, dsp_stx, dsp_sty, vop_plane_state->zpos, format_name.str,
	2159	+ fb->modifier ? "[AFBC]" : "", &vop_plane_state->yrgb_mst, current->comm);
2015	2160	/*
2016	2161	* spi interface(vop_plane_state->yrgb_kvaddr, fb->pixel_format,
2017	2162	* actual_w, actual_h)
..	..	@@ -2033,17 +2178,17 @@
2033	2178	planlist->dump_info.offset = vop_plane_state->offset;
2034	2179	planlist->dump_info.pitches = fb->pitches[0];
2035	2180	planlist->dump_info.height = actual_h;
2036		- planlist->dump_info.pixel_format = fb->format->format;
2037		- list_add_tail(&planlist->entry, &crtc->vop_dump_list_head);
	2181	+ planlist->dump_info.format = fb->format;
	2182	+ list_add_tail(&planlist->entry, &vop->rockchip_crtc.vop_dump_list_head);
2038	2183	vop_plane_state->planlist = planlist;
2039	2184	} else {
2040	2185	DRM_ERROR("can't alloc a node of planlist %p\n", planlist);
2041	2186	return;
2042	2187	}
2043		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
2044		- crtc->vop_dump_times > 0) {
2045		- vop_plane_dump(&planlist->dump_info, crtc->frame_count);
2046		- crtc->vop_dump_times--;
	2188	+ if (vop->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	2189	+ vop->rockchip_crtc.vop_dump_times > 0) {
	2190	+ rockchip_drm_dump_plane_buffer(&planlist->dump_info, vop->rockchip_crtc.frame_count);
	2191	+ vop->rockchip_crtc.vop_dump_times--;
2047	2192	}
2048	2193	#endif
2049	2194	}
..	..	@@ -2192,10 +2337,9 @@
2192	2337	if (!vop_plane_state)
2193	2338	return;
2194	2339
2195		- win->state.zpos = win->zpos;
	2340	+ __drm_atomic_helper_plane_reset(plane, &vop_plane_state->base);
	2341	+ vop_plane_state->base.zpos = win->zpos;
2196	2342	vop_plane_state->global_alpha = 0xff;
2197		- plane->state = &vop_plane_state->base;
2198		- plane->state->plane = plane;
2199	2343	}
2200	2344
2201	2345	static struct drm_plane_state *
..	..	@@ -2238,11 +2382,6 @@
2238	2382	struct vop_win *win = to_vop_win(plane);
2239	2383	struct vop_plane_state *plane_state = to_vop_plane_state(state);
2240	2384
2241		- if (property == win->vop->plane_zpos_prop) {
2242		- plane_state->zpos = val;
2243		- return 0;
2244		- }
2245		-
2246	2385	if (property == private->eotf_prop) {
2247	2386	plane_state->eotf = val;
2248	2387	return 0;
..	..	@@ -2250,16 +2389,6 @@
2250	2389
2251	2390	if (property == private->color_space_prop) {
2252	2391	plane_state->color_space = val;
2253		- return 0;
2254		- }
2255		-
2256		- if (property == private->global_alpha_prop) {
2257		- plane_state->global_alpha = val;
2258		- return 0;
2259		- }
2260		-
2261		- if (property == private->blend_mode_prop) {
2262		- plane_state->blend_mode = val;
2263	2392	return 0;
2264	2393	}
2265	2394
..	..	@@ -2288,11 +2417,6 @@
2288	2417	struct vop_win *win = to_vop_win(plane);
2289	2418	struct rockchip_drm_private *private = plane->dev->dev_private;
2290	2419
2291		- if (property == win->vop->plane_zpos_prop) {
2292		- *val = plane_state->zpos;
2293		- return 0;
2294		- }
2295		-
2296	2420	if (property == private->eotf_prop) {
2297	2421	*val = plane_state->eotf;
2298	2422	return 0;
..	..	@@ -2300,16 +2424,6 @@
2300	2424
2301	2425	if (property == private->color_space_prop) {
2302	2426	*val = plane_state->color_space;
2303		- return 0;
2304		- }
2305		-
2306		- if (property == private->global_alpha_prop) {
2307		- *val = plane_state->global_alpha;
2308		- return 0;
2309		- }
2310		-
2311		- if (property == private->blend_mode_prop) {
2312		- *val = plane_state->blend_mode;
2313	2427	return 0;
2314	2428	}
2315	2429
..	..	@@ -2350,6 +2464,7 @@
2350	2464	.atomic_destroy_state = vop_atomic_plane_destroy_state,
2351	2465	.atomic_set_property = vop_atomic_plane_set_property,
2352	2466	.atomic_get_property = vop_atomic_plane_get_property,
	2467	+ .format_mod_supported = rockchip_vop_mod_supported,
2353	2468	};
2354	2469
2355	2470	static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
..	..	@@ -2406,13 +2521,13 @@
2406	2521	if (e && e->base.file_priv == file_priv) {
2407	2522	vop->event = NULL;
2408	2523
2409		- //e->base.destroy(&e->base);//todo
	2524	+ /* e->base.destroy(&e->base);//todo */
2410	2525	file_priv->event_space += sizeof(e->event);
2411	2526	}
2412	2527	spin_unlock_irqrestore(&drm->event_lock, flags);
2413	2528	}
2414	2529
2415		-static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
	2530	+static int vop_crtc_loader_protect(struct drm_crtc crtc, bool on, void data)
2416	2531	{
2417	2532	struct rockchip_drm_private *private = crtc->dev->dev_private;
2418	2533	struct vop *vop = to_vop(crtc);
..	..	@@ -2471,6 +2586,9 @@
2471	2586	struct drm_framebuffer *fb = state->fb;
2472	2587	struct drm_format_name_buf format_name;
2473	2588	int i;
	2589	+ struct drm_gem_object *obj;
	2590	+ struct rockchip_gem_object *rk_obj;
	2591	+ dma_addr_t fb_addr;
2474	2592	u64 afbdc_format =
2475	2593	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16);
2476	2594
..	..	@@ -2498,14 +2616,30 @@
2498	2616	DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
2499	2617	drm_rect_width(dest), drm_rect_height(dest));
2500	2618
2501		- for (i = 0; i < drm_format_num_planes(fb->format->format); i++) {
2502		- dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
	2619	+ for (i = 0; i < fb->format->num_planes; i++) {
	2620	+ obj = fb->obj[0];
	2621	+ rk_obj = to_rockchip_obj(obj);
	2622	+ fb_addr = rk_obj->dma_addr + fb->offsets[0];
2503	2623
2504	2624	DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
2505	2625	i, &fb_addr, fb->pitches[i], fb->offsets[i]);
2506	2626	}
2507	2627
2508	2628	return 0;
	2629	+}
	2630	+
	2631	+static void vop_dump_connector_on_crtc(struct drm_crtc crtc, struct seq_file s)
	2632	+{
	2633	+ struct drm_connector_list_iter conn_iter;
	2634	+ struct drm_connector *connector;
	2635	+
	2636	+ drm_connector_list_iter_begin(crtc->dev, &conn_iter);
	2637	+ drm_for_each_connector_iter(connector, &conn_iter) {
	2638	+ if (crtc->state->connector_mask & drm_connector_mask(connector))
	2639	+ DEBUG_PRINT(" Connector: %s\n", connector->name);
	2640	+
	2641	+ }
	2642	+ drm_connector_list_iter_end(&conn_iter);
2509	2643	}
2510	2644
2511	2645	static int vop_crtc_debugfs_dump(struct drm_crtc crtc, struct seq_file s)
..	..	@@ -2524,8 +2658,7 @@
2524	2658	if (!crtc_state->active)
2525	2659	return 0;
2526	2660
2527		- DEBUG_PRINT(" Connector: %s\n",
2528		- drm_get_connector_name(state->output_type));
	2661	+ vop_dump_connector_on_crtc(crtc, s);
2529	2662	DEBUG_PRINT("\tbus_format[%x]: %s\n", state->bus_format,
2530	2663	drm_get_bus_format_name(state->bus_format));
2531	2664	DEBUG_PRINT("\toverlay_mode[%d] output_mode[%x]",
..	..	@@ -2619,24 +2752,15 @@
2619	2752	goto remove;
2620	2753	}
2621	2754	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
2622		- drm_debugfs_vop_add(crtc, vop->debugfs);
	2755	+ rockchip_drm_add_dump_buffer(crtc, vop->debugfs);
2623	2756	#endif
2624	2757	for (i = 0; i < ARRAY_SIZE(vop_debugfs_files); i++)
2625	2758	vop->debugfs_files[i].data = vop;
2626	2759
2627		- ret = drm_debugfs_create_files(vop->debugfs_files,
2628		- ARRAY_SIZE(vop_debugfs_files),
2629		- vop->debugfs,
2630		- minor);
2631		- if (ret) {
2632		- dev_err(vop->dev, "could not install rockchip_debugfs_list\n");
2633		- goto free;
2634		- }
	2760	+ drm_debugfs_create_files(vop->debugfs_files, ARRAY_SIZE(vop_debugfs_files),
	2761	+ vop->debugfs, minor);
2635	2762
2636	2763	return 0;
2637		-free:
2638		- kfree(vop->debugfs_files);
2639		- vop->debugfs_files = NULL;
2640	2764	remove:
2641	2765	debugfs_remove(vop->debugfs);
2642	2766	vop->debugfs = NULL;
..	..	@@ -2644,10 +2768,10 @@
2644	2768	}
2645	2769
2646	2770	static enum drm_mode_status
2647		-vop_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode,
2648		- int output_type)
	2771	+vop_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode)
2649	2772	{
2650	2773	struct vop *vop = to_vop(crtc);
	2774	+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2651	2775	const struct vop_data *vop_data = vop->data;
2652	2776	int request_clock = mode->clock;
2653	2777	int clock;
..	..	@@ -2660,15 +2784,20 @@
2660	2784	VOP_MINOR(vop->version) <= 2)
2661	2785	return MODE_BAD;
2662	2786
2663		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	2787	+ /*
	2788	+ * Dclk need to be double if BT656 interface and vop version >= 2.12.
	2789	+ */
	2790	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
	2791	+ (VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
	2792	+ s->output_if & VOP_OUTPUT_IF_BT656))
2664	2793	request_clock *= 2;
2665	2794	clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
2666	2795
2667	2796	/*
2668	2797	* Hdmi or DisplayPort request a Accurate clock.
2669	2798	*/
2670		- if (output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
2671		- output_type == DRM_MODE_CONNECTOR_DisplayPort)
	2799	+ if (s->output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
	2800	+ s->output_type == DRM_MODE_CONNECTOR_DisplayPort)
2672	2801	if (clock != request_clock)
2673	2802	return MODE_CLOCK_RANGE;
2674	2803
..	..	@@ -2698,7 +2827,7 @@
2698	2827	struct drm_framebuffer *fb = pstate->fb;
2699	2828	struct drm_rect *dest = &vop_plane_state->dest;
2700	2829	struct drm_rect *src = &vop_plane_state->src;
2701		- int bpp = fb->format->bpp[0];
	2830	+ int bpp = fb->format->cpp[0] << 3;
2702	2831	int src_width = drm_rect_width(src) >> 16;
2703	2832	int src_height = drm_rect_height(src) >> 16;
2704	2833	int dest_width = drm_rect_width(dest);
..	..	@@ -2747,8 +2876,7 @@
2747	2876
2748	2877	static size_t vop_crtc_bandwidth(struct drm_crtc *crtc,
2749	2878	struct drm_crtc_state *crtc_state,
2750		- size_t *frame_bw_mbyte,
2751		- unsigned int *plane_num_total)
	2879	+ struct dmcfreq_vop_info *vop_bw_info)
2752	2880	{
2753	2881	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2754	2882	u16 htotal = adjusted_mode->crtc_htotal;
..	..	@@ -2758,64 +2886,77 @@
2758	2886	struct drm_plane_state *pstate;
2759	2887	struct vop_bandwidth *pbandwidth;
2760	2888	struct drm_plane *plane;
2761		- u64 bandwidth;
	2889	+ u64 line_bw_mbyte = 0;
2762	2890	int cnt = 0, plane_num = 0;
2763	2891	struct drm_atomic_state *state = crtc_state->state;
2764	2892	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
2765	2893	struct vop_dump_list pos, n;
	2894	+ struct vop *vop = to_vop(crtc);
2766	2895	#endif
2767	2896
2768	2897	if (!htotal \|\| !vdisplay)
2769	2898	return 0;
2770	2899
2771	2900	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
2772		- if (!crtc->vop_dump_list_init_flag) {
2773		- INIT_LIST_HEAD(&crtc->vop_dump_list_head);
2774		- crtc->vop_dump_list_init_flag = true;
	2901	+ if (!vop->rockchip_crtc.vop_dump_list_init_flag) {
	2902	+ INIT_LIST_HEAD(&vop->rockchip_crtc.vop_dump_list_head);
	2903	+ vop->rockchip_crtc.vop_dump_list_init_flag = true;
2775	2904	}
2776		- list_for_each_entry_safe(pos, n, &crtc->vop_dump_list_head, entry) {
	2905	+ list_for_each_entry_safe(pos, n, &vop->rockchip_crtc.vop_dump_list_head, entry) {
2777	2906	list_del(&pos->entry);
2778	2907	}
2779		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
2780		- crtc->vop_dump_times > 0) {
2781		- crtc->frame_count++;
	2908	+ if (vop->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	2909	+ vop->rockchip_crtc.vop_dump_times > 0) {
	2910	+ vop->rockchip_crtc.frame_count++;
2782	2911	}
2783	2912	#endif
2784	2913
2785	2914	drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
2786	2915	plane_num++;
2787	2916
2788		- if (plane_num_total)
2789		- *plane_num_total += plane_num;
	2917	+ vop_bw_info->plane_num += plane_num;
2790	2918	pbandwidth = kmalloc_array(plane_num, sizeof(*pbandwidth),
2791	2919	GFP_KERNEL);
2792	2920	if (!pbandwidth)
2793	2921	return -ENOMEM;
2794	2922
2795	2923	drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
	2924	+ int act_w, act_h, cpp, afbc_fac;
	2925	+
2796	2926	pstate = drm_atomic_get_existing_plane_state(state, plane);
2797	2927	if (pstate->crtc != crtc \|\| !pstate->fb)
2798	2928	continue;
2799	2929
	2930	+ /* This is an empirical value, if it's afbc format, the frame buffer size div 2 */
	2931	+ afbc_fac = rockchip_afbc(plane, pstate->fb->modifier) ? 2 : 1;
	2932	+
2800	2933	vop_plane_state = to_vop_plane_state(pstate);
2801	2934	pbandwidth[cnt].y1 = vop_plane_state->dest.y1;
2802	2935	pbandwidth[cnt].y2 = vop_plane_state->dest.y2;
2803		- pbandwidth[cnt++].bandwidth = vop_plane_line_bandwidth(pstate);
	2936	+ pbandwidth[cnt++].bandwidth = vop_plane_line_bandwidth(pstate) / afbc_fac;
	2937	+
	2938	+ act_w = drm_rect_width(&pstate->src) >> 16;
	2939	+ act_h = drm_rect_height(&pstate->src) >> 16;
	2940	+ cpp = pstate->fb->format->cpp[0];
	2941	+
	2942	+ vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * cpp * drm_mode_vrefresh(adjusted_mode) / 1000;
	2943	+
2804	2944	}
2805	2945
2806	2946	sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop_bandwidth_cmp, NULL);
2807	2947
2808		- bandwidth = vop_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
	2948	+ vop_bw_info->line_bw_mbyte = vop_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
2809	2949	kfree(pbandwidth);
2810	2950	/*
2811		- * bandwidth(MB/s)
	2951	+ * line_bandwidth(MB/s)
2812	2952	* = line_bandwidth / line_time
2813	2953	* = line_bandwidth(Byte) * clock(KHZ) / 1000 / htotal
2814	2954	*/
2815		- bandwidth *= clock;
2816		- do_div(bandwidth, htotal * 1000);
	2955	+ line_bw_mbyte *= clock;
	2956	+ do_div(line_bw_mbyte, htotal * 1000);
	2957	+ vop_bw_info->line_bw_mbyte = line_bw_mbyte;
2817	2958
2818		- return bandwidth;
	2959	+ return vop_bw_info->line_bw_mbyte;
2819	2960	}
2820	2961
2821	2962	static void vop_crtc_close(struct drm_crtc *crtc)
..	..	@@ -2898,16 +3039,50 @@
2898	3039	vop_set_out_mode(vop, state->output_mode);
2899	3040	}
2900	3041
	3042	+static int vop_crtc_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
	3043	+{
	3044	+ struct vop *vop = to_vop(crtc);
	3045	+ unsigned long jiffies_left;
	3046	+ int ret = 0;
	3047	+
	3048	+ if (!vop->is_enabled)
	3049	+ return -ENODEV;
	3050	+
	3051	+ mutex_lock(&vop->vop_lock);
	3052	+
	3053	+ if (vop_line_flag_irq_is_enabled(vop)) {
	3054	+ ret = -EBUSY;
	3055	+ goto out;
	3056	+ }
	3057	+
	3058	+ reinit_completion(&vop->line_flag_completion);
	3059	+ vop_line_flag_irq_enable(vop);
	3060	+
	3061	+ jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
	3062	+ msecs_to_jiffies(mstimeout));
	3063	+ vop_line_flag_irq_disable(vop);
	3064	+
	3065	+ if (jiffies_left == 0) {
	3066	+ DRM_DEV_ERROR(vop->dev, "timeout waiting for lineflag IRQ\n");
	3067	+ ret = -ETIMEDOUT;
	3068	+ goto out;
	3069	+ }
	3070	+
	3071	+out:
	3072	+ mutex_unlock(&vop->vop_lock);
	3073	+ return ret;
	3074	+}
	3075	+
2901	3076	static const struct rockchip_crtc_funcs private_crtc_funcs = {
2902	3077	.loader_protect = vop_crtc_loader_protect,
2903	3078	.cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
2904	3079	.debugfs_init = vop_crtc_debugfs_init,
2905	3080	.debugfs_dump = vop_crtc_debugfs_dump,
2906	3081	.regs_dump = vop_crtc_regs_dump,
2907		- .mode_valid = vop_crtc_mode_valid,
2908	3082	.bandwidth = vop_crtc_bandwidth,
2909	3083	.crtc_close = vop_crtc_close,
2910	3084	.crtc_send_mcu_cmd = vop_crtc_send_mcu_cmd,
	3085	+ .wait_vact_end = vop_crtc_wait_vact_end,
2911	3086	};
2912	3087
2913	3088	static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
..	..	@@ -2916,6 +3091,8 @@
2916	3091	{
2917	3092	struct vop *vop = to_vop(crtc);
2918	3093	const struct vop_data *vop_data = vop->data;
	3094	+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
	3095	+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(new_crtc_state);
2919	3096
2920	3097	if (mode->hdisplay > vop_data->max_output.width)
2921	3098	return false;
..	..	@@ -2923,8 +3100,17 @@
2923	3100	drm_mode_set_crtcinfo(adj_mode,
2924	3101	CRTC_INTERLACE_HALVE_V \| CRTC_STEREO_DOUBLE);
2925	3102
2926		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	3103	+ /*
	3104	+ * Dclk need to be double if BT656 interface and vop version >= 2.12.
	3105	+ */
	3106	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
	3107	+ (VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
	3108	+ s->output_if & VOP_OUTPUT_IF_BT656))
2927	3109	adj_mode->crtc_clock *= 2;
	3110	+
	3111	+ if (vop->mcu_timing.mcu_pix_total)
	3112	+ adj_mode->crtc_clock = rockchip_drm_get_cycles_per_pixel(s->bus_format)
	3113	+ (vop->mcu_timing.mcu_pix_total + 1);
2928	3114
2929	3115	adj_mode->crtc_clock =
2930	3116	DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000),
..	..	@@ -2949,13 +3135,14 @@
2949	3135
2950	3136	switch (s->bus_format) {
2951	3137	case MEDIA_BUS_FMT_RGB565_1X16:
	3138	+ case MEDIA_BUS_FMT_RGB565_2X8_LE:
2952	3139	VOP_CTRL_SET(vop, dither_down_en, 1);
2953	3140	VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB565);
2954	3141	break;
2955	3142	case MEDIA_BUS_FMT_RGB666_1X18:
2956	3143	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
2957	3144	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
2958		- case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
	3145	+ case MEDIA_BUS_FMT_RGB666_3X6:
2959	3146	VOP_CTRL_SET(vop, dither_down_en, 1);
2960	3147	VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB666);
2961	3148	break;
..	..	@@ -2969,8 +3156,8 @@
2969	3156	VOP_CTRL_SET(vop, dither_down_en, 0);
2970	3157	VOP_CTRL_SET(vop, pre_dither_down_en, 0);
2971	3158	break;
2972		- case MEDIA_BUS_FMT_SRGB888_3X8:
2973		- case MEDIA_BUS_FMT_SRGB888_DUMMY_4X8:
	3159	+ case MEDIA_BUS_FMT_RGB888_3X8:
	3160	+ case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
2974	3161	case MEDIA_BUS_FMT_RGB888_1X24:
2975	3162	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
2976	3163	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
..	..	@@ -2992,12 +3179,15 @@
2992	3179	struct vop *vop = to_vop(crtc);
2993	3180	u32 val;
2994	3181
2995		- if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
2996		- !(vop->data->feature & VOP_FEATURE_OUTPUT_10BIT))
	3182	+ if ((s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
	3183	+ !(vop->data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
	3184	+ (VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
	3185	+ s->output_if & VOP_OUTPUT_IF_BT656))
2997	3186	s->output_mode = ROCKCHIP_OUT_MODE_P888;
2998	3187
2999		- if (is_uv_swap(s->bus_format, s->output_mode))
3000		- VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP);
	3188	+ if (is_uv_swap(s->bus_format, s->output_mode) \|\|
	3189	+ is_rb_swap(s->bus_format, s->output_mode))
	3190	+ VOP_CTRL_SET(vop, dsp_rb_swap, 1);
3001	3191	else
3002	3192	VOP_CTRL_SET(vop, dsp_data_swap, 0);
3003	3193
..	..	@@ -3103,11 +3293,20 @@
3103	3293	int for_ddr_freq = 0;
3104	3294	bool dclk_inv, yc_swap = false;
3105	3295
	3296	+ if (old_state && old_state->self_refresh_active) {
	3297	+ drm_crtc_vblank_on(crtc);
	3298	+ if (vop->aclk_rate_reset)
	3299	+ clk_set_rate(vop->aclk, vop->aclk_rate);
	3300	+ vop->aclk_rate_reset = false;
	3301	+
	3302	+ return;
	3303	+ }
	3304	+
3106	3305	rockchip_set_system_status(sys_status);
3107	3306	vop_lock(vop);
3108	3307	DRM_DEV_INFO(vop->dev, "Update mode to %dx%d%s%d, type: %d\n",
3109	3308	hdisplay, vdisplay, interlaced ? "i" : "p",
3110		- adjusted_mode->vrefresh, s->output_type);
	3309	+ drm_mode_vrefresh(adjusted_mode), s->output_type);
3111	3310	vop_initial(crtc);
3112	3311	vop_disable_allwin(vop);
3113	3312	VOP_CTRL_SET(vop, standby, 0);
..	..	@@ -3124,6 +3323,9 @@
3124	3323	vop_mcu_mode(crtc);
3125	3324
3126	3325	dclk_inv = (s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
	3326	+ /* For improving signal quality, dclk need to be inverted by default on rv1106. */
	3327	+ if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12))
	3328	+ dclk_inv = !dclk_inv;
3127	3329
3128	3330	VOP_CTRL_SET(vop, dclk_pol, dclk_inv);
3129	3331	val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
..	..	@@ -3153,6 +3355,10 @@
3153	3355	yc_swap = is_yc_swap(s->bus_format);
3154	3356	VOP_CTRL_SET(vop, bt1120_yc_swap, yc_swap);
3155	3357	VOP_CTRL_SET(vop, yuv_clip, 1);
	3358	+ } else if (s->output_if & VOP_OUTPUT_IF_BT656) {
	3359	+ VOP_CTRL_SET(vop, bt656_en, 1);
	3360	+ yc_swap = is_yc_swap(s->bus_format);
	3361	+ VOP_CTRL_SET(vop, bt1120_yc_swap, yc_swap);
3156	3362	}
3157	3363	break;
3158	3364	case DRM_MODE_CONNECTOR_eDP:
..	..	@@ -3239,7 +3445,8 @@
3239	3445	VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 \| vsync_len);
3240	3446
3241	3447	VOP_CTRL_SET(vop, core_dclk_div,
3242		- !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
	3448	+ !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) \|\|
	3449	+ s->output_if & VOP_OUTPUT_IF_BT656);
3243	3450
3244	3451	VOP_CTRL_SET(vop, win_csc_mode_sel, 1);
3245	3452
..	..	@@ -3264,7 +3471,6 @@
3264	3471	struct drm_crtc_state *crtc_state)
3265	3472	{
3266	3473	struct vop *vop = to_vop(crtc);
3267		- const struct vop_data *vop_data = vop->data;
3268	3474	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
3269	3475	struct drm_atomic_state *state = crtc_state->state;
3270	3476	struct drm_plane *plane;
..	..	@@ -3294,8 +3500,8 @@
3294	3500	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16))
3295	3501	continue;
3296	3502
3297		- if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
3298		- DRM_ERROR("not support afbdc\n");
	3503	+ if (!VOP_CTRL_SUPPORT(vop, afbdc_en)) {
	3504	+ DRM_INFO("not support afbdc\n");
3299	3505	return -EINVAL;
3300	3506	}
3301	3507
..	..	@@ -3335,10 +3541,17 @@
3335	3541
3336	3542	if (VOP_CTRL_SUPPORT(vop, afbdc_pic_vir_width)) {
3337	3543	u32 align_x1, align_x2, align_y1, align_y2, align_val;
	3544	+ struct drm_gem_object *obj;
	3545	+ struct rockchip_gem_object *rk_obj;
	3546	+ dma_addr_t fb_addr;
	3547	+
	3548	+ obj = fb->obj[0];
	3549	+ rk_obj = to_rockchip_obj(obj);
	3550	+ fb_addr = rk_obj->dma_addr + fb->offsets[0];
3338	3551
3339	3552	s->afbdc_win_format = afbdc_format;
3340	3553	s->afbdc_win_id = win->win_id;
3341		- s->afbdc_win_ptr = rockchip_fb_get_dma_addr(fb, 0);
	3554	+ s->afbdc_win_ptr = fb_addr;
3342	3555	s->afbdc_win_vir_width = fb->width;
3343	3556	s->afbdc_win_xoffset = (src->x1 >> 16);
3344	3557	s->afbdc_win_yoffset = (src->y1 >> 16);
..	..	@@ -3722,6 +3935,7 @@
3722	3935	struct rockchip_crtc_state *s =
3723	3936	to_rockchip_crtc_state(crtc->state);
3724	3937	struct vop *vop = to_vop(crtc);
	3938	+ const struct vop_data *vop_data = vop->data;
3725	3939
3726	3940	spin_lock(&vop->reg_lock);
3727	3941
..	..	@@ -3749,7 +3963,8 @@
3749	3963	VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
3750	3964
3751	3965	VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
3752		- vop_post_config(crtc);
	3966	+ if (vop_data->feature & VOP_FEATURE_OVERSCAN)
	3967	+ vop_post_config(crtc);
3753	3968
3754	3969	spin_unlock(&vop->reg_lock);
3755	3970	}
..	..	@@ -3827,6 +4042,7 @@
3827	4042	spin_lock_irqsave(&vop->irq_lock, flags);
3828	4043	vop->pre_overlay = s->hdr.pre_overlay;
3829	4044	vop_cfg_done(vop);
	4045	+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_CFG_DONE, "cfg_done\n\n");
3830	4046	/*
3831	4047	* rk322x and rk332x odd-even field will mistake when in interlace mode.
3832	4048	* we must switch to frame effect before switch screen and switch to
..	..	@@ -3860,21 +4076,6 @@
3860	4076	crtc->state->event = NULL;
3861	4077	}
3862	4078	spin_unlock_irq(&crtc->dev->event_lock);
3863		-
3864		-#if 0
3865		- for_each_plane_in_state(old_state, plane, old_plane_state, i) {
3866		- if (!old_plane_state->fb)
3867		- continue;
3868		-
3869		- if (old_plane_state->fb == plane->state->fb)
3870		- continue;
3871		-
3872		- drm_framebuffer_get(old_plane_state->fb);
3873		- WARN_ON(drm_crtc_vblank_get(crtc) != 0);
3874		- drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
3875		- set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
3876		- }
3877		-#else
3878	4079	for_each_old_plane_in_state(old_state, plane, old_plane_state, i) {
3879	4080	if (!old_plane_state->fb)
3880	4081	continue;
..	..	@@ -3887,11 +4088,11 @@
3887	4088	drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
3888	4089	set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
3889	4090	}
3890		-#endif
3891	4091	}
3892	4092
3893	4093	static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
3894	4094	.mode_fixup = vop_crtc_mode_fixup,
	4095	+ .mode_valid = vop_crtc_mode_valid,
3895	4096	.atomic_check = vop_crtc_atomic_check,
3896	4097	.atomic_flush = vop_crtc_atomic_flush,
3897	4098	.atomic_enable = vop_crtc_atomic_enable,
..	..	@@ -3927,6 +4128,9 @@
3927	4128	static struct drm_crtc_state vop_crtc_duplicate_state(struct drm_crtc crtc)
3928	4129	{
3929	4130	struct rockchip_crtc_state rockchip_state, old_state;
	4131	+
	4132	+ if (WARN_ON(!crtc->state))
	4133	+ return NULL;
3930	4134
3931	4135	old_state = to_rockchip_crtc_state(crtc->state);
3932	4136	rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
..	..	@@ -4042,8 +4246,19 @@
4042	4246	return 0;
4043	4247	}
4044	4248
4045		- if (property == private->alpha_scale_prop) {
4046		- *val = (vop->data->feature & VOP_FEATURE_ALPHA_SCALE) ? 1 : 0;
	4249	+ if (property == private->aclk_prop) {
	4250	+ /* KHZ, keep align with mode->clock */
	4251	+ *val = clk_get_rate(vop->aclk) / 1000;
	4252	+ return 0;
	4253	+ }
	4254	+
	4255	+ if (property == private->bg_prop) {
	4256	+ *val = vop->background;
	4257	+ return 0;
	4258	+ }
	4259	+
	4260	+ if (property == private->line_flag_prop) {
	4261	+ *val = vop->line_flag;
4047	4262	return 0;
4048	4263	}
4049	4264
..	..	@@ -4057,9 +4272,10 @@
4057	4272	uint64_t val)
4058	4273	{
4059	4274	struct drm_device *drm_dev = crtc->dev;
	4275	+ struct rockchip_drm_private *private = drm_dev->dev_private;
4060	4276	struct drm_mode_config *mode_config = &drm_dev->mode_config;
4061	4277	struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
4062		- //struct vop *vop = to_vop(crtc);
	4278	+ struct vop *vop = to_vop(crtc);
4063	4279
4064	4280	if (property == mode_config->tv_left_margin_property) {
4065	4281	s->left_margin = val;
..	..	@@ -4078,6 +4294,16 @@
4078	4294
4079	4295	if (property == mode_config->tv_bottom_margin_property) {
4080	4296	s->bottom_margin = val;
	4297	+ return 0;
	4298	+ }
	4299	+
	4300	+ if (property == private->bg_prop) {
	4301	+ vop->background = val;
	4302	+ return 0;
	4303	+ }
	4304	+
	4305	+ if (property == private->line_flag_prop) {
	4306	+ vop->line_flag = val;
4081	4307	return 0;
4082	4308	}
4083	4309
..	..	@@ -4106,14 +4332,14 @@
4106	4332	struct vop *vop = container_of(work, struct vop, fb_unref_work);
4107	4333	struct drm_framebuffer *fb = val;
4108	4334
4109		- drm_crtc_vblank_put(&vop->crtc);
	4335	+ drm_crtc_vblank_put(&vop->rockchip_crtc.crtc);
4110	4336	drm_framebuffer_put(fb);
4111	4337	}
4112	4338
4113	4339	static void vop_handle_vblank(struct vop *vop)
4114	4340	{
4115	4341	struct drm_device *drm = vop->drm_dev;
4116		- struct drm_crtc *crtc = &vop->crtc;
	4342	+ struct drm_crtc *crtc = &vop->rockchip_crtc.crtc;
4117	4343	unsigned long flags;
4118	4344
4119	4345	spin_lock_irqsave(&drm->event_lock, flags);
..	..	@@ -4131,7 +4357,7 @@
4131	4357	static irqreturn_t vop_isr(int irq, void *data)
4132	4358	{
4133	4359	struct vop *vop = data;
4134		- struct drm_crtc *crtc = &vop->crtc;
	4360	+ struct drm_crtc *crtc = &vop->rockchip_crtc.crtc;
4135	4361	uint32_t active_irqs;
4136	4362	unsigned long flags;
4137	4363	int ret = IRQ_NONE;
..	..	@@ -4182,6 +4408,7 @@
4182	4408	* frame effective, but actually it's effective immediately, so
4183	4409	* we config this register at frame start.
4184	4410	*/
	4411	+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_VSYNC, "vsync\n");
4185	4412	spin_lock_irqsave(&vop->irq_lock, flags);
4186	4413	VOP_CTRL_SET(vop, level2_overlay_en, vop->pre_overlay);
4187	4414	VOP_CTRL_SET(vop, alpha_hard_calc, vop->pre_overlay);
..	..	@@ -4228,27 +4455,49 @@
4228	4455
4229	4456	flags \|= (VOP_WIN_SUPPORT(vop, win, xmirror)) ? DRM_MODE_REFLECT_X : 0;
4230	4457	flags \|= (VOP_WIN_SUPPORT(vop, win, ymirror)) ? DRM_MODE_REFLECT_Y : 0;
	4458	+
4231	4459	if (flags)
4232	4460	drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
4233	4461	DRM_MODE_ROTATE_0 \| flags);
	4462	+}
	4463	+
	4464	+static int vop_plane_create_name_property(struct vop vop, struct vop_win win)
	4465	+{
	4466	+ struct drm_prop_enum_list *props = vop->plane_name_list;
	4467	+ struct drm_property *prop;
	4468	+ uint64_t bits = BIT_ULL(win->plane_id);
	4469	+
	4470	+ prop = drm_property_create_bitmask(vop->drm_dev,
	4471	+ DRM_MODE_PROP_IMMUTABLE, "NAME",
	4472	+ props, vop->num_wins, bits);
	4473	+ if (!prop) {
	4474	+ DRM_DEV_ERROR(vop->dev, "create Name prop for %s failed\n", win->name);
	4475	+ return -ENOMEM;
	4476	+ }
	4477	+ win->name_prop = prop;
	4478	+ drm_object_attach_property(&win->base.base, win->name_prop, bits);
	4479	+
	4480	+ return 0;
4234	4481	}
4235	4482
4236	4483	static int vop_plane_init(struct vop vop, struct vop_win win,
4237	4484	unsigned long possible_crtcs)
4238	4485	{
4239	4486	struct rockchip_drm_private *private = vop->drm_dev->dev_private;
	4487	+ unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) \| BIT(DRM_MODE_BLEND_PREMULTI) \|
	4488	+ BIT(DRM_MODE_BLEND_COVERAGE);
	4489	+ const struct vop_data *vop_data = vop->data;
4240	4490	uint64_t feature = 0;
4241	4491	int ret;
4242	4492
4243	4493	ret = drm_universal_plane_init(vop->drm_dev, &win->base, possible_crtcs, &vop_plane_funcs,
4244		- win->data_formats, win->nformats, NULL, win->type, NULL);
	4494	+ win->data_formats, win->nformats, win->format_modifiers,
	4495	+ win->type, win->name);
4245	4496	if (ret) {
4246	4497	DRM_ERROR("failed to initialize plane %d\n", ret);
4247	4498	return ret;
4248	4499	}
4249	4500	drm_plane_helper_add(&win->base, &plane_helper_funcs);
4250		- drm_object_attach_property(&win->base.base,
4251		- vop->plane_zpos_prop, win->win_id);
4252	4501
4253	4502	if (win->phy->scl)
4254	4503	feature \|= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
..	..	@@ -4268,15 +4517,9 @@
4268	4517	drm_object_attach_property(&win->base.base,
4269	4518	private->color_space_prop, 0);
4270	4519	if (VOP_WIN_SUPPORT(vop, win, global_alpha_val))
4271		- drm_object_attach_property(&win->base.base,
4272		- private->global_alpha_prop, 0xff);
4273		- drm_object_attach_property(&win->base.base,
4274		- private->blend_mode_prop, 0);
	4520	+ drm_plane_create_alpha_property(&win->base);
4275	4521	drm_object_attach_property(&win->base.base,
4276	4522	private->async_commit_prop, 0);
4277		- if (VOP_WIN_SUPPORT(vop, win, color_key))
4278		- drm_object_attach_property(&win->base.base,
4279		- win->color_key_prop, 0);
4280	4523
4281	4524	if (win->parent)
4282	4525	drm_object_attach_property(&win->base.base, private->share_id_prop,
..	..	@@ -4284,6 +4527,45 @@
4284	4527	else
4285	4528	drm_object_attach_property(&win->base.base, private->share_id_prop,
4286	4529	win->base.base.id);
	4530	+
	4531	+ drm_plane_create_blend_mode_property(&win->base, blend_caps);
	4532	+ drm_plane_create_zpos_property(&win->base, win->win_id, 0, vop->num_wins - 1);
	4533	+ vop_plane_create_name_property(vop, win);
	4534	+
	4535	+
	4536	+ win->input_width_prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_IMMUTABLE,
	4537	+ "INPUT_WIDTH", 0, vop_data->max_input.width);
	4538	+ win->input_height_prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_IMMUTABLE,
	4539	+ "INPUT_HEIGHT", 0, vop_data->max_input.height);
	4540	+
	4541	+ win->output_width_prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_IMMUTABLE,
	4542	+ "OUTPUT_WIDTH", 0, vop_data->max_input.width);
	4543	+ win->output_height_prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_IMMUTABLE,
	4544	+ "OUTPUT_HEIGHT", 0, vop_data->max_input.height);
	4545	+
	4546	+ win->scale_prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_IMMUTABLE,
	4547	+ "SCALE_RATE", 8, 8);
	4548	+ /*
	4549	+ * Support 24 bit(RGB888) or 16 bit(rgb565) color key.
	4550	+ * Bit 31 is used as a flag to disable (0) or enable
	4551	+ * color keying (1).
	4552	+ */
	4553	+ if (VOP_WIN_SUPPORT(vop, win, color_key))
	4554	+ win->color_key_prop = drm_property_create_range(vop->drm_dev, 0,
	4555	+ "colorkey", 0, 0x80ffffff);
	4556	+ if (!win->input_width_prop \|\| !win->input_height_prop \|\|
	4557	+ !win->scale_prop) {
	4558	+ DRM_ERROR("failed to create property\n");
	4559	+ return -ENOMEM;
	4560	+ }
	4561	+
	4562	+ drm_object_attach_property(&win->base.base, win->input_width_prop, 0);
	4563	+ drm_object_attach_property(&win->base.base, win->input_height_prop, 0);
	4564	+ drm_object_attach_property(&win->base.base, win->output_width_prop, 0);
	4565	+ drm_object_attach_property(&win->base.base, win->output_height_prop, 0);
	4566	+ drm_object_attach_property(&win->base.base, win->scale_prop, 0);
	4567	+ if (VOP_WIN_SUPPORT(vop, win, color_key))
	4568	+ drm_object_attach_property(&win->base.base, win->color_key_prop, 0);
4287	4569
4288	4570	return 0;
4289	4571	}
..	..	@@ -4345,16 +4627,75 @@
4345	4627	return 0;
4346	4628	}
4347	4629
	4630	+static int vop_crtc_create_plane_mask_property(struct vop vop, struct drm_crtc crtc)
	4631	+{
	4632	+ struct drm_property *prop;
	4633	+
	4634	+ static const struct drm_prop_enum_list props[] = {
	4635	+ { ROCKCHIP_VOP_WIN0, "Win0" },
	4636	+ { ROCKCHIP_VOP_WIN1, "Win1" },
	4637	+ { ROCKCHIP_VOP_WIN2, "Win2" },
	4638	+ { ROCKCHIP_VOP_WIN3, "Win3" },
	4639	+ };
	4640	+
	4641	+ prop = drm_property_create_bitmask(vop->drm_dev,
	4642	+ DRM_MODE_PROP_IMMUTABLE, "PLANE_MASK",
	4643	+ props, ARRAY_SIZE(props),
	4644	+ 0xffffffff);
	4645	+ if (!prop) {
	4646	+ DRM_DEV_ERROR(vop->dev, "create plane_mask prop for vp%d failed\n", vop->id);
	4647	+ return -ENOMEM;
	4648	+ }
	4649	+
	4650	+ vop->plane_mask_prop = prop;
	4651	+ drm_object_attach_property(&crtc->base, vop->plane_mask_prop, vop->plane_mask);
	4652	+
	4653	+ return 0;
	4654	+}
	4655	+
	4656	+static int vop_crtc_create_feature_property(struct vop vop, struct drm_crtc crtc)
	4657	+{
	4658	+ const struct vop_data *vop_data = vop->data;
	4659	+
	4660	+ struct drm_property *prop;
	4661	+ u64 feature = 0;
	4662	+
	4663	+ static const struct drm_prop_enum_list props[] = {
	4664	+ { ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE, "ALPHA_SCALE" },
	4665	+ { ROCKCHIP_DRM_CRTC_FEATURE_HDR10, "HDR10" },
	4666	+ { ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR, "NEXT_HDR" },
	4667	+ };
	4668	+
	4669	+ if (vop_data->feature & VOP_FEATURE_ALPHA_SCALE)
	4670	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE);
	4671	+ if (vop_data->feature & VOP_FEATURE_HDR10)
	4672	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_HDR10);
	4673	+ if (vop_data->feature & VOP_FEATURE_NEXT_HDR)
	4674	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR);
	4675	+
	4676	+ prop = drm_property_create_bitmask(vop->drm_dev,
	4677	+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
	4678	+ props, ARRAY_SIZE(props),
	4679	+ 0xffffffff);
	4680	+ if (!prop) {
	4681	+ DRM_DEV_ERROR(vop->dev, "create FEATURE prop for vop%d failed\n", vop->id);
	4682	+ return -ENOMEM;
	4683	+ }
	4684	+
	4685	+ vop->feature_prop = prop;
	4686	+ drm_object_attach_property(&crtc->base, vop->feature_prop, feature);
	4687	+
	4688	+ return 0;
	4689	+}
	4690	+
4348	4691	static int vop_create_crtc(struct vop *vop)
4349	4692	{
4350	4693	struct device *dev = vop->dev;
4351		- const struct vop_data *vop_data = vop->data;
4352	4694	struct drm_device *drm_dev = vop->drm_dev;
4353	4695	struct rockchip_drm_private *private = drm_dev->dev_private;
4354	4696	struct drm_plane primary = NULL, cursor = NULL, plane, tmp;
4355		- struct drm_crtc *crtc = &vop->crtc;
	4697	+ struct drm_crtc *crtc = &vop->rockchip_crtc.crtc;
4356	4698	struct device_node *port;
4357		- uint64_t feature = 0;
4358	4699	int ret = 0;
4359	4700	int i;
4360	4701
..	..	@@ -4370,7 +4711,8 @@
4370	4711	win->type != DRM_PLANE_TYPE_CURSOR)
4371	4712	continue;
4372	4713
4373		- if (vop_plane_init(vop, win, 0)) {
	4714	+ ret = vop_plane_init(vop, win, 0);
	4715	+ if (ret) {
4374	4716	DRM_DEV_ERROR(vop->dev, "failed to init plane\n");
4375	4717	goto err_cleanup_planes;
4376	4718	}
..	..	@@ -4400,7 +4742,8 @@
4400	4742	if (win->type != DRM_PLANE_TYPE_OVERLAY)
4401	4743	continue;
4402	4744
4403		- if (vop_plane_init(vop, win, possible_crtcs)) {
	4745	+ ret = vop_plane_init(vop, win, possible_crtcs);
	4746	+ if (ret) {
4404	4747	DRM_DEV_ERROR(vop->dev, "failed to init overlay\n");
4405	4748	goto err_cleanup_crtc;
4406	4749	}
..	..	@@ -4423,6 +4766,12 @@
4423	4766	crtc->port = port;
4424	4767	rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
4425	4768
	4769	+ drm_object_attach_property(&crtc->base, private->soc_id_prop, vop->soc_id);
	4770	+ drm_object_attach_property(&crtc->base, private->port_id_prop, vop->id);
	4771	+ drm_object_attach_property(&crtc->base, private->aclk_prop, 0);
	4772	+ drm_object_attach_property(&crtc->base, private->bg_prop, 0);
	4773	+ drm_object_attach_property(&crtc->base, private->line_flag_prop, 0);
	4774	+
4426	4775	#define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
4427	4776	drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
4428	4777
..	..	@@ -4430,13 +4779,15 @@
4430	4779	VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
4431	4780	VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
4432	4781	VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
4433		-
4434	4782	#undef VOP_ATTACH_MODE_CONFIG_PROP
4435		- drm_object_attach_property(&crtc->base, private->alpha_scale_prop, 0);
4436		- if (vop_data->feature & VOP_FEATURE_AFBDC)
4437		- feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
4438		- drm_object_attach_property(&crtc->base, vop->feature_prop,
4439		- feature);
	4783	+ vop_crtc_create_plane_mask_property(vop, crtc);
	4784	+ vop_crtc_create_feature_property(vop, crtc);
	4785	+ ret = drm_self_refresh_helper_init(crtc);
	4786	+ if (ret)
	4787	+ DRM_DEV_DEBUG_KMS(vop->dev,
	4788	+ "Failed to init %s with SR helpers %d, ignoring\n",
	4789	+ crtc->name, ret);
	4790	+
4440	4791	if (vop->lut_regs) {
4441	4792	u16 r_base, g_base, *b_base;
4442	4793	u32 lut_len = vop->lut_len;
..	..	@@ -4483,9 +4834,11 @@
4483	4834
4484	4835	static void vop_destroy_crtc(struct vop *vop)
4485	4836	{
4486		- struct drm_crtc *crtc = &vop->crtc;
	4837	+ struct drm_crtc *crtc = &vop->rockchip_crtc.crtc;
4487	4838	struct drm_device *drm_dev = vop->drm_dev;
4488	4839	struct drm_plane plane, tmp;
	4840	+
	4841	+ drm_self_refresh_helper_cleanup(crtc);
4489	4842
4490	4843	of_node_put(crtc->port);
4491	4844
..	..	@@ -4537,16 +4890,15 @@
4537	4890	const struct vop_data *vop_data = vop->data;
4538	4891	unsigned int i, j;
4539	4892	unsigned int num_wins = 0;
4540		- struct drm_property *prop;
	4893	+ char name[DRM_PROP_NAME_LEN];
	4894	+ uint8_t plane_id = 0;
	4895	+ struct drm_prop_enum_list *plane_name_list;
4541	4896	static const struct drm_prop_enum_list props[] = {
4542	4897	{ ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
4543	4898	{ ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
4544	4899	{ ROCKCHIP_DRM_PLANE_FEATURE_HDR2SDR, "hdr2sdr" },
4545	4900	{ ROCKCHIP_DRM_PLANE_FEATURE_SDR2HDR, "sdr2hdr" },
4546	4901	{ ROCKCHIP_DRM_PLANE_FEATURE_AFBDC, "afbdc" },
4547		- };
4548		- static const struct drm_prop_enum_list crtc_props[] = {
4549		- { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
4550	4902	};
4551	4903
4552	4904	for (i = 0; i < vop_data->win_size; i++) {
..	..	@@ -4562,16 +4914,16 @@
4562	4914	vop_win->type = win_data->type;
4563	4915	vop_win->data_formats = win_data->phy->data_formats;
4564	4916	vop_win->nformats = win_data->phy->nformats;
	4917	+ vop_win->format_modifiers = win_data->format_modifiers;
4565	4918	vop_win->feature = win_data->feature;
4566	4919	vop_win->vop = vop;
4567	4920	vop_win->win_id = i;
4568	4921	vop_win->area_id = 0;
	4922	+ vop_win->plane_id = plane_id++;
	4923	+ snprintf(name, sizeof(name), "VOP%d-win%d-%d", vop->id, vop_win->win_id, vop_win->area_id);
	4924	+ vop_win->name = devm_kstrdup(vop->dev, name, GFP_KERNEL);
4569	4925	vop_win->zpos = vop_plane_get_zpos(win_data->type,
4570	4926	vop_data->win_size);
4571		- if (VOP_WIN_SUPPORT(vop, vop_win, color_key))
4572		- vop_win->color_key_prop = drm_property_create_range(vop->drm_dev, 0,
4573		- "colorkey", 0,
4574		- 0x80ffffff);
4575	4927
4576	4928	num_wins++;
4577	4929
..	..	@@ -4588,22 +4940,19 @@
4588	4940	vop_area->type = DRM_PLANE_TYPE_OVERLAY;
4589	4941	vop_area->data_formats = vop_win->data_formats;
4590	4942	vop_area->nformats = vop_win->nformats;
	4943	+ vop_area->format_modifiers = win_data->format_modifiers;
4591	4944	vop_area->vop = vop;
4592	4945	vop_area->win_id = i;
4593	4946	vop_area->area_id = j + 1;
	4947	+ vop_area->plane_id = plane_id++;
	4948	+ snprintf(name, sizeof(name), "VOP%d-win%d-%d", vop->id, vop_area->win_id, vop_area->area_id);
	4949	+ vop_area->name = devm_kstrdup(vop->dev, name, GFP_KERNEL);
4594	4950	num_wins++;
4595	4951	}
	4952	+ vop->plane_mask \|= BIT(vop_win->win_id);
4596	4953	}
4597	4954
4598	4955	vop->num_wins = num_wins;
4599		-
4600		- prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
4601		- "ZPOS", 0, vop->data->win_size - 1);
4602		- if (!prop) {
4603		- DRM_ERROR("failed to create zpos property\n");
4604		- return -EINVAL;
4605		- }
4606		- vop->plane_zpos_prop = prop;
4607	4956
4608	4957	vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
4609	4958	DRM_MODE_PROP_IMMUTABLE, "FEATURE",
..	..	@@ -4618,66 +4967,25 @@
4618	4967	return -EINVAL;
4619	4968	}
4620	4969
4621		- vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
4622		- DRM_MODE_PROP_IMMUTABLE, "FEATURE",
4623		- crtc_props, ARRAY_SIZE(crtc_props),
4624		- BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
4625		- if (!vop->feature_prop) {
4626		- DRM_ERROR("failed to create vop feature property\n");
4627		- return -EINVAL;
	4970	+ plane_name_list = devm_kzalloc(vop->dev,
	4971	+ vop->num_wins * sizeof(*plane_name_list),
	4972	+ GFP_KERNEL);
	4973	+ if (!plane_name_list) {
	4974	+ DRM_DEV_ERROR(vop->dev, "failed to alloc memory for plane_name_list\n");
	4975	+ return -ENOMEM;
4628	4976	}
	4977	+
	4978	+ for (i = 0; i < vop->num_wins; i++) {
	4979	+ struct vop_win *vop_win = &vop->win[i];
	4980	+
	4981	+ plane_name_list[i].type = vop_win->plane_id;
	4982	+ plane_name_list[i].name = vop_win->name;
	4983	+ }
	4984	+
	4985	+ vop->plane_name_list = plane_name_list;
4629	4986
4630	4987	return 0;
4631	4988	}
4632		-
4633		-/**
4634		- * rockchip_drm_wait_vact_end
4635		- * @crtc: CRTC to enable line flag
4636		- * @mstimeout: millisecond for timeout
4637		- *
4638		- * Wait for vact_end line flag irq or timeout.
4639		- *
4640		- * Returns:
4641		- * Zero on success, negative errno on failure.
4642		- */
4643		-int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
4644		-{
4645		- struct vop *vop = to_vop(crtc);
4646		- unsigned long jiffies_left;
4647		- int ret = 0;
4648		-
4649		- if (!crtc \|\| !vop->is_enabled)
4650		- return -ENODEV;
4651		-
4652		- mutex_lock(&vop->vop_lock);
4653		- if (mstimeout <= 0) {
4654		- ret = -EINVAL;
4655		- goto out;
4656		- }
4657		-
4658		- if (vop_line_flag_irq_is_enabled(vop)) {
4659		- ret = -EBUSY;
4660		- goto out;
4661		- }
4662		-
4663		- reinit_completion(&vop->line_flag_completion);
4664		- vop_line_flag_irq_enable(vop);
4665		-
4666		- jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
4667		- msecs_to_jiffies(mstimeout));
4668		- vop_line_flag_irq_disable(vop);
4669		-
4670		- if (jiffies_left == 0) {
4671		- DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
4672		- ret = -ETIMEDOUT;
4673		- goto out;
4674		- }
4675		-
4676		-out:
4677		- mutex_unlock(&vop->vop_lock);
4678		- return ret;
4679		-}
4680		-EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
4681	4989
4682	4990	static int vop_bind(struct device dev, struct device master, void *data)
4683	4991	{
..	..	@@ -4713,6 +5021,8 @@
4713	5021	vop->drm_dev = drm_dev;
4714	5022	vop->num_wins = num_wins;
4715	5023	vop->version = vop_data->version;
	5024	+ vop->soc_id = vop_data->soc_id;
	5025	+ vop->id = vop_data->vop_id;
4716	5026	dev_set_drvdata(dev, vop);
4717	5027	vop->support_multi_area = of_property_read_bool(dev->of_node, "support-multi-area");
4718	5028