~hc/RK356X_SDK_RELEASE.git

..	..	@@ -21,25 +21,32 @@
21	21	* DEALINGS IN THE SOFTWARE.
22	22	*/
23	23
24		-#include <linux/backlight.h>
	24	+#include <linux/delay.h>
25	25	#include <linux/gpio/consumer.h>
	26	+#include <linux/iopoll.h>
26	27	#include <linux/module.h>
27	28	#include <linux/of_platform.h>
28	29	#include <linux/platform_device.h>
29	30	#include <linux/regulator/consumer.h>
30		-
31		-#include <drm/drmP.h>
32		-#include <drm/drm_crtc.h>
33		-#include <drm/drm_mipi_dsi.h>
34		-#include <drm/drm_panel.h>
	31	+#include <linux/spi/spi.h>
35	32
36	33	#include <video/display_timing.h>
37	34	#include <video/mipi_display.h>
38	35	#include <video/of_display_timing.h>
39		-#include <linux/of_graph.h>
40	36	#include <video/videomode.h>
41	37
42		-#include "../rockchip/rockchip_drm_drv.h"
	38	+#include <drm/drm_crtc.h>
	39	+#include <drm/drm_device.h>
	40	+#include <drm/drm_mipi_dsi.h>
	41	+#include <drm/drm_panel.h>
	42	+#include <drm/drm_dsc.h>
	43	+
	44	+#include "panel-simple.h"
	45	+
	46	+enum panel_simple_cmd_type {
	47	+ CMD_TYPE_DEFAULT,
	48	+ CMD_TYPE_SPI
	49	+};
43	50
44	51	struct panel_cmd_header {
45	52	u8 data_type;
..	..	@@ -57,6 +64,22 @@
57	64	unsigned int cmd_cnt;
58	65	};
59	66
	67	+/**
	68	+ * @modes: Pointer to array of fixed modes appropriate for this panel. If
	69	+ * only one mode then this can just be the address of this the mode.
	70	+ * NOTE: cannot be used with "timings" and also if this is specified
	71	+ * then you cannot override the mode in the device tree.
	72	+ * @num_modes: Number of elements in modes array.
	73	+ * @timings: Pointer to array of display timings. NOTE: cannot be used with
	74	+ * "modes" and also these will be used to validate a device tree
	75	+ * override if one is present.
	76	+ * @num_timings: Number of elements in timings array.
	77	+ * @bpc: Bits per color.
	78	+ * @size: Structure containing the physical size of this panel.
	79	+ * @delay: Structure containing various delay values for this panel.
	80	+ * @bus_format: See MEDIA_BUS_FMT_... defines.
	81	+ * @bus_flags: See DRM_BUS_FLAG_... defines.
	82	+ */
60	83	struct panel_desc {
61	84	const struct drm_display_mode *modes;
62	85	unsigned int num_modes;
..	..	@@ -77,6 +100,8 @@
77	100	/**
78	101	* @prepare: the time (in milliseconds) that it takes for the panel to
79	102	* become ready and start receiving video data
	103	+ * @hpd_absent_delay: Add this to the prepare delay if we know Hot
	104	+ * Plug Detect isn't used.
80	105	* @enable: the time (in milliseconds) that it takes for the panel to
81	106	* display the first valid frame after starting to receive
82	107	* video data
..	..	@@ -91,6 +116,7 @@
91	116	*/
92	117	struct {
93	118	unsigned int prepare;
	119	+ unsigned int hpd_absent_delay;
94	120	unsigned int enable;
95	121	unsigned int disable;
96	122	unsigned int unprepare;
..	..	@@ -100,9 +126,15 @@
100	126
101	127	u32 bus_format;
102	128	u32 bus_flags;
	129	+ int connector_type;
103	130
104	131	struct panel_cmd_seq *init_seq;
105	132	struct panel_cmd_seq *exit_seq;
	133	+
	134	+ enum panel_simple_cmd_type cmd_type;
	135	+
	136	+ int (spi_read)(struct device dev, const u8 cmd, u8 *val);
	137	+ int (spi_write)(struct device dev, const u8 *data, size_t len, u8 type);
106	138	};
107	139
108	140	struct panel_simple {
..	..	@@ -111,62 +143,22 @@
111	143	bool prepared;
112	144	bool enabled;
113	145	bool power_invert;
	146	+ bool no_hpd;
114	147
115	148	const struct panel_desc *desc;
116	149
117		- struct backlight_device *backlight;
118	150	struct regulator *supply;
119		- struct regulator_bulk_data supplies[2];
120	151	struct i2c_adapter *ddc;
121	152
122	153	struct gpio_desc *enable_gpio;
123	154	struct gpio_desc *reset_gpio;
124		- int cmd_type;
	155	+ struct gpio_desc *hpd_gpio;
125	156
126		- struct gpio_desc *spi_sdi_gpio;
127		- struct gpio_desc *spi_scl_gpio;
128		- struct gpio_desc *spi_cs_gpio;
129		- struct device_node *np_crtc;
	157	+ struct drm_display_mode override_mode;
	158	+
	159	+ struct drm_dsc_picture_parameter_set *pps;
	160	+ enum drm_panel_orientation orientation;
130	161	};
131		-
132		-enum rockchip_cmd_type {
133		- CMD_TYPE_DEFAULT,
134		- CMD_TYPE_SPI,
135		- CMD_TYPE_MCU
136		-};
137		-
138		-enum MCU_IOCTL {
139		- MCU_WRCMD = 0,
140		- MCU_WRDATA,
141		- MCU_SETBYPASS,
142		-};
143		-
144		-enum rockchip_spi_cmd_type {
145		- SPI_3LINE_9BIT_MODE_CMD = 0,
146		- SPI_3LINE_9BIT_MODE_DATA,
147		- SPI_4LINE_8BIT_MODE,
148		-};
149		-
150		-static void panel_simple_sleep(unsigned int msec)
151		-{
152		- if (msec > 20)
153		- msleep(msec);
154		- else
155		- usleep_range(msec * 1000, (msec + 1) * 1000);
156		-}
157		-
158		-static inline int get_panel_cmd_type(const char *s)
159		-{
160		- if (!s)
161		- return -EINVAL;
162		-
163		- if (strncmp(s, "spi", 3) == 0)
164		- return CMD_TYPE_SPI;
165		- else if (strncmp(s, "mcu", 3) == 0)
166		- return CMD_TYPE_MCU;
167		-
168		- return CMD_TYPE_DEFAULT;
169		-}
170	162
171	163	static inline struct panel_simple to_panel_simple(struct drm_panel panel)
172	164	{
..	..	@@ -232,109 +224,16 @@
232	224	return 0;
233	225	}
234	226
235		-static void panel_simple_spi_write_cmd(struct panel_simple *panel,
236		- u8 type, int value)
237		-{
238		- int i;
239		-
240		- gpiod_direction_output(panel->spi_cs_gpio, 0);
241		-
242		- /**
243		- * send cmd or data flag for 3line 9bit serial data
244		- */
245		- if (type == SPI_3LINE_9BIT_MODE_CMD) {
246		- gpiod_direction_output(panel->spi_sdi_gpio, 0);
247		- gpiod_direction_output(panel->spi_scl_gpio, 0);
248		- udelay(10);
249		- gpiod_direction_output(panel->spi_scl_gpio, 1);
250		- udelay(10);
251		- } else if (type == SPI_3LINE_9BIT_MODE_DATA) {
252		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
253		- gpiod_direction_output(panel->spi_scl_gpio, 0);
254		- udelay(10);
255		- gpiod_direction_output(panel->spi_scl_gpio, 1);
256		- udelay(10);
257		- }
258		-
259		- /**
260		- * send the 8bit value from the MSB
261		- */
262		- for (i = 0; i < 8; i++) {
263		- if (value & 0x80)
264		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
265		- else
266		- gpiod_direction_output(panel->spi_sdi_gpio, 0);
267		-
268		- gpiod_direction_output(panel->spi_scl_gpio, 0);
269		- udelay(10);
270		- gpiod_direction_output(panel->spi_scl_gpio, 1);
271		- value <<= 1;
272		- udelay(10);
273		- }
274		-
275		- gpiod_direction_output(panel->spi_cs_gpio, 1);
276		-}
277		-
278		-static int panel_simple_xfer_mcu_cmd_seq(struct panel_simple *panel,
279		- struct panel_cmd_seq *cmds)
280		-{
281		- int i;
282		-
283		- if (!cmds)
284		- return -EINVAL;
285		-
286		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm,
287		- panel->np_crtc, MCU_SETBYPASS, 1);
288		- for (i = 0; i < cmds->cmd_cnt; i++) {
289		- struct panel_cmd_desc *cmd = &cmds->cmds[i];
290		- u32 value = 0;
291		-
292		- value = cmd->payload[0];
293		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm, panel->np_crtc,
294		- cmd->header.data_type, value);
295		- if (cmd->header.delay)
296		- panel_simple_sleep(cmd->header.delay);
297		- }
298		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm,
299		- panel->np_crtc, MCU_SETBYPASS, 0);
300		-
301		- return 0;
302		-}
303		-
304		-static int panel_simple_xfer_spi_cmd_seq(struct panel_simple *panel,
305		- struct panel_cmd_seq *cmds)
306		-{
307		- int i;
308		-
309		- if (!cmds)
310		- return -EINVAL;
311		-
312		- for (i = 0; i < cmds->cmd_cnt; i++) {
313		- struct panel_cmd_desc *cmd = &cmds->cmds[i];
314		- int value = 0;
315		-
316		- if (cmd->header.payload_length == 2)
317		- value = (cmd->payload[0] << 8) \| cmd->payload[1];
318		- else
319		- value = cmd->payload[0];
320		- panel_simple_spi_write_cmd(panel, cmd->header.data_type, value);
321		-
322		- if (cmd->header.delay)
323		- panel_simple_sleep(cmd->header.delay);
324		- }
325		-
326		- return 0;
327		-}
328		-
329		-#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
330	227	static int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
331		- struct panel_cmd_seq *seq)
	228	+ struct panel_cmd_seq *seq)
332	229	{
333	230	struct device *dev = panel->base.dev;
334	231	struct mipi_dsi_device *dsi = panel->dsi;
335	232	unsigned int i;
336	233	int err;
337	234
	235	+ if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI))
	236	+ return -EINVAL;
338	237	if (!seq)
339	238	return -EINVAL;
340	239
..	..	@@ -342,6 +241,9 @@
342	241	struct panel_cmd_desc *cmd = &seq->cmds[i];
343	242
344	243	switch (cmd->header.data_type) {
	244	+ case MIPI_DSI_COMPRESSION_MODE:
	245	+ err = mipi_dsi_compression_mode(dsi, cmd->payload[0]);
	246	+ break;
345	247	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
346	248	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
347	249	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
..	..	@@ -355,6 +257,18 @@
355	257	err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
356	258	cmd->header.payload_length);
357	259	break;
	260	+ case MIPI_DSI_PICTURE_PARAMETER_SET:
	261	+ if (!panel->pps) {
	262	+ panel->pps = devm_kzalloc(dev, sizeof(*panel->pps),
	263	+ GFP_KERNEL);
	264	+ if (!panel->pps)
	265	+ return -ENOMEM;
	266	+
	267	+ memcpy(panel->pps, cmd->payload, cmd->header.payload_length);
	268	+ }
	269	+
	270	+ err = mipi_dsi_picture_parameter_set(dsi, panel->pps);
	271	+ break;
358	272	default:
359	273	return -EINVAL;
360	274	}
..	..	@@ -363,37 +277,49 @@
363	277	dev_err(dev, "failed to write dcs cmd: %d\n", err);
364	278
365	279	if (cmd->header.delay)
366		- panel_simple_sleep(cmd->header.delay);
	280	+ usleep_range(cmd->header.delay * 1000, cmd->header.delay * 1000 + 100);
367	281	}
368	282
369	283	return 0;
370	284	}
371		-#else
372		-static inline int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
373		- struct panel_cmd_seq *seq)
374		-{
375		- return -EINVAL;
376		-}
377		-#endif
378	285
379		-static int panel_simple_get_fixed_modes(struct panel_simple *panel)
	286	+static int panel_simple_xfer_spi_cmd_seq(struct panel_simple panel, struct panel_cmd_seq cmds)
380	287	{
381		- struct drm_connector *connector = panel->base.connector;
382		- struct drm_device *drm = panel->base.drm;
	288	+ int i;
	289	+ int ret;
	290	+
	291	+ if (!cmds)
	292	+ return -EINVAL;
	293	+
	294	+ for (i = 0; i < cmds->cmd_cnt; i++) {
	295	+ struct panel_cmd_desc *cmd = &cmds->cmds[i];
	296	+
	297	+ ret = panel->desc->spi_write(panel->base.dev, cmd->payload,
	298	+ cmd->header.payload_length, cmd->header.data_type);
	299	+ if (ret)
	300	+ return ret;
	301	+
	302	+ if (cmd->header.delay)
	303	+ usleep_range(cmd->header.delay * 1000, cmd->header.delay * 1000 + 100);
	304	+ }
	305	+
	306	+ return 0;
	307	+}
	308	+
	309	+static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
	310	+ struct drm_connector *connector)
	311	+{
383	312	struct drm_display_mode *mode;
384	313	unsigned int i, num = 0;
385		-
386		- if (!panel->desc)
387		- return 0;
388	314
389	315	for (i = 0; i < panel->desc->num_timings; i++) {
390	316	const struct display_timing *dt = &panel->desc->timings[i];
391	317	struct videomode vm;
392	318
393	319	videomode_from_timing(dt, &vm);
394		- mode = drm_mode_create(drm);
	320	+ mode = drm_mode_create(connector->dev);
395	321	if (!mode) {
396		- dev_err(drm->dev, "failed to add mode %ux%u\n",
	322	+ dev_err(panel->base.dev, "failed to add mode %ux%u\n",
397	323	dt->hactive.typ, dt->vactive.typ);
398	324	continue;
399	325	}
..	..	@@ -409,13 +335,23 @@
409	335	num++;
410	336	}
411	337
	338	+ return num;
	339	+}
	340	+
	341	+static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
	342	+ struct drm_connector *connector)
	343	+{
	344	+ struct drm_display_mode *mode;
	345	+ unsigned int i, num = 0;
	346	+
412	347	for (i = 0; i < panel->desc->num_modes; i++) {
413	348	const struct drm_display_mode *m = &panel->desc->modes[i];
414	349
415		- mode = drm_mode_duplicate(drm, m);
	350	+ mode = drm_mode_duplicate(connector->dev, m);
416	351	if (!mode) {
417		- dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
418		- m->hdisplay, m->vdisplay, m->vrefresh);
	352	+ dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
	353	+ m->hdisplay, m->vdisplay,
	354	+ drm_mode_vrefresh(m));
419	355	continue;
420	356	}
421	357
..	..	@@ -429,6 +365,44 @@
429	365	drm_mode_probed_add(connector, mode);
430	366	num++;
431	367	}
	368	+
	369	+ return num;
	370	+}
	371	+
	372	+static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
	373	+ struct drm_connector *connector)
	374	+{
	375	+ struct drm_display_mode *mode;
	376	+ bool has_override = panel->override_mode.type;
	377	+ unsigned int num = 0;
	378	+
	379	+ if (!panel->desc)
	380	+ return 0;
	381	+
	382	+ if (has_override) {
	383	+ mode = drm_mode_duplicate(connector->dev,
	384	+ &panel->override_mode);
	385	+ if (mode) {
	386	+ drm_mode_probed_add(connector, mode);
	387	+ num = 1;
	388	+ } else {
	389	+ dev_err(panel->base.dev, "failed to add override mode\n");
	390	+ }
	391	+ }
	392	+
	393	+ /* Only add timings if override was not there or failed to validate */
	394	+ if (num == 0 && panel->desc->num_timings)
	395	+ num = panel_simple_get_timings_modes(panel, connector);
	396	+
	397	+ /*
	398	+ * Only add fixed modes if timings/override added no mode.
	399	+ *
	400	+ * We should only ever have either the display timings specified
	401	+ * or a fixed mode. Anything else is rather bogus.
	402	+ */
	403	+ WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
	404	+ if (num == 0)
	405	+ num = panel_simple_get_display_modes(panel, connector);
432	406
433	407	if (panel->desc->bpc)
434	408	connector->display_info.bpc = panel->desc->bpc;
..	..	@@ -448,10 +422,6 @@
448	422	static int panel_simple_regulator_enable(struct panel_simple *p)
449	423	{
450	424	int err;
451		-
452		- err = regulator_bulk_enable(ARRAY_SIZE(p->supplies), p->supplies);
453		- if (err < 0)
454		- return err;
455	425
456	426	if (p->power_invert) {
457	427	if (regulator_is_enabled(p->supply) > 0)
..	..	@@ -479,55 +449,37 @@
479	449	regulator_disable(p->supply);
480	450	}
481	451
482		- regulator_bulk_disable(ARRAY_SIZE(p->supplies), p->supplies);
483		-
484	452	return 0;
485	453	}
486	454
487		-static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
	455	+int panel_simple_loader_protect(struct drm_panel *panel)
488	456	{
489	457	struct panel_simple *p = to_panel_simple(panel);
490	458	int err;
491	459
492		- if (on) {
493		- err = panel_simple_regulator_enable(p);
494		- if (err < 0) {
495		- dev_err(panel->dev, "failed to enable supply: %d\n",
496		- err);
497		- return err;
498		- }
499		-
500		- p->prepared = true;
501		- p->enabled = true;
502		- } else {
503		- /* do nothing */
	460	+ err = panel_simple_regulator_enable(p);
	461	+ if (err < 0) {
	462	+ dev_err(panel->dev, "failed to enable supply: %d\n", err);
	463	+ return err;
504	464	}
	465	+
	466	+ p->prepared = true;
	467	+ p->enabled = true;
505	468
506	469	return 0;
507	470	}
	471	+EXPORT_SYMBOL(panel_simple_loader_protect);
508	472
509	473	static int panel_simple_disable(struct drm_panel *panel)
510	474	{
511	475	struct panel_simple *p = to_panel_simple(panel);
512		- int err = 0;
513	476
514	477	if (!p->enabled)
515	478	return 0;
516	479
517		- if (p->backlight) {
518		- p->backlight->props.power = FB_BLANK_POWERDOWN;
519		- p->backlight->props.state \|= BL_CORE_FBBLANK;
520		- backlight_update_status(p->backlight);
521		- }
522		-
523	480	if (p->desc->delay.disable)
524		- panel_simple_sleep(p->desc->delay.disable);
	481	+ usleep_range(p->desc->delay.disable * 1000, p->desc->delay.disable * 1000 + 100);
525	482
526		- if (p->cmd_type == CMD_TYPE_MCU) {
527		- err = panel_simple_xfer_mcu_cmd_seq(p, p->desc->exit_seq);
528		- if (err)
529		- dev_err(panel->dev, "failed to send exit cmds seq\n");
530		- }
531	483	p->enabled = false;
532	484
533	485	return 0;
..	..	@@ -536,30 +488,56 @@
536	488	static int panel_simple_unprepare(struct drm_panel *panel)
537	489	{
538	490	struct panel_simple *p = to_panel_simple(panel);
539		- int err = 0;
540	491
541	492	if (!p->prepared)
542	493	return 0;
543	494
544	495	if (p->desc->exit_seq) {
545		- if (p->dsi)
546		- panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
547		- else if (p->cmd_type == CMD_TYPE_SPI)
548		- err = panel_simple_xfer_spi_cmd_seq(p, p->desc->exit_seq);
549		- if (err)
550		- dev_err(panel->dev, "failed to send exit cmds seq\n");
	496	+ if (p->desc->cmd_type == CMD_TYPE_SPI) {
	497	+ if (panel_simple_xfer_spi_cmd_seq(p, p->desc->exit_seq)) {
	498	+ dev_err(panel->dev, "failed to send exit spi cmds seq\n");
	499	+ return -EINVAL;
	500	+ }
	501	+ } else {
	502	+ if (p->dsi)
	503	+ panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
	504	+ }
551	505	}
552	506
553	507	gpiod_direction_output(p->reset_gpio, 1);
554		-
555	508	gpiod_direction_output(p->enable_gpio, 0);
556	509
557	510	panel_simple_regulator_disable(p);
558	511
559	512	if (p->desc->delay.unprepare)
560		- panel_simple_sleep(p->desc->delay.unprepare);
	513	+ usleep_range(p->desc->delay.unprepare * 1000, p->desc->delay.unprepare * 1000 + 100);
561	514
562	515	p->prepared = false;
	516	+
	517	+ return 0;
	518	+}
	519	+
	520	+static int panel_simple_get_hpd_gpio(struct device *dev,
	521	+ struct panel_simple *p, bool from_probe)
	522	+{
	523	+ int err;
	524	+
	525	+ p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
	526	+ if (IS_ERR(p->hpd_gpio)) {
	527	+ err = PTR_ERR(p->hpd_gpio);
	528	+
	529	+ /*
	530	+ * If we're called from probe we won't consider '-EPROBE_DEFER'
	531	+ * to be an error--we'll leave the error code in "hpd_gpio".
	532	+ * When we try to use it we'll try again. This allows for
	533	+ * circular dependencies where the component providing the
	534	+ * hpd gpio needs the panel to init before probing.
	535	+ */
	536	+ if (err != -EPROBE_DEFER \|\| !from_probe) {
	537	+ dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
	538	+ return err;
	539	+ }
	540	+ }
563	541
564	542	return 0;
565	543	}
..	..	@@ -567,7 +545,9 @@
567	545	static int panel_simple_prepare(struct drm_panel *panel)
568	546	{
569	547	struct panel_simple *p = to_panel_simple(panel);
	548	+ unsigned int delay;
570	549	int err;
	550	+ int hpd_asserted;
571	551
572	552	if (p->prepared)
573	553	return 0;
..	..	@@ -580,26 +560,52 @@
580	560
581	561	gpiod_direction_output(p->enable_gpio, 1);
582	562
583		- if (p->desc->delay.prepare)
584		- panel_simple_sleep(p->desc->delay.prepare);
	563	+ delay = p->desc->delay.prepare;
	564	+ if (p->no_hpd)
	565	+ delay += p->desc->delay.hpd_absent_delay;
	566	+ if (delay)
	567	+ usleep_range(delay * 1000, delay * 1000 + 100);
	568	+
	569	+ if (p->hpd_gpio) {
	570	+ if (IS_ERR(p->hpd_gpio)) {
	571	+ err = panel_simple_get_hpd_gpio(panel->dev, p, false);
	572	+ if (err)
	573	+ return err;
	574	+ }
	575	+
	576	+ err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
	577	+ hpd_asserted, hpd_asserted,
	578	+ 1000, 2000000);
	579	+ if (hpd_asserted < 0)
	580	+ err = hpd_asserted;
	581	+
	582	+ if (err) {
	583	+ dev_err(panel->dev,
	584	+ "error waiting for hpd GPIO: %d\n", err);
	585	+ return err;
	586	+ }
	587	+ }
585	588
586	589	gpiod_direction_output(p->reset_gpio, 1);
587	590
588	591	if (p->desc->delay.reset)
589		- panel_simple_sleep(p->desc->delay.reset);
	592	+ usleep_range(p->desc->delay.reset * 1000, p->desc->delay.reset * 1000 + 100);
590	593
591	594	gpiod_direction_output(p->reset_gpio, 0);
592	595
593	596	if (p->desc->delay.init)
594		- panel_simple_sleep(p->desc->delay.init);
	597	+ usleep_range(p->desc->delay.init * 1000, p->desc->delay.init * 1000 + 100);
595	598
596	599	if (p->desc->init_seq) {
597		- if (p->dsi)
598		- panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
599		- else if (p->cmd_type == CMD_TYPE_SPI)
600		- err = panel_simple_xfer_spi_cmd_seq(p, p->desc->init_seq);
601		- if (err)
602		- dev_err(panel->dev, "failed to send init cmds seq\n");
	600	+ if (p->desc->cmd_type == CMD_TYPE_SPI) {
	601	+ if (panel_simple_xfer_spi_cmd_seq(p, p->desc->init_seq)) {
	602	+ dev_err(panel->dev, "failed to send init spi cmds seq\n");
	603	+ return -EINVAL;
	604	+ }
	605	+ } else {
	606	+ if (p->dsi)
	607	+ panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
	608	+ }
603	609	}
604	610
605	611	p->prepared = true;
..	..	@@ -610,47 +616,40 @@
610	616	static int panel_simple_enable(struct drm_panel *panel)
611	617	{
612	618	struct panel_simple *p = to_panel_simple(panel);
613		- int err = 0;
614	619
615	620	if (p->enabled)
616	621	return 0;
617	622
618		- if (p->cmd_type == CMD_TYPE_MCU) {
619		- err = panel_simple_xfer_mcu_cmd_seq(p, p->desc->init_seq);
620		- if (err)
621		- dev_err(panel->dev, "failed to send init cmds seq\n");
622		- }
623	623	if (p->desc->delay.enable)
624		- panel_simple_sleep(p->desc->delay.enable);
625		-
626		- if (p->backlight) {
627		- p->backlight->props.state &= ~BL_CORE_FBBLANK;
628		- p->backlight->props.power = FB_BLANK_UNBLANK;
629		- backlight_update_status(p->backlight);
630		- }
	624	+ usleep_range(p->desc->delay.enable * 1000, p->desc->delay.enable * 1000 + 100);
631	625
632	626	p->enabled = true;
633	627
634	628	return 0;
635	629	}
636	630
637		-static int panel_simple_get_modes(struct drm_panel *panel)
	631	+static int panel_simple_get_modes(struct drm_panel *panel,
	632	+ struct drm_connector *connector)
638	633	{
639	634	struct panel_simple *p = to_panel_simple(panel);
640	635	int num = 0;
641	636
642	637	/* probe EDID if a DDC bus is available */
643	638	if (p->ddc) {
644		- struct edid *edid = drm_get_edid(panel->connector, p->ddc);
645		- drm_connector_update_edid_property(panel->connector, edid);
	639	+ struct edid *edid = drm_get_edid(connector, p->ddc);
	640	+
	641	+ drm_connector_update_edid_property(connector, edid);
646	642	if (edid) {
647		- num += drm_add_edid_modes(panel->connector, edid);
	643	+ num += drm_add_edid_modes(connector, edid);
648	644	kfree(edid);
649	645	}
650	646	}
651	647
652	648	/* add hard-coded panel modes */
653		- num += panel_simple_get_fixed_modes(p);
	649	+ num += panel_simple_get_non_edid_modes(p, connector);
	650	+
	651	+ /* set up connector's "panel orientation" property */
	652	+ drm_connector_set_panel_orientation(connector, p->orientation);
654	653
655	654	return num;
656	655	}
..	..	@@ -673,7 +672,6 @@
673	672	}
674	673
675	674	static const struct drm_panel_funcs panel_simple_funcs = {
676		- .loader_protect = panel_simple_loader_protect,
677	675	.disable = panel_simple_disable,
678	676	.unprepare = panel_simple_unprepare,
679	677	.prepare = panel_simple_prepare,
..	..	@@ -682,11 +680,154 @@
682	680	.get_timings = panel_simple_get_timings,
683	681	};
684	682
	683	+static struct panel_desc panel_dpi;
	684	+
	685	+static int panel_dpi_probe(struct device *dev,
	686	+ struct panel_simple *panel)
	687	+{
	688	+ struct display_timing *timing;
	689	+ const struct device_node *np;
	690	+ struct panel_desc *desc;
	691	+ unsigned int bus_flags;
	692	+ struct videomode vm;
	693	+ int ret;
	694	+
	695	+ np = dev->of_node;
	696	+ desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
	697	+ if (!desc)
	698	+ return -ENOMEM;
	699	+
	700	+ timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
	701	+ if (!timing)
	702	+ return -ENOMEM;
	703	+
	704	+ ret = of_get_display_timing(np, "panel-timing", timing);
	705	+ if (ret < 0) {
	706	+ dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
	707	+ np);
	708	+ return ret;
	709	+ }
	710	+
	711	+ desc->timings = timing;
	712	+ desc->num_timings = 1;
	713	+
	714	+ of_property_read_u32(np, "width-mm", &desc->size.width);
	715	+ of_property_read_u32(np, "height-mm", &desc->size.height);
	716	+
	717	+ /* Extract bus_flags from display_timing */
	718	+ bus_flags = 0;
	719	+ vm.flags = timing->flags;
	720	+ drm_bus_flags_from_videomode(&vm, &bus_flags);
	721	+ desc->bus_flags = bus_flags;
	722	+
	723	+ /* We do not know the connector for the DT node, so guess it */
	724	+ desc->connector_type = DRM_MODE_CONNECTOR_DPI;
	725	+
	726	+ panel->desc = desc;
	727	+
	728	+ return 0;
	729	+}
	730	+
	731	+#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
	732	+ (to_check->field.typ >= bounds->field.min && \
	733	+ to_check->field.typ <= bounds->field.max)
	734	+static void panel_simple_parse_panel_timing_node(struct device *dev,
	735	+ struct panel_simple *panel,
	736	+ const struct display_timing *ot)
	737	+{
	738	+ const struct panel_desc *desc = panel->desc;
	739	+ struct videomode vm;
	740	+ unsigned int i;
	741	+
	742	+ if (WARN_ON(desc->num_modes)) {
	743	+ dev_err(dev, "Reject override mode: panel has a fixed mode\n");
	744	+ return;
	745	+ }
	746	+ if (WARN_ON(!desc->num_timings)) {
	747	+ dev_err(dev, "Reject override mode: no timings specified\n");
	748	+ return;
	749	+ }
	750	+
	751	+ for (i = 0; i < panel->desc->num_timings; i++) {
	752	+ const struct display_timing *dt = &panel->desc->timings[i];
	753	+
	754	+ if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) \|\|
	755	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) \|\|
	756	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) \|\|
	757	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) \|\|
	758	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) \|\|
	759	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) \|\|
	760	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) \|\|
	761	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
	762	+ continue;
	763	+
	764	+ if (ot->flags != dt->flags)
	765	+ continue;
	766	+
	767	+ videomode_from_timing(ot, &vm);
	768	+ drm_display_mode_from_videomode(&vm, &panel->override_mode);
	769	+ panel->override_mode.type \|= DRM_MODE_TYPE_DRIVER \|
	770	+ DRM_MODE_TYPE_PREFERRED;
	771	+ break;
	772	+ }
	773	+
	774	+ if (WARN_ON(!panel->override_mode.type))
	775	+ dev_err(dev, "Reject override mode: No display_timing found\n");
	776	+}
	777	+
	778	+static int dcs_bl_update_status(struct backlight_device *bl)
	779	+{
	780	+ struct panel_simple *p = bl_get_data(bl);
	781	+ struct mipi_dsi_device *dsi = p->dsi;
	782	+ int ret;
	783	+
	784	+ if (!p->prepared)
	785	+ return 0;
	786	+
	787	+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	788	+
	789	+ ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
	790	+ if (ret < 0)
	791	+ return ret;
	792	+
	793	+ dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
	794	+
	795	+ return 0;
	796	+}
	797	+
	798	+static int dcs_bl_get_brightness(struct backlight_device *bl)
	799	+{
	800	+ struct panel_simple *p = bl_get_data(bl);
	801	+ struct mipi_dsi_device *dsi = p->dsi;
	802	+ u16 brightness = bl->props.brightness;
	803	+ int ret;
	804	+
	805	+ if (!p->prepared)
	806	+ return 0;
	807	+
	808	+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	809	+
	810	+ ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
	811	+ if (ret < 0)
	812	+ return ret;
	813	+
	814	+ dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
	815	+
	816	+ return brightness & 0xff;
	817	+}
	818	+
	819	+static const struct backlight_ops dcs_bl_ops = {
	820	+ .update_status = dcs_bl_update_status,
	821	+ .get_brightness = dcs_bl_get_brightness,
	822	+};
	823	+
685	824	static int panel_simple_probe(struct device dev, const struct panel_desc desc)
686	825	{
687		- struct device_node backlight, ddc;
688	826	struct panel_simple *panel;
689		- const char *cmd_type;
	827	+ struct display_timing dt;
	828	+ struct device_node *ddc;
	829	+ int connector_type;
	830	+ u32 bus_flags;
690	831	int err;
691	832
692	833	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
..	..	@@ -697,20 +838,21 @@
697	838	panel->prepared = false;
698	839	panel->desc = desc;
699	840
	841	+ panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
	842	+ if (!panel->no_hpd) {
	843	+ err = panel_simple_get_hpd_gpio(dev, panel, true);
	844	+ if (err)
	845	+ return err;
	846	+ }
	847	+
700	848	panel->supply = devm_regulator_get(dev, "power");
701		- if (IS_ERR(panel->supply))
702		- return PTR_ERR(panel->supply);
703		-
704		- panel->supplies[0].supply = "vsp";
705		- panel->supplies[1].supply = "vsn";
706		-
707		- err = devm_regulator_bulk_get(dev, ARRAY_SIZE(panel->supplies),
708		- panel->supplies);
709		- if (err)
	849	+ if (IS_ERR(panel->supply)) {
	850	+ err = PTR_ERR(panel->supply);
	851	+ dev_err(dev, "failed to get power regulator: %d\n", err);
710	852	return err;
	853	+ }
711	854
712		- panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
713		- GPIOD_ASIS);
	855	+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
714	856	if (IS_ERR(panel->enable_gpio)) {
715	857	err = PTR_ERR(panel->enable_gpio);
716	858	if (err != -EPROBE_DEFER)
..	..	@@ -726,68 +868,13 @@
726	868	return err;
727	869	}
728	870
729		- if (of_property_read_string(dev->of_node, "rockchip,cmd-type",
730		- &cmd_type))
731		- panel->cmd_type = CMD_TYPE_DEFAULT;
732		- else
733		- panel->cmd_type = get_panel_cmd_type(cmd_type);
734		-
735		- if (panel->cmd_type == CMD_TYPE_SPI) {
736		- panel->spi_sdi_gpio =
737		- devm_gpiod_get_optional(dev, "spi-sdi", 0);
738		- if (IS_ERR(panel->spi_sdi_gpio)) {
739		- err = PTR_ERR(panel->spi_sdi_gpio);
740		- dev_err(dev, "failed to request spi_sdi: %d\n", err);
741		- return err;
742		- }
743		-
744		- panel->spi_scl_gpio =
745		- devm_gpiod_get_optional(dev, "spi-scl", 0);
746		- if (IS_ERR(panel->spi_scl_gpio)) {
747		- err = PTR_ERR(panel->spi_scl_gpio);
748		- dev_err(dev, "failed to request spi_scl: %d\n", err);
749		- return err;
750		- }
751		-
752		- panel->spi_cs_gpio = devm_gpiod_get_optional(dev, "spi-cs", 0);
753		- if (IS_ERR(panel->spi_cs_gpio)) {
754		- err = PTR_ERR(panel->spi_cs_gpio);
755		- dev_err(dev, "failed to request spi_cs: %d\n", err);
756		- return err;
757		- }
758		- gpiod_direction_output(panel->spi_cs_gpio, 1);
759		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
760		- gpiod_direction_output(panel->spi_scl_gpio, 1);
761		- } else if (panel->cmd_type == CMD_TYPE_MCU) {
762		- struct device_node port, endpoint;
763		- struct device_node *np;
764		-
765		- port = of_graph_get_port_by_id(dev->of_node, 0);
766		- if (port) {
767		- endpoint = of_get_next_child(port, NULL);
768		- /* get connect device node */
769		- np = of_graph_get_remote_port_parent(endpoint);
770		-
771		- port = of_graph_get_port_by_id(np, 0);
772		- if (port) {
773		- endpoint = of_get_next_child(port, NULL);
774		- /* get crtc device node */
775		- np = of_graph_get_remote_port_parent(endpoint);
776		- panel->np_crtc = np;
777		- }
778		- }
	871	+ err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
	872	+ if (err) {
	873	+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
	874	+ return err;
779	875	}
780		- panel->power_invert =
781		- of_property_read_bool(dev->of_node, "power-invert");
782	876
783		- backlight = of_parse_phandle(dev->of_node, "backlight", 0);
784		- if (backlight) {
785		- panel->backlight = of_find_backlight_by_node(backlight);
786		- of_node_put(backlight);
787		-
788		- if (!panel->backlight)
789		- return -EPROBE_DEFER;
790		- }
	877	+ panel->power_invert = of_property_read_bool(dev->of_node, "power-invert");
791	878
792	879	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
793	880	if (ddc) {
..	..	@@ -796,17 +883,87 @@
796	883
797	884	if (!panel->ddc) {
798	885	err = -EPROBE_DEFER;
799		- goto free_backlight;
	886	+ dev_err(dev, "failed to find ddc-i2c-bus: %d\n", err);
	887	+ return err;
800	888	}
801	889	}
802	890
803		- drm_panel_init(&panel->base);
804		- panel->base.dev = dev;
805		- panel->base.funcs = &panel_simple_funcs;
	891	+ if (desc == &panel_dpi) {
	892	+ /* Handle the generic panel-dpi binding */
	893	+ err = panel_dpi_probe(dev, panel);
	894	+ if (err)
	895	+ goto free_ddc;
	896	+ desc = panel->desc;
	897	+ } else {
	898	+ if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
	899	+ panel_simple_parse_panel_timing_node(dev, panel, &dt);
	900	+ }
806	901
807		- err = drm_panel_add(&panel->base);
808		- if (err < 0)
	902	+ connector_type = desc->connector_type;
	903	+ /* Catch common mistakes for panels. */
	904	+ switch (connector_type) {
	905	+ case 0:
	906	+ dev_dbg(dev, "Specify missing connector_type\n");
	907	+ connector_type = DRM_MODE_CONNECTOR_DPI;
	908	+ break;
	909	+ case DRM_MODE_CONNECTOR_LVDS:
	910	+ WARN_ON(desc->bus_flags &
	911	+ ~(DRM_BUS_FLAG_DE_LOW \|
	912	+ DRM_BUS_FLAG_DE_HIGH \|
	913	+ DRM_BUS_FLAG_DATA_MSB_TO_LSB \|
	914	+ DRM_BUS_FLAG_DATA_LSB_TO_MSB));
	915	+ WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
	916	+ desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
	917	+ desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
	918	+ WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
	919	+ desc->bpc != 6);
	920	+ WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG \|\|
	921	+ desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
	922	+ desc->bpc != 8);
	923	+ break;
	924	+ case DRM_MODE_CONNECTOR_eDP:
	925	+ if (desc->bus_format == 0)
	926	+ dev_warn(dev, "Specify missing bus_format\n");
	927	+ if (desc->bpc != 6 && desc->bpc != 8)
	928	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	929	+ break;
	930	+ case DRM_MODE_CONNECTOR_DSI:
	931	+ if (desc->bpc != 6 && desc->bpc != 8)
	932	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	933	+ break;
	934	+ case DRM_MODE_CONNECTOR_DPI:
	935	+ bus_flags = DRM_BUS_FLAG_DE_LOW \|
	936	+ DRM_BUS_FLAG_DE_HIGH \|
	937	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE \|
	938	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	939	+ DRM_BUS_FLAG_DATA_MSB_TO_LSB \|
	940	+ DRM_BUS_FLAG_DATA_LSB_TO_MSB \|
	941	+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE \|
	942	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
	943	+ if (desc->bus_flags & ~bus_flags)
	944	+ dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
	945	+ if (!(desc->bus_flags & bus_flags))
	946	+ dev_warn(dev, "Specify missing bus_flags\n");
	947	+ if (desc->bus_format == 0)
	948	+ dev_warn(dev, "Specify missing bus_format\n");
	949	+ if (desc->bpc != 6 && desc->bpc != 8)
	950	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	951	+ break;
	952	+ default:
	953	+ dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
	954	+ connector_type = DRM_MODE_CONNECTOR_DPI;
	955	+ break;
	956	+ }
	957	+
	958	+ drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
	959	+
	960	+ err = drm_panel_of_backlight(&panel->base);
	961	+ if (err) {
	962	+ dev_err(dev, "failed to find backlight: %d\n", err);
809	963	goto free_ddc;
	964	+ }
	965	+
	966	+ drm_panel_add(&panel->base);
810	967
811	968	dev_set_drvdata(dev, panel);
812	969
..	..	@@ -815,9 +972,6 @@
815	972	free_ddc:
816	973	if (panel->ddc)
817	974	put_device(&panel->ddc->dev);
818		-free_backlight:
819		- if (panel->backlight)
820		- put_device(&panel->backlight->dev);
821	975
822	976	return err;
823	977	}
..	..	@@ -827,15 +981,11 @@
827	981	struct panel_simple *panel = dev_get_drvdata(dev);
828	982
829	983	drm_panel_remove(&panel->base);
830		-
831		- panel_simple_disable(&panel->base);
832		- panel_simple_unprepare(&panel->base);
	984	+ drm_panel_disable(&panel->base);
	985	+ drm_panel_unprepare(&panel->base);
833	986
834	987	if (panel->ddc)
835	988	put_device(&panel->ddc->dev);
836		-
837		- if (panel->backlight)
838		- put_device(&panel->backlight->dev);
839	989
840	990	return 0;
841	991	}
..	..	@@ -844,14 +994,35 @@
844	994	{
845	995	struct panel_simple *panel = dev_get_drvdata(dev);
846	996
847		- panel_simple_disable(&panel->base);
848		-
849		- if (panel->prepared) {
850		- gpiod_direction_output(panel->reset_gpio, 1);
851		- gpiod_direction_output(panel->enable_gpio, 0);
852		- panel_simple_regulator_disable(panel);
853		- }
	997	+ drm_panel_disable(&panel->base);
	998	+ drm_panel_unprepare(&panel->base);
854	999	}
	1000	+
	1001	+static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
	1002	+ .clock = 71100,
	1003	+ .hdisplay = 1280,
	1004	+ .hsync_start = 1280 + 40,
	1005	+ .hsync_end = 1280 + 40 + 80,
	1006	+ .htotal = 1280 + 40 + 80 + 40,
	1007	+ .vdisplay = 800,
	1008	+ .vsync_start = 800 + 3,
	1009	+ .vsync_end = 800 + 3 + 10,
	1010	+ .vtotal = 800 + 3 + 10 + 10,
	1011	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	1012	+};
	1013	+
	1014	+static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
	1015	+ .modes = &ampire_am_1280800n3tzqw_t00h_mode,
	1016	+ .num_modes = 1,
	1017	+ .bpc = 8,
	1018	+ .size = {
	1019	+ .width = 217,
	1020	+ .height = 136,
	1021	+ },
	1022	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1023	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1024	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1025	+};
855	1026
856	1027	static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
857	1028	.clock = 9000,
..	..	@@ -863,7 +1034,6 @@
863	1034	.vsync_start = 272 + 2,
864	1035	.vsync_end = 272 + 2 + 10,
865	1036	.vtotal = 272 + 2 + 10 + 2,
866		- .vrefresh = 60,
867	1037	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
868	1038	};
869	1039
..	..	@@ -888,7 +1058,6 @@
888	1058	.vsync_start = 480 + 2,
889	1059	.vsync_end = 480 + 2 + 45,
890	1060	.vtotal = 480 + 2 + 45 + 0,
891		- .vrefresh = 60,
892	1061	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
893	1062	};
894	1063
..	..	@@ -926,7 +1095,7 @@
926	1095	.height = 86,
927	1096	},
928	1097	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
929		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	1098	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
930	1099	};
931	1100
932	1101	static const struct drm_display_mode auo_b101aw03_mode = {
..	..	@@ -939,7 +1108,6 @@
939	1108	.vsync_start = 600 + 16,
940	1109	.vsync_end = 600 + 16 + 6,
941	1110	.vtotal = 600 + 16 + 6 + 16,
942		- .vrefresh = 60,
943	1111	};
944	1112
945	1113	static const struct panel_desc auo_b101aw03 = {
..	..	@@ -950,24 +1118,26 @@
950	1118	.width = 223,
951	1119	.height = 125,
952	1120	},
	1121	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1122	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1123	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
953	1124	};
954	1125
955		-static const struct drm_display_mode auo_b101ean01_mode = {
956		- .clock = 72500,
957		- .hdisplay = 1280,
958		- .hsync_start = 1280 + 119,
959		- .hsync_end = 1280 + 119 + 32,
960		- .htotal = 1280 + 119 + 32 + 21,
961		- .vdisplay = 800,
962		- .vsync_start = 800 + 4,
963		- .vsync_end = 800 + 4 + 20,
964		- .vtotal = 800 + 4 + 20 + 8,
965		- .vrefresh = 60,
	1126	+static const struct display_timing auo_b101ean01_timing = {
	1127	+ .pixelclock = { 65300000, 72500000, 75000000 },
	1128	+ .hactive = { 1280, 1280, 1280 },
	1129	+ .hfront_porch = { 18, 119, 119 },
	1130	+ .hback_porch = { 21, 21, 21 },
	1131	+ .hsync_len = { 32, 32, 32 },
	1132	+ .vactive = { 800, 800, 800 },
	1133	+ .vfront_porch = { 4, 4, 4 },
	1134	+ .vback_porch = { 8, 8, 8 },
	1135	+ .vsync_len = { 18, 20, 20 },
966	1136	};
967	1137
968	1138	static const struct panel_desc auo_b101ean01 = {
969		- .modes = &auo_b101ean01_mode,
970		- .num_modes = 1,
	1139	+ .timings = &auo_b101ean01_timing,
	1140	+ .num_timings = 1,
971	1141	.bpc = 6,
972	1142	.size = {
973	1143	.width = 217,
..	..	@@ -985,7 +1155,6 @@
985	1155	.vsync_start = 768 + 14,
986	1156	.vsync_end = 768 + 14 + 42,
987	1157	.vtotal = 768 + 14 + 42,
988		- .vrefresh = 60,
989	1158	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
990	1159	};
991	1160
..	..	@@ -999,6 +1168,34 @@
999	1168	},
1000	1169	};
1001	1170
	1171	+static const struct drm_display_mode auo_b116xak01_mode = {
	1172	+ .clock = 69300,
	1173	+ .hdisplay = 1366,
	1174	+ .hsync_start = 1366 + 48,
	1175	+ .hsync_end = 1366 + 48 + 32,
	1176	+ .htotal = 1366 + 48 + 32 + 10,
	1177	+ .vdisplay = 768,
	1178	+ .vsync_start = 768 + 4,
	1179	+ .vsync_end = 768 + 4 + 6,
	1180	+ .vtotal = 768 + 4 + 6 + 15,
	1181	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	1182	+};
	1183	+
	1184	+static const struct panel_desc auo_b116xak01 = {
	1185	+ .modes = &auo_b116xak01_mode,
	1186	+ .num_modes = 1,
	1187	+ .bpc = 6,
	1188	+ .size = {
	1189	+ .width = 256,
	1190	+ .height = 144,
	1191	+ },
	1192	+ .delay = {
	1193	+ .hpd_absent_delay = 200,
	1194	+ },
	1195	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1196	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1197	+};
	1198	+
1002	1199	static const struct drm_display_mode auo_b116xw03_mode = {
1003	1200	.clock = 70589,
1004	1201	.hdisplay = 1366,
..	..	@@ -1009,7 +1206,7 @@
1009	1206	.vsync_start = 768 + 10,
1010	1207	.vsync_end = 768 + 10 + 12,
1011	1208	.vtotal = 768 + 10 + 12 + 6,
1012		- .vrefresh = 60,
	1209	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1013	1210	};
1014	1211
1015	1212	static const struct panel_desc auo_b116xw03 = {
..	..	@@ -1020,6 +1217,12 @@
1020	1217	.width = 256,
1021	1218	.height = 144,
1022	1219	},
	1220	+ .delay = {
	1221	+ .enable = 400,
	1222	+ },
	1223	+ .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
	1224	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1225	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
1023	1226	};
1024	1227
1025	1228	static const struct drm_display_mode auo_b133xtn01_mode = {
..	..	@@ -1032,7 +1235,6 @@
1032	1235	.vsync_start = 768 + 3,
1033	1236	.vsync_end = 768 + 3 + 6,
1034	1237	.vtotal = 768 + 3 + 6 + 13,
1035		- .vrefresh = 60,
1036	1238	};
1037	1239
1038	1240	static const struct panel_desc auo_b133xtn01 = {
..	..	@@ -1055,7 +1257,6 @@
1055	1257	.vsync_start = 1080 + 25,
1056	1258	.vsync_end = 1080 + 25 + 10,
1057	1259	.vtotal = 1080 + 25 + 10 + 10,
1058		- .vrefresh = 60,
1059	1260	};
1060	1261
1061	1262	static const struct panel_desc auo_b133htn01 = {
..	..	@@ -1101,6 +1302,30 @@
1101	1302	},
1102	1303	};
1103	1304
	1305	+static const struct drm_display_mode auo_g101evn010_mode = {
	1306	+ .clock = 68930,
	1307	+ .hdisplay = 1280,
	1308	+ .hsync_start = 1280 + 82,
	1309	+ .hsync_end = 1280 + 82 + 2,
	1310	+ .htotal = 1280 + 82 + 2 + 84,
	1311	+ .vdisplay = 800,
	1312	+ .vsync_start = 800 + 8,
	1313	+ .vsync_end = 800 + 8 + 2,
	1314	+ .vtotal = 800 + 8 + 2 + 6,
	1315	+};
	1316	+
	1317	+static const struct panel_desc auo_g101evn010 = {
	1318	+ .modes = &auo_g101evn010_mode,
	1319	+ .num_modes = 1,
	1320	+ .bpc = 6,
	1321	+ .size = {
	1322	+ .width = 216,
	1323	+ .height = 135,
	1324	+ },
	1325	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1326	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1327	+};
	1328	+
1104	1329	static const struct drm_display_mode auo_g104sn02_mode = {
1105	1330	.clock = 40000,
1106	1331	.hdisplay = 800,
..	..	@@ -1111,7 +1336,6 @@
1111	1336	.vsync_start = 600 + 10,
1112	1337	.vsync_end = 600 + 10 + 35,
1113	1338	.vtotal = 600 + 10 + 35 + 2,
1114		- .vrefresh = 60,
1115	1339	};
1116	1340
1117	1341	static const struct panel_desc auo_g104sn02 = {
..	..	@@ -1122,6 +1346,30 @@
1122	1346	.width = 211,
1123	1347	.height = 158,
1124	1348	},
	1349	+};
	1350	+
	1351	+static const struct drm_display_mode auo_g121ean01_mode = {
	1352	+ .clock = 66700,
	1353	+ .hdisplay = 1280,
	1354	+ .hsync_start = 1280 + 58,
	1355	+ .hsync_end = 1280 + 58 + 8,
	1356	+ .htotal = 1280 + 58 + 8 + 70,
	1357	+ .vdisplay = 800,
	1358	+ .vsync_start = 800 + 6,
	1359	+ .vsync_end = 800 + 6 + 4,
	1360	+ .vtotal = 800 + 6 + 4 + 10,
	1361	+};
	1362	+
	1363	+static const struct panel_desc auo_g121ean01 = {
	1364	+ .modes = &auo_g121ean01_mode,
	1365	+ .num_modes = 1,
	1366	+ .bpc = 8,
	1367	+ .size = {
	1368	+ .width = 261,
	1369	+ .height = 163,
	1370	+ },
	1371	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1372	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1125	1373	};
1126	1374
1127	1375	static const struct display_timing auo_g133han01_timings = {
..	..	@@ -1151,6 +1399,31 @@
1151	1399	.unprepare = 1000,
1152	1400	},
1153	1401	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	1402	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1403	+};
	1404	+
	1405	+static const struct drm_display_mode auo_g156xtn01_mode = {
	1406	+ .clock = 76000,
	1407	+ .hdisplay = 1366,
	1408	+ .hsync_start = 1366 + 33,
	1409	+ .hsync_end = 1366 + 33 + 67,
	1410	+ .htotal = 1560,
	1411	+ .vdisplay = 768,
	1412	+ .vsync_start = 768 + 4,
	1413	+ .vsync_end = 768 + 4 + 4,
	1414	+ .vtotal = 806,
	1415	+};
	1416	+
	1417	+static const struct panel_desc auo_g156xtn01 = {
	1418	+ .modes = &auo_g156xtn01_mode,
	1419	+ .num_modes = 1,
	1420	+ .bpc = 8,
	1421	+ .size = {
	1422	+ .width = 344,
	1423	+ .height = 194,
	1424	+ },
	1425	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1426	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1154	1427	};
1155	1428
1156	1429	static const struct display_timing auo_g185han01_timings = {
..	..	@@ -1180,6 +1453,37 @@
1180	1453	.unprepare = 1000,
1181	1454	},
1182	1455	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1456	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1457	+};
	1458	+
	1459	+static const struct display_timing auo_g190ean01_timings = {
	1460	+ .pixelclock = { 90000000, 108000000, 135000000 },
	1461	+ .hactive = { 1280, 1280, 1280 },
	1462	+ .hfront_porch = { 126, 184, 1266 },
	1463	+ .hback_porch = { 84, 122, 844 },
	1464	+ .hsync_len = { 70, 102, 704 },
	1465	+ .vactive = { 1024, 1024, 1024 },
	1466	+ .vfront_porch = { 4, 26, 76 },
	1467	+ .vback_porch = { 2, 8, 25 },
	1468	+ .vsync_len = { 2, 8, 25 },
	1469	+};
	1470	+
	1471	+static const struct panel_desc auo_g190ean01 = {
	1472	+ .timings = &auo_g190ean01_timings,
	1473	+ .num_timings = 1,
	1474	+ .bpc = 8,
	1475	+ .size = {
	1476	+ .width = 376,
	1477	+ .height = 301,
	1478	+ },
	1479	+ .delay = {
	1480	+ .prepare = 50,
	1481	+ .enable = 200,
	1482	+ .disable = 110,
	1483	+ .unprepare = 1000,
	1484	+ },
	1485	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1486	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1183	1487	};
1184	1488
1185	1489	static const struct display_timing auo_p320hvn03_timings = {
..	..	@@ -1208,6 +1512,7 @@
1208	1512	.unprepare = 500,
1209	1513	},
1210	1514	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1515	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1211	1516	};
1212	1517
1213	1518	static const struct drm_display_mode auo_t215hvn01_mode = {
..	..	@@ -1220,7 +1525,6 @@
1220	1525	.vsync_start = 1080 + 4,
1221	1526	.vsync_end = 1080 + 4 + 5,
1222	1527	.vtotal = 1080 + 4 + 5 + 36,
1223		- .vrefresh = 60,
1224	1528	};
1225	1529
1226	1530	static const struct panel_desc auo_t215hvn01 = {
..	..	@@ -1247,7 +1551,6 @@
1247	1551	.vsync_start = 600 + 17,
1248	1552	.vsync_end = 600 + 17 + 1,
1249	1553	.vtotal = 600 + 17 + 1 + 17,
1250		- .vrefresh = 60,
1251	1554	};
1252	1555
1253	1556	static const struct panel_desc avic_tm070ddh03 = {
..	..	@@ -1265,26 +1568,51 @@
1265	1568	},
1266	1569	};
1267	1570
	1571	+static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
	1572	+ .clock = 30000,
	1573	+ .hdisplay = 800,
	1574	+ .hsync_start = 800 + 40,
	1575	+ .hsync_end = 800 + 40 + 48,
	1576	+ .htotal = 800 + 40 + 48 + 40,
	1577	+ .vdisplay = 480,
	1578	+ .vsync_start = 480 + 13,
	1579	+ .vsync_end = 480 + 13 + 3,
	1580	+ .vtotal = 480 + 13 + 3 + 29,
	1581	+};
	1582	+
	1583	+static const struct panel_desc bananapi_s070wv20_ct16 = {
	1584	+ .modes = &bananapi_s070wv20_ct16_mode,
	1585	+ .num_modes = 1,
	1586	+ .bpc = 6,
	1587	+ .size = {
	1588	+ .width = 154,
	1589	+ .height = 86,
	1590	+ },
	1591	+};
	1592	+
1268	1593	static const struct drm_display_mode boe_hv070wsa_mode = {
1269		- .clock = 40800,
	1594	+ .clock = 42105,
1270	1595	.hdisplay = 1024,
1271		- .hsync_start = 1024 + 90,
1272		- .hsync_end = 1024 + 90 + 90,
1273		- .htotal = 1024 + 90 + 90 + 90,
	1596	+ .hsync_start = 1024 + 30,
	1597	+ .hsync_end = 1024 + 30 + 30,
	1598	+ .htotal = 1024 + 30 + 30 + 30,
1274	1599	.vdisplay = 600,
1275		- .vsync_start = 600 + 3,
1276		- .vsync_end = 600 + 3 + 4,
1277		- .vtotal = 600 + 3 + 4 + 3,
1278		- .vrefresh = 60,
	1600	+ .vsync_start = 600 + 10,
	1601	+ .vsync_end = 600 + 10 + 10,
	1602	+ .vtotal = 600 + 10 + 10 + 10,
1279	1603	};
1280	1604
1281	1605	static const struct panel_desc boe_hv070wsa = {
1282	1606	.modes = &boe_hv070wsa_mode,
1283	1607	.num_modes = 1,
	1608	+ .bpc = 8,
1284	1609	.size = {
1285	1610	.width = 154,
1286	1611	.height = 90,
1287	1612	},
	1613	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1614	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1615	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1288	1616	};
1289	1617
1290	1618	static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
..	..	@@ -1298,7 +1626,6 @@
1298	1626	.vsync_start = 800 + 3,
1299	1627	.vsync_end = 800 + 3 + 5,
1300	1628	.vtotal = 800 + 3 + 5 + 24,
1301		- .vrefresh = 60,
1302	1629	},
1303	1630	{
1304	1631	.clock = 57500,
..	..	@@ -1310,7 +1637,6 @@
1310	1637	.vsync_start = 800 + 3,
1311	1638	.vsync_end = 800 + 3 + 5,
1312	1639	.vtotal = 800 + 3 + 5 + 24,
1313		- .vrefresh = 48,
1314	1640	},
1315	1641	};
1316	1642
..	..	@@ -1329,6 +1655,214 @@
1329	1655	},
1330	1656	};
1331	1657
	1658	+/* Also used for boe_nv133fhm_n62 */
	1659	+static const struct drm_display_mode boe_nv133fhm_n61_modes = {
	1660	+ .clock = 147840,
	1661	+ .hdisplay = 1920,
	1662	+ .hsync_start = 1920 + 48,
	1663	+ .hsync_end = 1920 + 48 + 32,
	1664	+ .htotal = 1920 + 48 + 32 + 200,
	1665	+ .vdisplay = 1080,
	1666	+ .vsync_start = 1080 + 3,
	1667	+ .vsync_end = 1080 + 3 + 6,
	1668	+ .vtotal = 1080 + 3 + 6 + 31,
	1669	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1670	+};
	1671	+
	1672	+/* Also used for boe_nv133fhm_n62 */
	1673	+static const struct panel_desc boe_nv133fhm_n61 = {
	1674	+ .modes = &boe_nv133fhm_n61_modes,
	1675	+ .num_modes = 1,
	1676	+ .bpc = 6,
	1677	+ .size = {
	1678	+ .width = 294,
	1679	+ .height = 165,
	1680	+ },
	1681	+ .delay = {
	1682	+ /*
	1683	+ * When power is first given to the panel there's a short
	1684	+ * spike on the HPD line. It was explained that this spike
	1685	+ * was until the TCON data download was complete. On
	1686	+ * one system this was measured at 8 ms. We'll put 15 ms
	1687	+ * in the prepare delay just to be safe and take it away
	1688	+ * from the hpd_absent_delay (which would otherwise be 200 ms)
	1689	+ * to handle this. That means:
	1690	+ * - If HPD isn't hooked up you still have 200 ms delay.
	1691	+ * - If HPD is hooked up we won't try to look at it for the
	1692	+ * first 15 ms.
	1693	+ */
	1694	+ .prepare = 15,
	1695	+ .hpd_absent_delay = 185,
	1696	+
	1697	+ .unprepare = 500,
	1698	+ },
	1699	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	1700	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	1701	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1702	+};
	1703	+
	1704	+static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
	1705	+ {
	1706	+ .clock = 148500,
	1707	+ .hdisplay = 1920,
	1708	+ .hsync_start = 1920 + 48,
	1709	+ .hsync_end = 1920 + 48 + 32,
	1710	+ .htotal = 2200,
	1711	+ .vdisplay = 1080,
	1712	+ .vsync_start = 1080 + 3,
	1713	+ .vsync_end = 1080 + 3 + 5,
	1714	+ .vtotal = 1125,
	1715	+ },
	1716	+};
	1717	+
	1718	+static const struct panel_desc boe_nv140fhmn49 = {
	1719	+ .modes = boe_nv140fhmn49_modes,
	1720	+ .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
	1721	+ .bpc = 6,
	1722	+ .size = {
	1723	+ .width = 309,
	1724	+ .height = 174,
	1725	+ },
	1726	+ .delay = {
	1727	+ .prepare = 210,
	1728	+ .enable = 50,
	1729	+ .unprepare = 160,
	1730	+ },
	1731	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1732	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1733	+};
	1734	+
	1735	+static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
	1736	+ .clock = 9000,
	1737	+ .hdisplay = 480,
	1738	+ .hsync_start = 480 + 5,
	1739	+ .hsync_end = 480 + 5 + 5,
	1740	+ .htotal = 480 + 5 + 5 + 40,
	1741	+ .vdisplay = 272,
	1742	+ .vsync_start = 272 + 8,
	1743	+ .vsync_end = 272 + 8 + 8,
	1744	+ .vtotal = 272 + 8 + 8 + 8,
	1745	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1746	+};
	1747	+
	1748	+static const struct panel_desc cdtech_s043wq26h_ct7 = {
	1749	+ .modes = &cdtech_s043wq26h_ct7_mode,
	1750	+ .num_modes = 1,
	1751	+ .bpc = 8,
	1752	+ .size = {
	1753	+ .width = 95,
	1754	+ .height = 54,
	1755	+ },
	1756	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	1757	+};
	1758	+
	1759	+/* S070PWS19HP-FC21 2017/04/22 */
	1760	+static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
	1761	+ .clock = 51200,
	1762	+ .hdisplay = 1024,
	1763	+ .hsync_start = 1024 + 160,
	1764	+ .hsync_end = 1024 + 160 + 20,
	1765	+ .htotal = 1024 + 160 + 20 + 140,
	1766	+ .vdisplay = 600,
	1767	+ .vsync_start = 600 + 12,
	1768	+ .vsync_end = 600 + 12 + 3,
	1769	+ .vtotal = 600 + 12 + 3 + 20,
	1770	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1771	+};
	1772	+
	1773	+static const struct panel_desc cdtech_s070pws19hp_fc21 = {
	1774	+ .modes = &cdtech_s070pws19hp_fc21_mode,
	1775	+ .num_modes = 1,
	1776	+ .bpc = 6,
	1777	+ .size = {
	1778	+ .width = 154,
	1779	+ .height = 86,
	1780	+ },
	1781	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1782	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	1783	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	1784	+};
	1785	+
	1786	+/* S070SWV29HG-DC44 2017/09/21 */
	1787	+static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
	1788	+ .clock = 33300,
	1789	+ .hdisplay = 800,
	1790	+ .hsync_start = 800 + 210,
	1791	+ .hsync_end = 800 + 210 + 2,
	1792	+ .htotal = 800 + 210 + 2 + 44,
	1793	+ .vdisplay = 480,
	1794	+ .vsync_start = 480 + 22,
	1795	+ .vsync_end = 480 + 22 + 2,
	1796	+ .vtotal = 480 + 22 + 2 + 21,
	1797	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1798	+};
	1799	+
	1800	+static const struct panel_desc cdtech_s070swv29hg_dc44 = {
	1801	+ .modes = &cdtech_s070swv29hg_dc44_mode,
	1802	+ .num_modes = 1,
	1803	+ .bpc = 6,
	1804	+ .size = {
	1805	+ .width = 154,
	1806	+ .height = 86,
	1807	+ },
	1808	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1809	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	1810	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	1811	+};
	1812	+
	1813	+static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
	1814	+ .clock = 35000,
	1815	+ .hdisplay = 800,
	1816	+ .hsync_start = 800 + 40,
	1817	+ .hsync_end = 800 + 40 + 40,
	1818	+ .htotal = 800 + 40 + 40 + 48,
	1819	+ .vdisplay = 480,
	1820	+ .vsync_start = 480 + 29,
	1821	+ .vsync_end = 480 + 29 + 13,
	1822	+ .vtotal = 480 + 29 + 13 + 3,
	1823	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1824	+};
	1825	+
	1826	+static const struct panel_desc cdtech_s070wv95_ct16 = {
	1827	+ .modes = &cdtech_s070wv95_ct16_mode,
	1828	+ .num_modes = 1,
	1829	+ .bpc = 8,
	1830	+ .size = {
	1831	+ .width = 154,
	1832	+ .height = 85,
	1833	+ },
	1834	+};
	1835	+
	1836	+static const struct display_timing chefree_ch101olhlwh_002_timing = {
	1837	+ .pixelclock = { 68900000, 71100000, 73400000 },
	1838	+ .hactive = { 1280, 1280, 1280 },
	1839	+ .hfront_porch = { 65, 80, 95 },
	1840	+ .hback_porch = { 64, 79, 94 },
	1841	+ .hsync_len = { 1, 1, 1 },
	1842	+ .vactive = { 800, 800, 800 },
	1843	+ .vfront_porch = { 7, 11, 14 },
	1844	+ .vback_porch = { 7, 11, 14 },
	1845	+ .vsync_len = { 1, 1, 1 },
	1846	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	1847	+};
	1848	+
	1849	+static const struct panel_desc chefree_ch101olhlwh_002 = {
	1850	+ .timings = &chefree_ch101olhlwh_002_timing,
	1851	+ .num_timings = 1,
	1852	+ .bpc = 8,
	1853	+ .size = {
	1854	+ .width = 217,
	1855	+ .height = 135,
	1856	+ },
	1857	+ .delay = {
	1858	+ .enable = 200,
	1859	+ .disable = 200,
	1860	+ },
	1861	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1862	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1863	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1864	+};
	1865	+
1332	1866	static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1333	1867	.clock = 66770,
1334	1868	.hdisplay = 800,
..	..	@@ -1339,7 +1873,6 @@
1339	1873	.vsync_start = 1280 + 1,
1340	1874	.vsync_end = 1280 + 1 + 7,
1341	1875	.vtotal = 1280 + 1 + 7 + 15,
1342		- .vrefresh = 60,
1343	1876	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1344	1877	};
1345	1878
..	..	@@ -1351,6 +1884,9 @@
1351	1884	.width = 94,
1352	1885	.height = 150,
1353	1886	},
	1887	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1888	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1889	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1354	1890	};
1355	1891
1356	1892	static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
..	..	@@ -1363,7 +1899,6 @@
1363	1899	.vsync_start = 768 + 4,
1364	1900	.vsync_end = 768 + 4 + 4,
1365	1901	.vtotal = 768 + 4 + 4 + 4,
1366		- .vrefresh = 60,
1367	1902	};
1368	1903
1369	1904	static const struct panel_desc chunghwa_claa101wa01a = {
..	..	@@ -1374,6 +1909,9 @@
1374	1909	.width = 220,
1375	1910	.height = 120,
1376	1911	},
	1912	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1913	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1914	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1377	1915	};
1378	1916
1379	1917	static const struct drm_display_mode chunghwa_claa101wb01_mode = {
..	..	@@ -1386,7 +1924,6 @@
1386	1924	.vsync_start = 768 + 16,
1387	1925	.vsync_end = 768 + 16 + 8,
1388	1926	.vtotal = 768 + 16 + 8 + 16,
1389		- .vrefresh = 60,
1390	1927	};
1391	1928
1392	1929	static const struct panel_desc chunghwa_claa101wb01 = {
..	..	@@ -1397,6 +1934,9 @@
1397	1934	.width = 223,
1398	1935	.height = 125,
1399	1936	},
	1937	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1938	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1939	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1400	1940	};
1401	1941
1402	1942	static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
..	..	@@ -1409,7 +1949,6 @@
1409	1949	.vsync_start = 480 + 10,
1410	1950	.vsync_end = 480 + 10 + 2,
1411	1951	.vtotal = 480 + 10 + 2 + 33,
1412		- .vrefresh = 60,
1413	1952	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1414	1953	};
1415	1954
..	..	@@ -1422,7 +1961,7 @@
1422	1961	.height = 91,
1423	1962	},
1424	1963	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1425		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	1964	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1426	1965	};
1427	1966
1428	1967	static const struct display_timing dlc_dlc0700yzg_1_timing = {
..	..	@@ -1452,6 +1991,116 @@
1452	1991	.disable = 200,
1453	1992	},
1454	1993	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1994	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1995	+};
	1996	+
	1997	+static const struct display_timing dlc_dlc1010gig_timing = {
	1998	+ .pixelclock = { 68900000, 71100000, 73400000 },
	1999	+ .hactive = { 1280, 1280, 1280 },
	2000	+ .hfront_porch = { 43, 53, 63 },
	2001	+ .hback_porch = { 43, 53, 63 },
	2002	+ .hsync_len = { 44, 54, 64 },
	2003	+ .vactive = { 800, 800, 800 },
	2004	+ .vfront_porch = { 5, 8, 11 },
	2005	+ .vback_porch = { 5, 8, 11 },
	2006	+ .vsync_len = { 5, 7, 11 },
	2007	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	2008	+};
	2009	+
	2010	+static const struct panel_desc dlc_dlc1010gig = {
	2011	+ .timings = &dlc_dlc1010gig_timing,
	2012	+ .num_timings = 1,
	2013	+ .bpc = 8,
	2014	+ .size = {
	2015	+ .width = 216,
	2016	+ .height = 135,
	2017	+ },
	2018	+ .delay = {
	2019	+ .prepare = 60,
	2020	+ .enable = 150,
	2021	+ .disable = 100,
	2022	+ .unprepare = 60,
	2023	+ },
	2024	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2025	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2026	+};
	2027	+
	2028	+static const struct drm_display_mode edt_et035012dm6_mode = {
	2029	+ .clock = 6500,
	2030	+ .hdisplay = 320,
	2031	+ .hsync_start = 320 + 20,
	2032	+ .hsync_end = 320 + 20 + 30,
	2033	+ .htotal = 320 + 20 + 68,
	2034	+ .vdisplay = 240,
	2035	+ .vsync_start = 240 + 4,
	2036	+ .vsync_end = 240 + 4 + 4,
	2037	+ .vtotal = 240 + 4 + 4 + 14,
	2038	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2039	+};
	2040	+
	2041	+static const struct panel_desc edt_et035012dm6 = {
	2042	+ .modes = &edt_et035012dm6_mode,
	2043	+ .num_modes = 1,
	2044	+ .bpc = 8,
	2045	+ .size = {
	2046	+ .width = 70,
	2047	+ .height = 52,
	2048	+ },
	2049	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2050	+ .bus_flags = DRM_BUS_FLAG_DE_LOW \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
	2051	+};
	2052	+
	2053	+static const struct drm_display_mode edt_etm043080dh6gp_mode = {
	2054	+ .clock = 10870,
	2055	+ .hdisplay = 480,
	2056	+ .hsync_start = 480 + 8,
	2057	+ .hsync_end = 480 + 8 + 4,
	2058	+ .htotal = 480 + 8 + 4 + 41,
	2059	+
	2060	+ /*
	2061	+ * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
	2062	+ * fb_align
	2063	+ */
	2064	+
	2065	+ .vdisplay = 288,
	2066	+ .vsync_start = 288 + 2,
	2067	+ .vsync_end = 288 + 2 + 4,
	2068	+ .vtotal = 288 + 2 + 4 + 10,
	2069	+};
	2070	+
	2071	+static const struct panel_desc edt_etm043080dh6gp = {
	2072	+ .modes = &edt_etm043080dh6gp_mode,
	2073	+ .num_modes = 1,
	2074	+ .bpc = 8,
	2075	+ .size = {
	2076	+ .width = 100,
	2077	+ .height = 65,
	2078	+ },
	2079	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2080	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2081	+};
	2082	+
	2083	+static const struct drm_display_mode edt_etm0430g0dh6_mode = {
	2084	+ .clock = 9000,
	2085	+ .hdisplay = 480,
	2086	+ .hsync_start = 480 + 2,
	2087	+ .hsync_end = 480 + 2 + 41,
	2088	+ .htotal = 480 + 2 + 41 + 2,
	2089	+ .vdisplay = 272,
	2090	+ .vsync_start = 272 + 2,
	2091	+ .vsync_end = 272 + 2 + 10,
	2092	+ .vtotal = 272 + 2 + 10 + 2,
	2093	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2094	+};
	2095	+
	2096	+static const struct panel_desc edt_etm0430g0dh6 = {
	2097	+ .modes = &edt_etm0430g0dh6_mode,
	2098	+ .num_modes = 1,
	2099	+ .bpc = 6,
	2100	+ .size = {
	2101	+ .width = 95,
	2102	+ .height = 54,
	2103	+ },
1455	2104	};
1456	2105
1457	2106	static const struct drm_display_mode edt_et057090dhu_mode = {
..	..	@@ -1464,7 +2113,6 @@
1464	2113	.vsync_start = 480 + 10,
1465	2114	.vsync_end = 480 + 10 + 3,
1466	2115	.vtotal = 480 + 10 + 3 + 32,
1467		- .vrefresh = 60,
1468	2116	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1469	2117	};
1470	2118
..	..	@@ -1477,7 +2125,8 @@
1477	2125	.height = 86,
1478	2126	},
1479	2127	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1480		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_NEGEDGE,
	2128	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
	2129	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
1481	2130	};
1482	2131
1483	2132	static const struct drm_display_mode edt_etm0700g0dh6_mode = {
..	..	@@ -1490,7 +2139,6 @@
1490	2139	.vsync_start = 480 + 10,
1491	2140	.vsync_end = 480 + 10 + 2,
1492	2141	.vtotal = 480 + 10 + 2 + 33,
1493		- .vrefresh = 60,
1494	2142	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1495	2143	};
1496	2144
..	..	@@ -1503,7 +2151,7 @@
1503	2151	.height = 91,
1504	2152	},
1505	2153	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1506		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_NEGEDGE,
	2154	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1507	2155	};
1508	2156
1509	2157	static const struct panel_desc edt_etm0700g0bdh6 = {
..	..	@@ -1515,7 +2163,34 @@
1515	2163	.height = 91,
1516	2164	},
1517	2165	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1518		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	2166	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	2167	+};
	2168	+
	2169	+static const struct display_timing evervision_vgg804821_timing = {
	2170	+ .pixelclock = { 27600000, 33300000, 50000000 },
	2171	+ .hactive = { 800, 800, 800 },
	2172	+ .hfront_porch = { 40, 66, 70 },
	2173	+ .hback_porch = { 40, 67, 70 },
	2174	+ .hsync_len = { 40, 67, 70 },
	2175	+ .vactive = { 480, 480, 480 },
	2176	+ .vfront_porch = { 6, 10, 10 },
	2177	+ .vback_porch = { 7, 11, 11 },
	2178	+ .vsync_len = { 7, 11, 11 },
	2179	+ .flags = DISPLAY_FLAGS_HSYNC_HIGH \| DISPLAY_FLAGS_VSYNC_HIGH \|
	2180	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_NEGEDGE \|
	2181	+ DISPLAY_FLAGS_SYNC_NEGEDGE,
	2182	+};
	2183	+
	2184	+static const struct panel_desc evervision_vgg804821 = {
	2185	+ .timings = &evervision_vgg804821_timing,
	2186	+ .num_timings = 1,
	2187	+ .bpc = 8,
	2188	+ .size = {
	2189	+ .width = 108,
	2190	+ .height = 64,
	2191	+ },
	2192	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2193	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1519	2194	};
1520	2195
1521	2196	static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
..	..	@@ -1528,7 +2203,6 @@
1528	2203	.vsync_start = 480 + 37,
1529	2204	.vsync_end = 480 + 37 + 2,
1530	2205	.vtotal = 480 + 37 + 2 + 8,
1531		- .vrefresh = 60,
1532	2206	};
1533	2207
1534	2208	static const struct panel_desc foxlink_fl500wvr00_a0t = {
..	..	@@ -1542,6 +2216,68 @@
1542	2216	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1543	2217	};
1544	2218
	2219	+static const struct drm_display_mode frida_frd350h54004_modes[] = {
	2220	+ { /* 60 Hz */
	2221	+ .clock = 6000,
	2222	+ .hdisplay = 320,
	2223	+ .hsync_start = 320 + 44,
	2224	+ .hsync_end = 320 + 44 + 16,
	2225	+ .htotal = 320 + 44 + 16 + 20,
	2226	+ .vdisplay = 240,
	2227	+ .vsync_start = 240 + 2,
	2228	+ .vsync_end = 240 + 2 + 6,
	2229	+ .vtotal = 240 + 2 + 6 + 2,
	2230	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2231	+ },
	2232	+ { /* 50 Hz */
	2233	+ .clock = 5400,
	2234	+ .hdisplay = 320,
	2235	+ .hsync_start = 320 + 56,
	2236	+ .hsync_end = 320 + 56 + 16,
	2237	+ .htotal = 320 + 56 + 16 + 40,
	2238	+ .vdisplay = 240,
	2239	+ .vsync_start = 240 + 2,
	2240	+ .vsync_end = 240 + 2 + 6,
	2241	+ .vtotal = 240 + 2 + 6 + 2,
	2242	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2243	+ },
	2244	+};
	2245	+
	2246	+static const struct panel_desc frida_frd350h54004 = {
	2247	+ .modes = frida_frd350h54004_modes,
	2248	+ .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
	2249	+ .bpc = 8,
	2250	+ .size = {
	2251	+ .width = 77,
	2252	+ .height = 64,
	2253	+ },
	2254	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2255	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	2256	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2257	+};
	2258	+
	2259	+static const struct drm_display_mode friendlyarm_hd702e_mode = {
	2260	+ .clock = 67185,
	2261	+ .hdisplay = 800,
	2262	+ .hsync_start = 800 + 20,
	2263	+ .hsync_end = 800 + 20 + 24,
	2264	+ .htotal = 800 + 20 + 24 + 20,
	2265	+ .vdisplay = 1280,
	2266	+ .vsync_start = 1280 + 4,
	2267	+ .vsync_end = 1280 + 4 + 8,
	2268	+ .vtotal = 1280 + 4 + 8 + 4,
	2269	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2270	+};
	2271	+
	2272	+static const struct panel_desc friendlyarm_hd702e = {
	2273	+ .modes = &friendlyarm_hd702e_mode,
	2274	+ .num_modes = 1,
	2275	+ .size = {
	2276	+ .width = 94,
	2277	+ .height = 151,
	2278	+ },
	2279	+};
	2280	+
1545	2281	static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1546	2282	.clock = 9000,
1547	2283	.hdisplay = 480,
..	..	@@ -1552,7 +2288,6 @@
1552	2288	.vsync_start = 272 + 8,
1553	2289	.vsync_end = 272 + 8 + 1,
1554	2290	.vtotal = 272 + 8 + 1 + 8,
1555		- .vrefresh = 60,
1556	2291	};
1557	2292
1558	2293	static const struct panel_desc giantplus_gpg482739qs5 = {
..	..	@@ -1564,6 +2299,31 @@
1564	2299	.height = 54,
1565	2300	},
1566	2301	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2302	+};
	2303	+
	2304	+static const struct display_timing giantplus_gpm940b0_timing = {
	2305	+ .pixelclock = { 13500000, 27000000, 27500000 },
	2306	+ .hactive = { 320, 320, 320 },
	2307	+ .hfront_porch = { 14, 686, 718 },
	2308	+ .hback_porch = { 50, 70, 255 },
	2309	+ .hsync_len = { 1, 1, 1 },
	2310	+ .vactive = { 240, 240, 240 },
	2311	+ .vfront_porch = { 1, 1, 179 },
	2312	+ .vback_porch = { 1, 21, 31 },
	2313	+ .vsync_len = { 1, 1, 6 },
	2314	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW,
	2315	+};
	2316	+
	2317	+static const struct panel_desc giantplus_gpm940b0 = {
	2318	+ .timings = &giantplus_gpm940b0_timing,
	2319	+ .num_timings = 1,
	2320	+ .bpc = 8,
	2321	+ .size = {
	2322	+ .width = 60,
	2323	+ .height = 45,
	2324	+ },
	2325	+ .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
	2326	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1567	2327	};
1568	2328
1569	2329	static const struct display_timing hannstar_hsd070pww1_timing = {
..	..	@@ -1593,6 +2353,7 @@
1593	2353	.height = 94,
1594	2354	},
1595	2355	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2356	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1596	2357	};
1597	2358
1598	2359	static const struct display_timing hannstar_hsd100pxn1_timing = {
..	..	@@ -1617,6 +2378,7 @@
1617	2378	.height = 152,
1618	2379	},
1619	2380	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2381	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1620	2382	};
1621	2383
1622	2384	static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
..	..	@@ -1629,7 +2391,6 @@
1629	2391	.vsync_start = 480 + 16,
1630	2392	.vsync_end = 480 + 16 + 13,
1631	2393	.vtotal = 480 + 16 + 13 + 16,
1632		- .vrefresh = 60,
1633	2394	};
1634	2395
1635	2396	static const struct panel_desc hitachi_tx23d38vm0caa = {
..	..	@@ -1656,7 +2417,6 @@
1656	2417	.vsync_start = 272 + 2,
1657	2418	.vsync_end = 272 + 2 + 10,
1658	2419	.vtotal = 272 + 2 + 10 + 2,
1659		- .vrefresh = 60,
1660	2420	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1661	2421	};
1662	2422
..	..	@@ -1669,7 +2429,7 @@
1669	2429	.height = 54,
1670	2430	},
1671	2431	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1672		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	2432	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1673	2433	};
1674	2434
1675	2435	static const struct drm_display_mode innolux_at070tn92_mode = {
..	..	@@ -1682,7 +2442,6 @@
1682	2442	.vsync_start = 480 + 22,
1683	2443	.vsync_end = 480 + 22 + 10,
1684	2444	.vtotal = 480 + 22 + 23 + 10,
1685		- .vrefresh = 60,
1686	2445	};
1687	2446
1688	2447	static const struct panel_desc innolux_at070tn92 = {
..	..	@@ -1711,7 +2470,7 @@
1711	2470	static const struct panel_desc innolux_g070y2_l01 = {
1712	2471	.timings = &innolux_g070y2_l01_timing,
1713	2472	.num_timings = 1,
1714		- .bpc = 6,
	2473	+ .bpc = 8,
1715	2474	.size = {
1716	2475	.width = 152,
1717	2476	.height = 91,
..	..	@@ -1723,6 +2482,8 @@
1723	2482	.unprepare = 800,
1724	2483	},
1725	2484	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2485	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2486	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1726	2487	};
1727	2488
1728	2489	static const struct display_timing innolux_g101ice_l01_timing = {
..	..	@@ -1751,6 +2512,7 @@
1751	2512	.disable = 200,
1752	2513	},
1753	2514	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2515	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1754	2516	};
1755	2517
1756	2518	static const struct display_timing innolux_g121i1_l01_timing = {
..	..	@@ -1777,7 +2539,8 @@
1777	2539	.enable = 200,
1778	2540	.disable = 20,
1779	2541	},
1780		- .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2542	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2543	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1781	2544	};
1782	2545
1783	2546	static const struct drm_display_mode innolux_g121x1_l03_mode = {
..	..	@@ -1790,7 +2553,6 @@
1790	2553	.vsync_start = 768 + 38,
1791	2554	.vsync_end = 768 + 38 + 1,
1792	2555	.vtotal = 768 + 38 + 1 + 0,
1793		- .vrefresh = 60,
1794	2556	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1795	2557	};
1796	2558
..	..	@@ -1809,23 +2571,32 @@
1809	2571	},
1810	2572	};
1811	2573
1812		-static const struct drm_display_mode innolux_n116bge_mode = {
1813		- .clock = 76420,
1814		- .hdisplay = 1366,
1815		- .hsync_start = 1366 + 136,
1816		- .hsync_end = 1366 + 136 + 30,
1817		- .htotal = 1366 + 136 + 30 + 60,
1818		- .vdisplay = 768,
1819		- .vsync_start = 768 + 8,
1820		- .vsync_end = 768 + 8 + 12,
1821		- .vtotal = 768 + 8 + 12 + 12,
1822		- .vrefresh = 60,
1823		- .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2574	+/*
	2575	+ * Datasheet specifies that at 60 Hz refresh rate:
	2576	+ * - total horizontal time: { 1506, 1592, 1716 }
	2577	+ * - total vertical time: { 788, 800, 868 }
	2578	+ *
	2579	+ * ...but doesn't go into exactly how that should be split into a front
	2580	+ * porch, back porch, or sync length. For now we'll leave a single setting
	2581	+ * here which allows a bit of tweaking of the pixel clock at the expense of
	2582	+ * refresh rate.
	2583	+ */
	2584	+static const struct display_timing innolux_n116bge_timing = {
	2585	+ .pixelclock = { 72600000, 76420000, 80240000 },
	2586	+ .hactive = { 1366, 1366, 1366 },
	2587	+ .hfront_porch = { 136, 136, 136 },
	2588	+ .hback_porch = { 60, 60, 60 },
	2589	+ .hsync_len = { 30, 30, 30 },
	2590	+ .vactive = { 768, 768, 768 },
	2591	+ .vfront_porch = { 8, 8, 8 },
	2592	+ .vback_porch = { 12, 12, 12 },
	2593	+ .vsync_len = { 12, 12, 12 },
	2594	+ .flags = DISPLAY_FLAGS_VSYNC_LOW \| DISPLAY_FLAGS_HSYNC_LOW,
1824	2595	};
1825	2596
1826	2597	static const struct panel_desc innolux_n116bge = {
1827		- .modes = &innolux_n116bge_mode,
1828		- .num_modes = 1,
	2598	+ .timings = &innolux_n116bge_timing,
	2599	+ .num_timings = 1,
1829	2600	.bpc = 6,
1830	2601	.size = {
1831	2602	.width = 256,
..	..	@@ -1843,7 +2614,6 @@
1843	2614	.vsync_start = 768 + 2,
1844	2615	.vsync_end = 768 + 2 + 6,
1845	2616	.vtotal = 768 + 2 + 6 + 12,
1846		- .vrefresh = 60,
1847	2617	};
1848	2618
1849	2619	static const struct panel_desc innolux_n156bge_l21 = {
..	..	@@ -1854,9 +2624,12 @@
1854	2624	.width = 344,
1855	2625	.height = 193,
1856	2626	},
	2627	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2628	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2629	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1857	2630	};
1858	2631
1859		-static const struct drm_display_mode innolux_tv123wam_mode = {
	2632	+static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1860	2633	.clock = 206016,
1861	2634	.hdisplay = 2160,
1862	2635	.hsync_start = 2160 + 48,
..	..	@@ -1866,19 +2639,19 @@
1866	2639	.vsync_start = 1440 + 3,
1867	2640	.vsync_end = 1440 + 3 + 10,
1868	2641	.vtotal = 1440 + 3 + 10 + 27,
1869		- .vrefresh = 60,
1870	2642	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
1871	2643	};
1872	2644
1873		-static const struct panel_desc innolux_tv123wam = {
1874		- .modes = &innolux_tv123wam_mode,
	2645	+static const struct panel_desc innolux_p120zdg_bf1 = {
	2646	+ .modes = &innolux_p120zdg_bf1_mode,
1875	2647	.num_modes = 1,
1876	2648	.bpc = 8,
1877	2649	.size = {
1878		- .width = 259,
1879		- .height = 173,
	2650	+ .width = 254,
	2651	+ .height = 169,
1880	2652	},
1881	2653	.delay = {
	2654	+ .hpd_absent_delay = 200,
1882	2655	.unprepare = 500,
1883	2656	},
1884	2657	};
..	..	@@ -1893,7 +2666,6 @@
1893	2666	.vsync_start = 600 + 16,
1894	2667	.vsync_end = 600 + 16 + 4,
1895	2668	.vtotal = 600 + 16 + 4 + 16,
1896		- .vrefresh = 60,
1897	2669	};
1898	2670
1899	2671	static const struct panel_desc innolux_zj070na_01p = {
..	..	@@ -1904,6 +2676,118 @@
1904	2676	.width = 154,
1905	2677	.height = 90,
1906	2678	},
	2679	+};
	2680	+
	2681	+static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
	2682	+ .clock = 138778,
	2683	+ .hdisplay = 1920,
	2684	+ .hsync_start = 1920 + 24,
	2685	+ .hsync_end = 1920 + 24 + 48,
	2686	+ .htotal = 1920 + 24 + 48 + 88,
	2687	+ .vdisplay = 1080,
	2688	+ .vsync_start = 1080 + 3,
	2689	+ .vsync_end = 1080 + 3 + 12,
	2690	+ .vtotal = 1080 + 3 + 12 + 17,
	2691	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	2692	+};
	2693	+
	2694	+static const struct panel_desc ivo_m133nwf4_r0 = {
	2695	+ .modes = &ivo_m133nwf4_r0_mode,
	2696	+ .num_modes = 1,
	2697	+ .bpc = 8,
	2698	+ .size = {
	2699	+ .width = 294,
	2700	+ .height = 165,
	2701	+ },
	2702	+ .delay = {
	2703	+ .hpd_absent_delay = 200,
	2704	+ .unprepare = 500,
	2705	+ },
	2706	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2707	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	2708	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	2709	+};
	2710	+
	2711	+static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
	2712	+ .clock = 81000,
	2713	+ .hdisplay = 1366,
	2714	+ .hsync_start = 1366 + 40,
	2715	+ .hsync_end = 1366 + 40 + 32,
	2716	+ .htotal = 1366 + 40 + 32 + 62,
	2717	+ .vdisplay = 768,
	2718	+ .vsync_start = 768 + 5,
	2719	+ .vsync_end = 768 + 5 + 5,
	2720	+ .vtotal = 768 + 5 + 5 + 122,
	2721	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2722	+};
	2723	+
	2724	+static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
	2725	+ .modes = &kingdisplay_kd116n21_30nv_a010_mode,
	2726	+ .num_modes = 1,
	2727	+ .bpc = 6,
	2728	+ .size = {
	2729	+ .width = 256,
	2730	+ .height = 144,
	2731	+ },
	2732	+ .delay = {
	2733	+ .hpd_absent_delay = 200,
	2734	+ },
	2735	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2736	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	2737	+};
	2738	+
	2739	+static const struct display_timing koe_tx14d24vm1bpa_timing = {
	2740	+ .pixelclock = { 5580000, 5850000, 6200000 },
	2741	+ .hactive = { 320, 320, 320 },
	2742	+ .hfront_porch = { 30, 30, 30 },
	2743	+ .hback_porch = { 30, 30, 30 },
	2744	+ .hsync_len = { 1, 5, 17 },
	2745	+ .vactive = { 240, 240, 240 },
	2746	+ .vfront_porch = { 6, 6, 6 },
	2747	+ .vback_porch = { 5, 5, 5 },
	2748	+ .vsync_len = { 1, 2, 11 },
	2749	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	2750	+};
	2751	+
	2752	+static const struct panel_desc koe_tx14d24vm1bpa = {
	2753	+ .timings = &koe_tx14d24vm1bpa_timing,
	2754	+ .num_timings = 1,
	2755	+ .bpc = 6,
	2756	+ .size = {
	2757	+ .width = 115,
	2758	+ .height = 86,
	2759	+ },
	2760	+};
	2761	+
	2762	+static const struct display_timing koe_tx26d202vm0bwa_timing = {
	2763	+ .pixelclock = { 151820000, 156720000, 159780000 },
	2764	+ .hactive = { 1920, 1920, 1920 },
	2765	+ .hfront_porch = { 105, 130, 142 },
	2766	+ .hback_porch = { 45, 70, 82 },
	2767	+ .hsync_len = { 30, 30, 30 },
	2768	+ .vactive = { 1200, 1200, 1200},
	2769	+ .vfront_porch = { 3, 5, 10 },
	2770	+ .vback_porch = { 2, 5, 10 },
	2771	+ .vsync_len = { 5, 5, 5 },
	2772	+};
	2773	+
	2774	+static const struct panel_desc koe_tx26d202vm0bwa = {
	2775	+ .timings = &koe_tx26d202vm0bwa_timing,
	2776	+ .num_timings = 1,
	2777	+ .bpc = 8,
	2778	+ .size = {
	2779	+ .width = 217,
	2780	+ .height = 136,
	2781	+ },
	2782	+ .delay = {
	2783	+ .prepare = 1000,
	2784	+ .enable = 1000,
	2785	+ .unprepare = 1000,
	2786	+ .disable = 1000,
	2787	+ },
	2788	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2789	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2790	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1907	2791	};
1908	2792
1909	2793	static const struct display_timing koe_tx31d200vm0baa_timing = {
..	..	@@ -1928,6 +2812,7 @@
1928	2812	.height = 109,
1929	2813	},
1930	2814	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2815	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1931	2816	};
1932	2817
1933	2818	static const struct display_timing kyo_tcg121xglp_timing = {
..	..	@@ -1952,6 +2837,30 @@
1952	2837	.height = 184,
1953	2838	},
1954	2839	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2840	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2841	+};
	2842	+
	2843	+static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
	2844	+ .clock = 7000,
	2845	+ .hdisplay = 320,
	2846	+ .hsync_start = 320 + 20,
	2847	+ .hsync_end = 320 + 20 + 30,
	2848	+ .htotal = 320 + 20 + 30 + 38,
	2849	+ .vdisplay = 240,
	2850	+ .vsync_start = 240 + 4,
	2851	+ .vsync_end = 240 + 4 + 3,
	2852	+ .vtotal = 240 + 4 + 3 + 15,
	2853	+};
	2854	+
	2855	+static const struct panel_desc lemaker_bl035_rgb_002 = {
	2856	+ .modes = &lemaker_bl035_rgb_002_mode,
	2857	+ .num_modes = 1,
	2858	+ .size = {
	2859	+ .width = 70,
	2860	+ .height = 52,
	2861	+ },
	2862	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2863	+ .bus_flags = DRM_BUS_FLAG_DE_LOW,
1955	2864	};
1956	2865
1957	2866	static const struct drm_display_mode lg_lb070wv8_mode = {
..	..	@@ -1964,7 +2873,6 @@
1964	2873	.vsync_start = 480 + 10,
1965	2874	.vsync_end = 480 + 10 + 25,
1966	2875	.vtotal = 480 + 10 + 25 + 10,
1967		- .vrefresh = 60,
1968	2876	};
1969	2877
1970	2878	static const struct panel_desc lg_lb070wv8 = {
..	..	@@ -1976,6 +2884,7 @@
1976	2884	.height = 91,
1977	2885	},
1978	2886	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2887	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1979	2888	};
1980	2889
1981	2890	static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
..	..	@@ -1988,7 +2897,6 @@
1988	2897	.vsync_start = 2048 + 8,
1989	2898	.vsync_end = 2048 + 8 + 4,
1990	2899	.vtotal = 2048 + 8 + 4 + 8,
1991		- .vrefresh = 60,
1992	2900	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1993	2901	};
1994	2902
..	..	@@ -2011,7 +2919,6 @@
2011	2919	.vsync_start = 1536 + 3,
2012	2920	.vsync_end = 1536 + 3 + 1,
2013	2921	.vtotal = 1536 + 3 + 1 + 9,
2014		- .vrefresh = 60,
2015	2922	};
2016	2923
2017	2924	static const struct panel_desc lg_lp097qx1_spa1 = {
..	..	@@ -2033,7 +2940,6 @@
2033	2940	.vsync_start = 1280 + 4,
2034	2941	.vsync_end = 1280 + 4 + 4,
2035	2942	.vtotal = 1280 + 4 + 4 + 12,
2036		- .vrefresh = 60,
2037	2943	};
2038	2944
2039	2945	static const struct panel_desc lg_lp120up1 = {
..	..	@@ -2044,6 +2950,7 @@
2044	2950	.width = 267,
2045	2951	.height = 183,
2046	2952	},
	2953	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
2047	2954	};
2048	2955
2049	2956	static const struct drm_display_mode lg_lp129qe_mode = {
..	..	@@ -2056,7 +2963,6 @@
2056	2963	.vsync_start = 1700 + 3,
2057	2964	.vsync_end = 1700 + 3 + 10,
2058	2965	.vtotal = 1700 + 3 + 10 + 36,
2059		- .vrefresh = 60,
2060	2966	};
2061	2967
2062	2968	static const struct panel_desc lg_lp129qe = {
..	..	@@ -2069,6 +2975,64 @@
2069	2975	},
2070	2976	};
2071	2977
	2978	+static const struct display_timing logictechno_lt161010_2nh_timing = {
	2979	+ .pixelclock = { 26400000, 33300000, 46800000 },
	2980	+ .hactive = { 800, 800, 800 },
	2981	+ .hfront_porch = { 16, 210, 354 },
	2982	+ .hback_porch = { 46, 46, 46 },
	2983	+ .hsync_len = { 1, 20, 40 },
	2984	+ .vactive = { 480, 480, 480 },
	2985	+ .vfront_porch = { 7, 22, 147 },
	2986	+ .vback_porch = { 23, 23, 23 },
	2987	+ .vsync_len = { 1, 10, 20 },
	2988	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW \|
	2989	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_POSEDGE \|
	2990	+ DISPLAY_FLAGS_SYNC_POSEDGE,
	2991	+};
	2992	+
	2993	+static const struct panel_desc logictechno_lt161010_2nh = {
	2994	+ .timings = &logictechno_lt161010_2nh_timing,
	2995	+ .num_timings = 1,
	2996	+ .bpc = 6,
	2997	+ .size = {
	2998	+ .width = 154,
	2999	+ .height = 86,
	3000	+ },
	3001	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3002	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \|
	3003	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3004	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
	3005	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3006	+};
	3007	+
	3008	+static const struct display_timing logictechno_lt170410_2whc_timing = {
	3009	+ .pixelclock = { 68900000, 71100000, 73400000 },
	3010	+ .hactive = { 1280, 1280, 1280 },
	3011	+ .hfront_porch = { 23, 60, 71 },
	3012	+ .hback_porch = { 23, 60, 71 },
	3013	+ .hsync_len = { 15, 40, 47 },
	3014	+ .vactive = { 800, 800, 800 },
	3015	+ .vfront_porch = { 5, 7, 10 },
	3016	+ .vback_porch = { 5, 7, 10 },
	3017	+ .vsync_len = { 6, 9, 12 },
	3018	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW \|
	3019	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_POSEDGE \|
	3020	+ DISPLAY_FLAGS_SYNC_POSEDGE,
	3021	+};
	3022	+
	3023	+static const struct panel_desc logictechno_lt170410_2whc = {
	3024	+ .timings = &logictechno_lt170410_2whc_timing,
	3025	+ .num_timings = 1,
	3026	+ .bpc = 8,
	3027	+ .size = {
	3028	+ .width = 217,
	3029	+ .height = 136,
	3030	+ },
	3031	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3032	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3033	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3034	+};
	3035	+
2072	3036	static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2073	3037	.clock = 30400,
2074	3038	.hdisplay = 800,
..	..	@@ -2079,8 +3043,41 @@
2079	3043	.vsync_start = 480 + 0,
2080	3044	.vsync_end = 480 + 48 + 1,
2081	3045	.vtotal = 480 + 48 + 1 + 0,
2082		- .vrefresh = 60,
2083	3046	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3047	+};
	3048	+
	3049	+static const struct drm_display_mode logicpd_type_28_mode = {
	3050	+ .clock = 9107,
	3051	+ .hdisplay = 480,
	3052	+ .hsync_start = 480 + 3,
	3053	+ .hsync_end = 480 + 3 + 42,
	3054	+ .htotal = 480 + 3 + 42 + 2,
	3055	+
	3056	+ .vdisplay = 272,
	3057	+ .vsync_start = 272 + 2,
	3058	+ .vsync_end = 272 + 2 + 11,
	3059	+ .vtotal = 272 + 2 + 11 + 3,
	3060	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3061	+};
	3062	+
	3063	+static const struct panel_desc logicpd_type_28 = {
	3064	+ .modes = &logicpd_type_28_mode,
	3065	+ .num_modes = 1,
	3066	+ .bpc = 8,
	3067	+ .size = {
	3068	+ .width = 105,
	3069	+ .height = 67,
	3070	+ },
	3071	+ .delay = {
	3072	+ .prepare = 200,
	3073	+ .enable = 200,
	3074	+ .unprepare = 200,
	3075	+ .disable = 200,
	3076	+ },
	3077	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3078	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3079	+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
	3080	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2084	3081	};
2085	3082
2086	3083	static const struct panel_desc mitsubishi_aa070mc01 = {
..	..	@@ -2098,6 +3095,7 @@
2098	3095	.disable = 400,
2099	3096	},
2100	3097	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3098	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2101	3099	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2102	3100	};
2103	3101
..	..	@@ -2126,6 +3124,7 @@
2126	3124	.disable = 50,
2127	3125	},
2128	3126	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3127	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2129	3128	};
2130	3129
2131	3130	static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
..	..	@@ -2138,7 +3137,6 @@
2138	3137	.vsync_start = 272 + 2,
2139	3138	.vsync_end = 272 + 2 + 4,
2140	3139	.vtotal = 272 + 2 + 4 + 2,
2141		- .vrefresh = 74,
2142	3140	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2143	3141	};
2144	3142
..	..	@@ -2151,7 +3149,7 @@
2151	3149	.height = 54,
2152	3150	},
2153	3151	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2154		- .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
	3152	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2155	3153	};
2156	3154
2157	3155	static const struct drm_display_mode netron_dy_e231732_mode = {
..	..	@@ -2164,7 +3162,6 @@
2164	3162	.vsync_start = 600 + 127,
2165	3163	.vsync_end = 600 + 127 + 20,
2166	3164	.vtotal = 600 + 127 + 20 + 3,
2167		- .vrefresh = 60,
2168	3165	};
2169	3166
2170	3167	static const struct panel_desc netron_dy_e231732 = {
..	..	@@ -2177,6 +3174,49 @@
2177	3174	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2178	3175	};
2179	3176
	3177	+static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
	3178	+ {
	3179	+ .clock = 138500,
	3180	+ .hdisplay = 1920,
	3181	+ .hsync_start = 1920 + 48,
	3182	+ .hsync_end = 1920 + 48 + 32,
	3183	+ .htotal = 1920 + 48 + 32 + 80,
	3184	+ .vdisplay = 1080,
	3185	+ .vsync_start = 1080 + 3,
	3186	+ .vsync_end = 1080 + 3 + 5,
	3187	+ .vtotal = 1080 + 3 + 5 + 23,
	3188	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3189	+ }, {
	3190	+ .clock = 110920,
	3191	+ .hdisplay = 1920,
	3192	+ .hsync_start = 1920 + 48,
	3193	+ .hsync_end = 1920 + 48 + 32,
	3194	+ .htotal = 1920 + 48 + 32 + 80,
	3195	+ .vdisplay = 1080,
	3196	+ .vsync_start = 1080 + 3,
	3197	+ .vsync_end = 1080 + 3 + 5,
	3198	+ .vtotal = 1080 + 3 + 5 + 23,
	3199	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3200	+ }
	3201	+};
	3202	+
	3203	+static const struct panel_desc neweast_wjfh116008a = {
	3204	+ .modes = neweast_wjfh116008a_modes,
	3205	+ .num_modes = 2,
	3206	+ .bpc = 6,
	3207	+ .size = {
	3208	+ .width = 260,
	3209	+ .height = 150,
	3210	+ },
	3211	+ .delay = {
	3212	+ .prepare = 110,
	3213	+ .enable = 20,
	3214	+ .unprepare = 500,
	3215	+ },
	3216	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3217	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	3218	+};
	3219	+
2180	3220	static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2181	3221	.clock = 9000,
2182	3222	.hdisplay = 480,
..	..	@@ -2187,7 +3227,6 @@
2187	3227	.vsync_start = 272 + 2,
2188	3228	.vsync_end = 272 + 2 + 10,
2189	3229	.vtotal = 272 + 2 + 10 + 2,
2190		- .vrefresh = 60,
2191	3230	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2192	3231	};
2193	3232
..	..	@@ -2200,8 +3239,9 @@
2200	3239	.height = 54,
2201	3240	},
2202	3241	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2203		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE \|
2204		- DRM_BUS_FLAG_SYNC_POSEDGE,
	3242	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3243	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3244	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2205	3245	};
2206	3246
2207	3247	static const struct display_timing nlt_nl192108ac18_02d_timing = {
..	..	@@ -2228,6 +3268,7 @@
2228	3268	.unprepare = 500,
2229	3269	},
2230	3270	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3271	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2231	3272	};
2232	3273
2233	3274	static const struct drm_display_mode nvd_9128_mode = {
..	..	@@ -2251,6 +3292,7 @@
2251	3292	.height = 88,
2252	3293	},
2253	3294	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3295	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2254	3296	};
2255	3297
2256	3298	static const struct display_timing okaya_rs800480t_7x0gp_timing = {
..	..	@@ -2293,7 +3335,6 @@
2293	3335	.vsync_start = 272 + 8,
2294	3336	.vsync_end = 272 + 8 + 5,
2295	3337	.vtotal = 272 + 8 + 5 + 3,
2296		- .vrefresh = 60,
2297	3338	};
2298	3339
2299	3340	static const struct panel_desc olimex_lcd_olinuxino_43ts = {
..	..	@@ -2321,7 +3362,6 @@
2321	3362	.vsync_start = 483,
2322	3363	.vsync_end = 493,
2323	3364	.vtotal = 500,
2324		- .vrefresh = 60,
2325	3365	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2326	3366	};
2327	3367
..	..	@@ -2340,6 +3380,32 @@
2340	3380	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2341	3381	};
2342	3382
	3383	+static const struct drm_display_mode ortustech_com37h3m_mode = {
	3384	+ .clock = 22230,
	3385	+ .hdisplay = 480,
	3386	+ .hsync_start = 480 + 40,
	3387	+ .hsync_end = 480 + 40 + 10,
	3388	+ .htotal = 480 + 40 + 10 + 40,
	3389	+ .vdisplay = 640,
	3390	+ .vsync_start = 640 + 4,
	3391	+ .vsync_end = 640 + 4 + 2,
	3392	+ .vtotal = 640 + 4 + 2 + 4,
	3393	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3394	+};
	3395	+
	3396	+static const struct panel_desc ortustech_com37h3m = {
	3397	+ .modes = &ortustech_com37h3m_mode,
	3398	+ .num_modes = 1,
	3399	+ .bpc = 8,
	3400	+ .size = {
	3401	+ .width = 56, /* 56.16mm */
	3402	+ .height = 75, /* 74.88mm */
	3403	+ },
	3404	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3405	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3406	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3407	+};
	3408	+
2343	3409	static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2344	3410	.clock = 25000,
2345	3411	.hdisplay = 480,
..	..	@@ -2350,19 +3416,94 @@
2350	3416	.vsync_start = 800 + 3,
2351	3417	.vsync_end = 800 + 3 + 3,
2352	3418	.vtotal = 800 + 3 + 3 + 3,
2353		- .vrefresh = 60,
2354	3419	};
2355	3420
2356	3421	static const struct panel_desc ortustech_com43h4m85ulc = {
2357	3422	.modes = &ortustech_com43h4m85ulc_mode,
2358	3423	.num_modes = 1,
2359		- .bpc = 8,
	3424	+ .bpc = 6,
2360	3425	.size = {
2361	3426	.width = 56,
2362	3427	.height = 93,
2363	3428	},
	3429	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3430	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	3431	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3432	+};
	3433	+
	3434	+static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
	3435	+ .clock = 33000,
	3436	+ .hdisplay = 800,
	3437	+ .hsync_start = 800 + 210,
	3438	+ .hsync_end = 800 + 210 + 30,
	3439	+ .htotal = 800 + 210 + 30 + 16,
	3440	+ .vdisplay = 480,
	3441	+ .vsync_start = 480 + 22,
	3442	+ .vsync_end = 480 + 22 + 13,
	3443	+ .vtotal = 480 + 22 + 13 + 10,
	3444	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3445	+};
	3446	+
	3447	+static const struct panel_desc osddisplays_osd070t1718_19ts = {
	3448	+ .modes = &osddisplays_osd070t1718_19ts_mode,
	3449	+ .num_modes = 1,
	3450	+ .bpc = 8,
	3451	+ .size = {
	3452	+ .width = 152,
	3453	+ .height = 91,
	3454	+ },
2364	3455	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2365		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	3456	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3457	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3458	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3459	+};
	3460	+
	3461	+static const struct drm_display_mode pda_91_00156_a0_mode = {
	3462	+ .clock = 33300,
	3463	+ .hdisplay = 800,
	3464	+ .hsync_start = 800 + 1,
	3465	+ .hsync_end = 800 + 1 + 64,
	3466	+ .htotal = 800 + 1 + 64 + 64,
	3467	+ .vdisplay = 480,
	3468	+ .vsync_start = 480 + 1,
	3469	+ .vsync_end = 480 + 1 + 23,
	3470	+ .vtotal = 480 + 1 + 23 + 22,
	3471	+};
	3472	+
	3473	+static const struct panel_desc pda_91_00156_a0 = {
	3474	+ .modes = &pda_91_00156_a0_mode,
	3475	+ .num_modes = 1,
	3476	+ .size = {
	3477	+ .width = 152,
	3478	+ .height = 91,
	3479	+ },
	3480	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3481	+};
	3482	+
	3483	+static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
	3484	+ .clock = 24750,
	3485	+ .hdisplay = 800,
	3486	+ .hsync_start = 800 + 54,
	3487	+ .hsync_end = 800 + 54 + 2,
	3488	+ .htotal = 800 + 54 + 2 + 44,
	3489	+ .vdisplay = 480,
	3490	+ .vsync_start = 480 + 49,
	3491	+ .vsync_end = 480 + 49 + 2,
	3492	+ .vtotal = 480 + 49 + 2 + 22,
	3493	+};
	3494	+
	3495	+static const struct panel_desc powertip_ph800480t013_idf02 = {
	3496	+ .modes = &powertip_ph800480t013_idf02_mode,
	3497	+ .num_modes = 1,
	3498	+ .size = {
	3499	+ .width = 152,
	3500	+ .height = 91,
	3501	+ },
	3502	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \|
	3503	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3504	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
	3505	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3506	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2366	3507	};
2367	3508
2368	3509	static const struct drm_display_mode qd43003c0_40_mode = {
..	..	@@ -2375,7 +3516,6 @@
2375	3516	.vsync_start = 272 + 4,
2376	3517	.vsync_end = 272 + 4 + 10,
2377	3518	.vtotal = 272 + 4 + 10 + 2,
2378		- .vrefresh = 60,
2379	3519	};
2380	3520
2381	3521	static const struct panel_desc qd43003c0_40 = {
..	..	@@ -2419,6 +3559,34 @@
2419	3559	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2420	3560	};
2421	3561
	3562	+static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
	3563	+ .clock = 71100,
	3564	+ .hdisplay = 1280,
	3565	+ .hsync_start = 1280 + 48,
	3566	+ .hsync_end = 1280 + 48 + 32,
	3567	+ .htotal = 1280 + 48 + 32 + 80,
	3568	+ .vdisplay = 800,
	3569	+ .vsync_start = 800 + 2,
	3570	+ .vsync_end = 800 + 2 + 5,
	3571	+ .vtotal = 800 + 2 + 5 + 16,
	3572	+};
	3573	+
	3574	+static const struct panel_desc rocktech_rk101ii01d_ct = {
	3575	+ .modes = &rocktech_rk101ii01d_ct_mode,
	3576	+ .num_modes = 1,
	3577	+ .size = {
	3578	+ .width = 217,
	3579	+ .height = 136,
	3580	+ },
	3581	+ .delay = {
	3582	+ .prepare = 50,
	3583	+ .disable = 50,
	3584	+ },
	3585	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3586	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3587	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3588	+};
	3589	+
2422	3590	static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2423	3591	.clock = 271560,
2424	3592	.hdisplay = 2560,
..	..	@@ -2429,7 +3597,6 @@
2429	3597	.vsync_start = 1600 + 2,
2430	3598	.vsync_end = 1600 + 2 + 5,
2431	3599	.vtotal = 1600 + 2 + 5 + 57,
2432		- .vrefresh = 60,
2433	3600	};
2434	3601
2435	3602	static const struct panel_desc samsung_lsn122dl01_c01 = {
..	..	@@ -2451,7 +3618,6 @@
2451	3618	.vsync_start = 600 + 3,
2452	3619	.vsync_end = 600 + 3 + 6,
2453	3620	.vtotal = 600 + 3 + 6 + 61,
2454		- .vrefresh = 60,
2455	3621	};
2456	3622
2457	3623	static const struct panel_desc samsung_ltn101nt05 = {
..	..	@@ -2462,6 +3628,9 @@
2462	3628	.width = 223,
2463	3629	.height = 125,
2464	3630	},
	3631	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	3632	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3633	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2465	3634	};
2466	3635
2467	3636	static const struct drm_display_mode samsung_ltn140at29_301_mode = {
..	..	@@ -2474,7 +3643,6 @@
2474	3643	.vsync_start = 768 + 2,
2475	3644	.vsync_end = 768 + 2 + 5,
2476	3645	.vtotal = 768 + 2 + 5 + 17,
2477		- .vrefresh = 60,
2478	3646	};
2479	3647
2480	3648	static const struct panel_desc samsung_ltn140at29_301 = {
..	..	@@ -2487,6 +3655,81 @@
2487	3655	},
2488	3656	};
2489	3657
	3658	+static const struct display_timing satoz_sat050at40h12r2_timing = {
	3659	+ .pixelclock = {33300000, 33300000, 50000000},
	3660	+ .hactive = {800, 800, 800},
	3661	+ .hfront_porch = {16, 210, 354},
	3662	+ .hback_porch = {46, 46, 46},
	3663	+ .hsync_len = {1, 1, 40},
	3664	+ .vactive = {480, 480, 480},
	3665	+ .vfront_porch = {7, 22, 147},
	3666	+ .vback_porch = {23, 23, 23},
	3667	+ .vsync_len = {1, 1, 20},
	3668	+};
	3669	+
	3670	+static const struct panel_desc satoz_sat050at40h12r2 = {
	3671	+ .timings = &satoz_sat050at40h12r2_timing,
	3672	+ .num_timings = 1,
	3673	+ .bpc = 8,
	3674	+ .size = {
	3675	+ .width = 108,
	3676	+ .height = 65,
	3677	+ },
	3678	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3679	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3680	+};
	3681	+
	3682	+static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
	3683	+ .clock = 168480,
	3684	+ .hdisplay = 1920,
	3685	+ .hsync_start = 1920 + 48,
	3686	+ .hsync_end = 1920 + 48 + 32,
	3687	+ .htotal = 1920 + 48 + 32 + 80,
	3688	+ .vdisplay = 1280,
	3689	+ .vsync_start = 1280 + 3,
	3690	+ .vsync_end = 1280 + 3 + 10,
	3691	+ .vtotal = 1280 + 3 + 10 + 57,
	3692	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3693	+};
	3694	+
	3695	+static const struct panel_desc sharp_ld_d5116z01b = {
	3696	+ .modes = &sharp_ld_d5116z01b_mode,
	3697	+ .num_modes = 1,
	3698	+ .bpc = 8,
	3699	+ .size = {
	3700	+ .width = 260,
	3701	+ .height = 120,
	3702	+ },
	3703	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3704	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	3705	+};
	3706	+
	3707	+static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
	3708	+ .clock = 33260,
	3709	+ .hdisplay = 800,
	3710	+ .hsync_start = 800 + 64,
	3711	+ .hsync_end = 800 + 64 + 128,
	3712	+ .htotal = 800 + 64 + 128 + 64,
	3713	+ .vdisplay = 480,
	3714	+ .vsync_start = 480 + 8,
	3715	+ .vsync_end = 480 + 8 + 2,
	3716	+ .vtotal = 480 + 8 + 2 + 35,
	3717	+ .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
	3718	+};
	3719	+
	3720	+static const struct panel_desc sharp_lq070y3dg3b = {
	3721	+ .modes = &sharp_lq070y3dg3b_mode,
	3722	+ .num_modes = 1,
	3723	+ .bpc = 8,
	3724	+ .size = {
	3725	+ .width = 152, /* 152.4mm */
	3726	+ .height = 91, /* 91.4mm */
	3727	+ },
	3728	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3729	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3730	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3731	+};
	3732	+
2490	3733	static const struct drm_display_mode sharp_lq035q7db03_mode = {
2491	3734	.clock = 5500,
2492	3735	.hdisplay = 240,
..	..	@@ -2497,7 +3740,6 @@
2497	3740	.vsync_start = 320 + 9,
2498	3741	.vsync_end = 320 + 9 + 1,
2499	3742	.vtotal = 320 + 9 + 1 + 7,
2500		- .vrefresh = 60,
2501	3743	};
2502	3744
2503	3745	static const struct panel_desc sharp_lq035q7db03 = {
..	..	@@ -2533,6 +3775,7 @@
2533	3775	.height = 136,
2534	3776	},
2535	3777	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	3778	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2536	3779	};
2537	3780
2538	3781	static const struct display_timing sharp_lq123p1jx31_timing = {
..	..	@@ -2563,28 +3806,45 @@
2563	3806	},
2564	3807	};
2565	3808
2566		-static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2567		- .clock = 71100,
2568		- .hdisplay = 1024,
2569		- .hsync_start = 1024 + 168,
2570		- .hsync_end = 1024 + 168 + 64,
2571		- .htotal = 1024 + 168 + 64 + 88,
2572		- .vdisplay = 768,
2573		- .vsync_start = 768 + 37,
2574		- .vsync_end = 768 + 37 + 2,
2575		- .vtotal = 768 + 37 + 2 + 8,
2576		- .vrefresh = 60,
	3809	+static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
	3810	+ { /* 50 Hz */
	3811	+ .clock = 3000,
	3812	+ .hdisplay = 240,
	3813	+ .hsync_start = 240 + 58,
	3814	+ .hsync_end = 240 + 58 + 1,
	3815	+ .htotal = 240 + 58 + 1 + 1,
	3816	+ .vdisplay = 160,
	3817	+ .vsync_start = 160 + 24,
	3818	+ .vsync_end = 160 + 24 + 10,
	3819	+ .vtotal = 160 + 24 + 10 + 6,
	3820	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3821	+ },
	3822	+ { /* 60 Hz */
	3823	+ .clock = 3000,
	3824	+ .hdisplay = 240,
	3825	+ .hsync_start = 240 + 8,
	3826	+ .hsync_end = 240 + 8 + 1,
	3827	+ .htotal = 240 + 8 + 1 + 1,
	3828	+ .vdisplay = 160,
	3829	+ .vsync_start = 160 + 24,
	3830	+ .vsync_end = 160 + 24 + 10,
	3831	+ .vtotal = 160 + 24 + 10 + 6,
	3832	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3833	+ },
2577	3834	};
2578	3835
2579		-static const struct panel_desc sharp_lq150x1lg11 = {
2580		- .modes = &sharp_lq150x1lg11_mode,
2581		- .num_modes = 1,
	3836	+static const struct panel_desc sharp_ls020b1dd01d = {
	3837	+ .modes = sharp_ls020b1dd01d_modes,
	3838	+ .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
2582	3839	.bpc = 6,
2583	3840	.size = {
2584		- .width = 304,
2585		- .height = 228,
	3841	+ .width = 42,
	3842	+ .height = 28,
2586	3843	},
2587	3844	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
	3845	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH
	3846	+ \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
	3847	+ \| DRM_BUS_FLAG_SHARP_SIGNALS,
2588	3848	};
2589	3849
2590	3850	static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
..	..	@@ -2597,7 +3857,6 @@
2597	3857	.vsync_start = 480 + 1,
2598	3858	.vsync_end = 480 + 1 + 23,
2599	3859	.vtotal = 480 + 1 + 23 + 22,
2600		- .vrefresh = 60,
2601	3860	};
2602	3861
2603	3862	static const struct panel_desc shelly_sca07010_bfn_lnn = {
..	..	@@ -2610,6 +3869,31 @@
2610	3869	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2611	3870	};
2612	3871
	3872	+static const struct drm_display_mode starry_kr070pe2t_mode = {
	3873	+ .clock = 33000,
	3874	+ .hdisplay = 800,
	3875	+ .hsync_start = 800 + 209,
	3876	+ .hsync_end = 800 + 209 + 1,
	3877	+ .htotal = 800 + 209 + 1 + 45,
	3878	+ .vdisplay = 480,
	3879	+ .vsync_start = 480 + 22,
	3880	+ .vsync_end = 480 + 22 + 1,
	3881	+ .vtotal = 480 + 22 + 1 + 22,
	3882	+};
	3883	+
	3884	+static const struct panel_desc starry_kr070pe2t = {
	3885	+ .modes = &starry_kr070pe2t_mode,
	3886	+ .num_modes = 1,
	3887	+ .bpc = 8,
	3888	+ .size = {
	3889	+ .width = 152,
	3890	+ .height = 86,
	3891	+ },
	3892	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3893	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
	3894	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3895	+};
	3896	+
2613	3897	static const struct drm_display_mode starry_kr122ea0sra_mode = {
2614	3898	.clock = 147000,
2615	3899	.hdisplay = 1920,
..	..	@@ -2620,7 +3904,6 @@
2620	3904	.vsync_start = 1200 + 15,
2621	3905	.vsync_end = 1200 + 15 + 2,
2622	3906	.vtotal = 1200 + 15 + 2 + 18,
2623		- .vrefresh = 60,
2624	3907	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2625	3908	};
2626	3909
..	..	@@ -2636,6 +3919,30 @@
2636	3919	.enable = 50,
2637	3920	.unprepare = 10 + 500,
2638	3921	},
	3922	+};
	3923	+
	3924	+static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
	3925	+ .clock = 30000,
	3926	+ .hdisplay = 800,
	3927	+ .hsync_start = 800 + 39,
	3928	+ .hsync_end = 800 + 39 + 47,
	3929	+ .htotal = 800 + 39 + 47 + 39,
	3930	+ .vdisplay = 480,
	3931	+ .vsync_start = 480 + 13,
	3932	+ .vsync_end = 480 + 13 + 2,
	3933	+ .vtotal = 480 + 13 + 2 + 29,
	3934	+};
	3935	+
	3936	+static const struct panel_desc tfc_s9700rtwv43tr_01b = {
	3937	+ .modes = &tfc_s9700rtwv43tr_01b_mode,
	3938	+ .num_modes = 1,
	3939	+ .bpc = 8,
	3940	+ .size = {
	3941	+ .width = 155,
	3942	+ .height = 90,
	3943	+ },
	3944	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3945	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2639	3946	};
2640	3947
2641	3948	static const struct display_timing tianma_tm070jdhg30_timing = {
..	..	@@ -2660,6 +3967,19 @@
2660	3967	.height = 95,
2661	3968	},
2662	3969	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3970	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3971	+};
	3972	+
	3973	+static const struct panel_desc tianma_tm070jvhg33 = {
	3974	+ .timings = &tianma_tm070jdhg30_timing,
	3975	+ .num_timings = 1,
	3976	+ .bpc = 8,
	3977	+ .size = {
	3978	+ .width = 150,
	3979	+ .height = 94,
	3980	+ },
	3981	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3982	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2663	3983	};
2664	3984
2665	3985	static const struct display_timing tianma_tm070rvhg71_timing = {
..	..	@@ -2684,6 +4004,63 @@
2684	4004	.height = 86,
2685	4005	},
2686	4006	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	4007	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	4008	+};
	4009	+
	4010	+static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
	4011	+ {
	4012	+ .clock = 10000,
	4013	+ .hdisplay = 320,
	4014	+ .hsync_start = 320 + 50,
	4015	+ .hsync_end = 320 + 50 + 6,
	4016	+ .htotal = 320 + 50 + 6 + 38,
	4017	+ .vdisplay = 240,
	4018	+ .vsync_start = 240 + 3,
	4019	+ .vsync_end = 240 + 3 + 1,
	4020	+ .vtotal = 240 + 3 + 1 + 17,
	4021	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	4022	+ },
	4023	+};
	4024	+
	4025	+static const struct panel_desc ti_nspire_cx_lcd_panel = {
	4026	+ .modes = ti_nspire_cx_lcd_mode,
	4027	+ .num_modes = 1,
	4028	+ .bpc = 8,
	4029	+ .size = {
	4030	+ .width = 65,
	4031	+ .height = 49,
	4032	+ },
	4033	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4034	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
	4035	+};
	4036	+
	4037	+static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
	4038	+ {
	4039	+ .clock = 10000,
	4040	+ .hdisplay = 320,
	4041	+ .hsync_start = 320 + 6,
	4042	+ .hsync_end = 320 + 6 + 6,
	4043	+ .htotal = 320 + 6 + 6 + 6,
	4044	+ .vdisplay = 240,
	4045	+ .vsync_start = 240 + 0,
	4046	+ .vsync_end = 240 + 0 + 1,
	4047	+ .vtotal = 240 + 0 + 1 + 0,
	4048	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	4049	+ },
	4050	+};
	4051	+
	4052	+static const struct panel_desc ti_nspire_classic_lcd_panel = {
	4053	+ .modes = ti_nspire_classic_lcd_mode,
	4054	+ .num_modes = 1,
	4055	+ /* The grayscale panel has 8 bit for the color .. Y (black) */
	4056	+ .bpc = 8,
	4057	+ .size = {
	4058	+ .width = 71,
	4059	+ .height = 53,
	4060	+ },
	4061	+ /* This is the grayscale bus format */
	4062	+ .bus_format = MEDIA_BUS_FMT_Y8_1X8,
	4063	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2687	4064	};
2688	4065
2689	4066	static const struct drm_display_mode toshiba_lt089ac29000_mode = {
..	..	@@ -2696,7 +4073,6 @@
2696	4073	.vsync_start = 768 + 20,
2697	4074	.vsync_end = 768 + 20 + 7,
2698	4075	.vtotal = 768 + 20 + 7 + 3,
2699		- .vrefresh = 60,
2700	4076	};
2701	4077
2702	4078	static const struct panel_desc toshiba_lt089ac29000 = {
..	..	@@ -2706,8 +4082,9 @@
2706	4082	.width = 194,
2707	4083	.height = 116,
2708	4084	},
2709		- .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2710		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	4085	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	4086	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	4087	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2711	4088	};
2712	4089
2713	4090	static const struct drm_display_mode tpk_f07a_0102_mode = {
..	..	@@ -2720,7 +4097,6 @@
2720	4097	.vsync_start = 480 + 10,
2721	4098	.vsync_end = 480 + 10 + 2,
2722	4099	.vtotal = 480 + 10 + 2 + 33,
2723		- .vrefresh = 60,
2724	4100	};
2725	4101
2726	4102	static const struct panel_desc tpk_f07a_0102 = {
..	..	@@ -2730,7 +4106,7 @@
2730	4106	.width = 152,
2731	4107	.height = 91,
2732	4108	},
2733		- .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
	4109	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2734	4110	};
2735	4111
2736	4112	static const struct drm_display_mode tpk_f10a_0102_mode = {
..	..	@@ -2743,7 +4119,6 @@
2743	4119	.vsync_start = 600 + 20,
2744	4120	.vsync_end = 600 + 20 + 5,
2745	4121	.vtotal = 600 + 20 + 5 + 25,
2746		- .vrefresh = 60,
2747	4122	};
2748	4123
2749	4124	static const struct panel_desc tpk_f10a_0102 = {
..	..	@@ -2778,6 +4153,7 @@
2778	4153	.height = 91,
2779	4154	},
2780	4155	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	4156	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2781	4157	};
2782	4158
2783	4159	static const struct panel_desc urt_umsh_8596md_parallel = {
..	..	@@ -2791,6 +4167,31 @@
2791	4167	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2792	4168	};
2793	4169
	4170	+static const struct drm_display_mode vl050_8048nt_c01_mode = {
	4171	+ .clock = 33333,
	4172	+ .hdisplay = 800,
	4173	+ .hsync_start = 800 + 210,
	4174	+ .hsync_end = 800 + 210 + 20,
	4175	+ .htotal = 800 + 210 + 20 + 46,
	4176	+ .vdisplay = 480,
	4177	+ .vsync_start = 480 + 22,
	4178	+ .vsync_end = 480 + 22 + 10,
	4179	+ .vtotal = 480 + 22 + 10 + 23,
	4180	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	4181	+};
	4182	+
	4183	+static const struct panel_desc vl050_8048nt_c01 = {
	4184	+ .modes = &vl050_8048nt_c01_mode,
	4185	+ .num_modes = 1,
	4186	+ .bpc = 8,
	4187	+ .size = {
	4188	+ .width = 120,
	4189	+ .height = 76,
	4190	+ },
	4191	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4192	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	4193	+};
	4194	+
2794	4195	static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2795	4196	.clock = 6410,
2796	4197	.hdisplay = 320,
..	..	@@ -2801,7 +4202,6 @@
2801	4202	.vsync_start = 240 + 4,
2802	4203	.vsync_end = 240 + 4 + 3,
2803	4204	.vtotal = 240 + 4 + 3 + 15,
2804		- .vrefresh = 60,
2805	4205	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2806	4206	};
2807	4207
..	..	@@ -2816,17 +4216,48 @@
2816	4216	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2817	4217	};
2818	4218
	4219	+static const struct drm_display_mode arm_rtsm_mode[] = {
	4220	+ {
	4221	+ .clock = 65000,
	4222	+ .hdisplay = 1024,
	4223	+ .hsync_start = 1024 + 24,
	4224	+ .hsync_end = 1024 + 24 + 136,
	4225	+ .htotal = 1024 + 24 + 136 + 160,
	4226	+ .vdisplay = 768,
	4227	+ .vsync_start = 768 + 3,
	4228	+ .vsync_end = 768 + 3 + 6,
	4229	+ .vtotal = 768 + 3 + 6 + 29,
	4230	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	4231	+ },
	4232	+};
	4233	+
	4234	+static const struct panel_desc arm_rtsm = {
	4235	+ .modes = arm_rtsm_mode,
	4236	+ .num_modes = 1,
	4237	+ .bpc = 8,
	4238	+ .size = {
	4239	+ .width = 400,
	4240	+ .height = 300,
	4241	+ },
	4242	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4243	+};
	4244	+
2819	4245	static const struct of_device_id platform_of_match[] = {
2820	4246	{
2821	4247	.compatible = "simple-panel",
2822	4248	.data = NULL,
2823		-#ifndef CONFIG_DRM_PANEL_SIMPLE_OF_ONLY
	4249	+ }, {
	4250	+ .compatible = "ampire,am-1280800n3tzqw-t00h",
	4251	+ .data = &ampire_am_1280800n3tzqw_t00h,
2824	4252	}, {
2825	4253	.compatible = "ampire,am-480272h3tmqw-t01h",
2826	4254	.data = &ampire_am_480272h3tmqw_t01h,
2827	4255	}, {
2828	4256	.compatible = "ampire,am800480r3tmqwa1h",
2829	4257	.data = &ampire_am800480r3tmqwa1h,
	4258	+ }, {
	4259	+ .compatible = "arm,rtsm-display",
	4260	+ .data = &arm_rtsm,
2830	4261	}, {
2831	4262	.compatible = "armadeus,st0700-adapt",
2832	4263	.data = &armadeus_st0700_adapt,
..	..	@@ -2840,6 +4271,9 @@
2840	4271	.compatible = "auo,b101xtn01",
2841	4272	.data = &auo_b101xtn01,
2842	4273	}, {
	4274	+ .compatible = "auo,b116xa01",
	4275	+ .data = &auo_b116xak01,
	4276	+ }, {
2843	4277	.compatible = "auo,b116xw03",
2844	4278	.data = &auo_b116xw03,
2845	4279	}, {
..	..	@@ -2852,14 +4286,26 @@
2852	4286	.compatible = "auo,g070vvn01",
2853	4287	.data = &auo_g070vvn01,
2854	4288	}, {
	4289	+ .compatible = "auo,g101evn010",
	4290	+ .data = &auo_g101evn010,
	4291	+ }, {
2855	4292	.compatible = "auo,g104sn02",
2856	4293	.data = &auo_g104sn02,
	4294	+ }, {
	4295	+ .compatible = "auo,g121ean01",
	4296	+ .data = &auo_g121ean01,
2857	4297	}, {
2858	4298	.compatible = "auo,g133han01",
2859	4299	.data = &auo_g133han01,
2860	4300	}, {
	4301	+ .compatible = "auo,g156xtn01",
	4302	+ .data = &auo_g156xtn01,
	4303	+ }, {
2861	4304	.compatible = "auo,g185han01",
2862	4305	.data = &auo_g185han01,
	4306	+ }, {
	4307	+ .compatible = "auo,g190ean01",
	4308	+ .data = &auo_g190ean01,
2863	4309	}, {
2864	4310	.compatible = "auo,p320hvn03",
2865	4311	.data = &auo_p320hvn03,
..	..	@@ -2870,11 +4316,38 @@
2870	4316	.compatible = "avic,tm070ddh03",
2871	4317	.data = &avic_tm070ddh03,
2872	4318	}, {
	4319	+ .compatible = "bananapi,s070wv20-ct16",
	4320	+ .data = &bananapi_s070wv20_ct16,
	4321	+ }, {
2873	4322	.compatible = "boe,hv070wsa-100",
2874	4323	.data = &boe_hv070wsa
2875	4324	}, {
2876	4325	.compatible = "boe,nv101wxmn51",
2877	4326	.data = &boe_nv101wxmn51,
	4327	+ }, {
	4328	+ .compatible = "boe,nv133fhm-n61",
	4329	+ .data = &boe_nv133fhm_n61,
	4330	+ }, {
	4331	+ .compatible = "boe,nv133fhm-n62",
	4332	+ .data = &boe_nv133fhm_n61,
	4333	+ }, {
	4334	+ .compatible = "boe,nv140fhmn49",
	4335	+ .data = &boe_nv140fhmn49,
	4336	+ }, {
	4337	+ .compatible = "cdtech,s043wq26h-ct7",
	4338	+ .data = &cdtech_s043wq26h_ct7,
	4339	+ }, {
	4340	+ .compatible = "cdtech,s070pws19hp-fc21",
	4341	+ .data = &cdtech_s070pws19hp_fc21,
	4342	+ }, {
	4343	+ .compatible = "cdtech,s070swv29hg-dc44",
	4344	+ .data = &cdtech_s070swv29hg_dc44,
	4345	+ }, {
	4346	+ .compatible = "cdtech,s070wv95-ct16",
	4347	+ .data = &cdtech_s070wv95_ct16,
	4348	+ }, {
	4349	+ .compatible = "chefree,ch101olhlwh-002",
	4350	+ .data = &chefree_ch101olhlwh_002,
2878	4351	}, {
2879	4352	.compatible = "chunghwa,claa070wp03xg",
2880	4353	.data = &chunghwa_claa070wp03xg,
..	..	@@ -2891,6 +4364,18 @@
2891	4364	.compatible = "dlc,dlc0700yzg-1",
2892	4365	.data = &dlc_dlc0700yzg_1,
2893	4366	}, {
	4367	+ .compatible = "dlc,dlc1010gig",
	4368	+ .data = &dlc_dlc1010gig,
	4369	+ }, {
	4370	+ .compatible = "edt,et035012dm6",
	4371	+ .data = &edt_et035012dm6,
	4372	+ }, {
	4373	+ .compatible = "edt,etm043080dh6gp",
	4374	+ .data = &edt_etm043080dh6gp,
	4375	+ }, {
	4376	+ .compatible = "edt,etm0430g0dh6",
	4377	+ .data = &edt_etm0430g0dh6,
	4378	+ }, {
2894	4379	.compatible = "edt,et057090dhu",
2895	4380	.data = &edt_et057090dhu,
2896	4381	}, {
..	..	@@ -2906,11 +4391,23 @@
2906	4391	.compatible = "edt,etm0700g0edh6",
2907	4392	.data = &edt_etm0700g0bdh6,
2908	4393	}, {
	4394	+ .compatible = "evervision,vgg804821",
	4395	+ .data = &evervision_vgg804821,
	4396	+ }, {
2909	4397	.compatible = "foxlink,fl500wvr00-a0t",
2910	4398	.data = &foxlink_fl500wvr00_a0t,
2911	4399	}, {
	4400	+ .compatible = "frida,frd350h54004",
	4401	+ .data = &frida_frd350h54004,
	4402	+ }, {
	4403	+ .compatible = "friendlyarm,hd702e",
	4404	+ .data = &friendlyarm_hd702e,
	4405	+ }, {
2912	4406	.compatible = "giantplus,gpg482739qs5",
2913	4407	.data = &giantplus_gpg482739qs5
	4408	+ }, {
	4409	+ .compatible = "giantplus,gpm940b0",
	4410	+ .data = &giantplus_gpm940b0,
2914	4411	}, {
2915	4412	.compatible = "hannstar,hsd070pww1",
2916	4413	.data = &hannstar_hsd070pww1,
..	..	@@ -2945,17 +4442,32 @@
2945	4442	.compatible = "innolux,n156bge-l21",
2946	4443	.data = &innolux_n156bge_l21,
2947	4444	}, {
2948		- .compatible = "innolux,tv123wam",
2949		- .data = &innolux_tv123wam,
	4445	+ .compatible = "innolux,p120zdg-bf1",
	4446	+ .data = &innolux_p120zdg_bf1,
2950	4447	}, {
2951	4448	.compatible = "innolux,zj070na-01p",
2952	4449	.data = &innolux_zj070na_01p,
	4450	+ }, {
	4451	+ .compatible = "ivo,m133nwf4-r0",
	4452	+ .data = &ivo_m133nwf4_r0,
	4453	+ }, {
	4454	+ .compatible = "kingdisplay,kd116n21-30nv-a010",
	4455	+ .data = &kingdisplay_kd116n21_30nv_a010,
	4456	+ }, {
	4457	+ .compatible = "koe,tx14d24vm1bpa",
	4458	+ .data = &koe_tx14d24vm1bpa,
	4459	+ }, {
	4460	+ .compatible = "koe,tx26d202vm0bwa",
	4461	+ .data = &koe_tx26d202vm0bwa,
2953	4462	}, {
2954	4463	.compatible = "koe,tx31d200vm0baa",
2955	4464	.data = &koe_tx31d200vm0baa,
2956	4465	}, {
2957	4466	.compatible = "kyo,tcg121xglp",
2958	4467	.data = &kyo_tcg121xglp,
	4468	+ }, {
	4469	+ .compatible = "lemaker,bl035-rgb-002",
	4470	+ .data = &lemaker_bl035_rgb_002,
2959	4471	}, {
2960	4472	.compatible = "lg,lb070wv8",
2961	4473	.data = &lg_lb070wv8,
..	..	@@ -2972,6 +4484,18 @@
2972	4484	.compatible = "lg,lp129qe",
2973	4485	.data = &lg_lp129qe,
2974	4486	}, {
	4487	+ .compatible = "logicpd,type28",
	4488	+ .data = &logicpd_type_28,
	4489	+ }, {
	4490	+ .compatible = "logictechno,lt161010-2nhc",
	4491	+ .data = &logictechno_lt161010_2nh,
	4492	+ }, {
	4493	+ .compatible = "logictechno,lt161010-2nhr",
	4494	+ .data = &logictechno_lt161010_2nh,
	4495	+ }, {
	4496	+ .compatible = "logictechno,lt170410-2whc",
	4497	+ .data = &logictechno_lt170410_2whc,
	4498	+ }, {
2975	4499	.compatible = "mitsubishi,aa070mc01-ca1",
2976	4500	.data = &mitsubishi_aa070mc01,
2977	4501	}, {
..	..	@@ -2983,6 +4507,9 @@
2983	4507	}, {
2984	4508	.compatible = "netron-dy,e231732",
2985	4509	.data = &netron_dy_e231732,
	4510	+ }, {
	4511	+ .compatible = "neweast,wjfh116008a",
	4512	+ .data = &neweast_wjfh116008a,
2986	4513	}, {
2987	4514	.compatible = "newhaven,nhd-4.3-480272ef-atxl",
2988	4515	.data = &newhaven_nhd_43_480272ef_atxl,
..	..	@@ -3002,14 +4529,32 @@
3002	4529	.compatible = "ontat,yx700wv03",
3003	4530	.data = &ontat_yx700wv03,
3004	4531	}, {
	4532	+ .compatible = "ortustech,com37h3m05dtc",
	4533	+ .data = &ortustech_com37h3m,
	4534	+ }, {
	4535	+ .compatible = "ortustech,com37h3m99dtc",
	4536	+ .data = &ortustech_com37h3m,
	4537	+ }, {
3005	4538	.compatible = "ortustech,com43h4m85ulc",
3006	4539	.data = &ortustech_com43h4m85ulc,
	4540	+ }, {
	4541	+ .compatible = "osddisplays,osd070t1718-19ts",
	4542	+ .data = &osddisplays_osd070t1718_19ts,
	4543	+ }, {
	4544	+ .compatible = "pda,91-00156-a0",
	4545	+ .data = &pda_91_00156_a0,
	4546	+ }, {
	4547	+ .compatible = "powertip,ph800480t013-idf02",
	4548	+ .data = &powertip_ph800480t013_idf02,
3007	4549	}, {
3008	4550	.compatible = "qiaodian,qd43003c0-40",
3009	4551	.data = &qd43003c0_40,
3010	4552	}, {
3011	4553	.compatible = "rocktech,rk070er9427",
3012	4554	.data = &rocktech_rk070er9427,
	4555	+ }, {
	4556	+ .compatible = "rocktech,rk101ii01d-ct",
	4557	+ .data = &rocktech_rk101ii01d_ct,
3013	4558	}, {
3014	4559	.compatible = "samsung,lsn122dl01-c01",
3015	4560	.data = &samsung_lsn122dl01_c01,
..	..	@@ -3020,8 +4565,17 @@
3020	4565	.compatible = "samsung,ltn140at29-301",
3021	4566	.data = &samsung_ltn140at29_301,
3022	4567	}, {
	4568	+ .compatible = "satoz,sat050at40h12r2",
	4569	+ .data = &satoz_sat050at40h12r2,
	4570	+ }, {
	4571	+ .compatible = "sharp,ld-d5116z01b",
	4572	+ .data = &sharp_ld_d5116z01b,
	4573	+ }, {
3023	4574	.compatible = "sharp,lq035q7db03",
3024	4575	.data = &sharp_lq035q7db03,
	4576	+ }, {
	4577	+ .compatible = "sharp,lq070y3dg3b",
	4578	+ .data = &sharp_lq070y3dg3b,
3025	4579	}, {
3026	4580	.compatible = "sharp,lq101k1ly04",
3027	4581	.data = &sharp_lq101k1ly04,
..	..	@@ -3029,20 +4583,35 @@
3029	4583	.compatible = "sharp,lq123p1jx31",
3030	4584	.data = &sharp_lq123p1jx31,
3031	4585	}, {
3032		- .compatible = "sharp,lq150x1lg11",
3033		- .data = &sharp_lq150x1lg11,
	4586	+ .compatible = "sharp,ls020b1dd01d",
	4587	+ .data = &sharp_ls020b1dd01d,
3034	4588	}, {
3035	4589	.compatible = "shelly,sca07010-bfn-lnn",
3036	4590	.data = &shelly_sca07010_bfn_lnn,
3037	4591	}, {
	4592	+ .compatible = "starry,kr070pe2t",
	4593	+ .data = &starry_kr070pe2t,
	4594	+ }, {
3038	4595	.compatible = "starry,kr122ea0sra",
3039	4596	.data = &starry_kr122ea0sra,
	4597	+ }, {
	4598	+ .compatible = "tfc,s9700rtwv43tr-01b",
	4599	+ .data = &tfc_s9700rtwv43tr_01b,
3040	4600	}, {
3041	4601	.compatible = "tianma,tm070jdhg30",
3042	4602	.data = &tianma_tm070jdhg30,
3043	4603	}, {
	4604	+ .compatible = "tianma,tm070jvhg33",
	4605	+ .data = &tianma_tm070jvhg33,
	4606	+ }, {
3044	4607	.compatible = "tianma,tm070rvhg71",
3045	4608	.data = &tianma_tm070rvhg71,
	4609	+ }, {
	4610	+ .compatible = "ti,nspire-cx-lcd-panel",
	4611	+ .data = &ti_nspire_cx_lcd_panel,
	4612	+ }, {
	4613	+ .compatible = "ti,nspire-classic-lcd-panel",
	4614	+ .data = &ti_nspire_classic_lcd_panel,
3046	4615	}, {
3047	4616	.compatible = "toshiba,lt089ac29000",
3048	4617	.data = &toshiba_lt089ac29000,
..	..	@@ -3071,35 +4640,74 @@
3071	4640	.compatible = "urt,umsh-8596md-20t",
3072	4641	.data = &urt_umsh_8596md_parallel,
3073	4642	}, {
	4643	+ .compatible = "vxt,vl050-8048nt-c01",
	4644	+ .data = &vl050_8048nt_c01,
	4645	+ }, {
3074	4646	.compatible = "winstar,wf35ltiacd",
3075	4647	.data = &winstar_wf35ltiacd,
3076		-#endif /* !CONFIG_DRM_PANEL_SIMPLE_OF_ONLY */
	4648	+ }, {
	4649	+ /* Must be the last entry */
	4650	+ .compatible = "panel-dpi",
	4651	+ .data = &panel_dpi,
3077	4652	}, {
3078	4653	/* sentinel */
3079	4654	}
3080	4655	};
3081	4656	MODULE_DEVICE_TABLE(of, platform_of_match);
3082	4657
	4658	+static bool of_child_node_is_present(const struct device_node *node,
	4659	+ const char *name)
	4660	+{
	4661	+ struct device_node *child;
	4662	+
	4663	+ child = of_get_child_by_name(node, name);
	4664	+ of_node_put(child);
	4665	+
	4666	+ return !!child;
	4667	+}
	4668	+
3083	4669	static int panel_simple_of_get_desc_data(struct device *dev,
3084	4670	struct panel_desc *desc)
3085	4671	{
3086	4672	struct device_node *np = dev->of_node;
3087		- struct drm_display_mode *mode;
3088	4673	u32 bus_flags;
3089	4674	const void *data;
3090	4675	int len;
3091	4676	int err;
3092	4677
3093		- mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
3094		- if (!mode)
3095		- return -ENOMEM;
	4678	+ if (of_child_node_is_present(np, "display-timings")) {
	4679	+ struct drm_display_mode *mode;
3096	4680
3097		- err = of_get_drm_display_mode(np, mode, &bus_flags, OF_USE_NATIVE_MODE);
3098		- if (!err) {
3099		- desc->modes = mode;
3100		- desc->num_modes = 1;
3101		- desc->bus_flags = bus_flags;
	4681	+ mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
	4682	+ if (!mode)
	4683	+ return -ENOMEM;
3102	4684
	4685	+ if (!of_get_drm_display_mode(np, mode, &bus_flags,
	4686	+ OF_USE_NATIVE_MODE)) {
	4687	+ desc->modes = mode;
	4688	+ desc->num_modes = 1;
	4689	+ desc->bus_flags = bus_flags;
	4690	+ }
	4691	+ } else if (of_child_node_is_present(np, "panel-timing")) {
	4692	+ struct display_timing *timing;
	4693	+ struct videomode vm;
	4694	+
	4695	+ timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
	4696	+ if (!timing)
	4697	+ return -ENOMEM;
	4698	+
	4699	+ if (!of_get_display_timing(np, "panel-timing", timing)) {
	4700	+ desc->timings = timing;
	4701	+ desc->num_timings = 1;
	4702	+
	4703	+ bus_flags = 0;
	4704	+ vm.flags = timing->flags;
	4705	+ drm_bus_flags_from_videomode(&vm, &bus_flags);
	4706	+ desc->bus_flags = bus_flags;
	4707	+ }
	4708	+ }
	4709	+
	4710	+ if (desc->num_modes \|\| desc->num_timings) {
3103	4711	of_property_read_u32(np, "bpc", &desc->bpc);
3104	4712	of_property_read_u32(np, "bus-format", &desc->bus_format);
3105	4713	of_property_read_u32(np, "width-mm", &desc->size.width);
..	..	@@ -3213,7 +4821,6 @@
3213	4821	.vsync_start = 1920 + 9,
3214	4822	.vsync_end = 1920 + 9 + 2,
3215	4823	.vtotal = 1920 + 9 + 2 + 8,
3216		- .vrefresh = 60,
3217	4824	};
3218	4825
3219	4826	static const struct panel_desc_dsi auo_b080uan01 = {
..	..	@@ -3225,6 +4832,7 @@
3225	4832	.width = 108,
3226	4833	.height = 272,
3227	4834	},
	4835	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3228	4836	},
3229	4837	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_CLOCK_NON_CONTINUOUS,
3230	4838	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3241,7 +4849,6 @@
3241	4849	.vsync_start = 1920 + 21,
3242	4850	.vsync_end = 1920 + 21 + 3,
3243	4851	.vtotal = 1920 + 21 + 3 + 18,
3244		- .vrefresh = 60,
3245	4852	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
3246	4853	};
3247	4854
..	..	@@ -3253,6 +4860,7 @@
3253	4860	.width = 107,
3254	4861	.height = 172,
3255	4862	},
	4863	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3256	4864	},
3257	4865	.flags = MIPI_DSI_MODE_VIDEO \|
3258	4866	MIPI_DSI_MODE_VIDEO_BURST \|
..	..	@@ -3271,7 +4879,6 @@
3271	4879	.vsync_start = 1280 + 28,
3272	4880	.vsync_end = 1280 + 28 + 1,
3273	4881	.vtotal = 1280 + 28 + 1 + 14,
3274		- .vrefresh = 60,
3275	4882	};
3276	4883
3277	4884	static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
..	..	@@ -3283,6 +4890,7 @@
3283	4890	.width = 94,
3284	4891	.height = 151,
3285	4892	},
	4893	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3286	4894	},
3287	4895	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_CLOCK_NON_CONTINUOUS,
3288	4896	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3299,7 +4907,6 @@
3299	4907	.vsync_start = 1280 + 8,
3300	4908	.vsync_end = 1280 + 8 + 4,
3301	4909	.vtotal = 1280 + 8 + 4 + 12,
3302		- .vrefresh = 60,
3303	4910	};
3304	4911
3305	4912	static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
..	..	@@ -3311,6 +4918,7 @@
3311	4918	.width = 62,
3312	4919	.height = 110,
3313	4920	},
	4921	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3314	4922	},
3315	4923	.flags = MIPI_DSI_MODE_VIDEO,
3316	4924	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3327,7 +4935,6 @@
3327	4935	.vsync_start = 1200 + 17,
3328	4936	.vsync_end = 1200 + 17 + 2,
3329	4937	.vtotal = 1200 + 17 + 2 + 16,
3330		- .vrefresh = 60,
3331	4938	};
3332	4939
3333	4940	static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
..	..	@@ -3339,9 +4946,69 @@
3339	4946	.width = 217,
3340	4947	.height = 136,
3341	4948	},
	4949	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3342	4950	},
3343	4951	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
3344	4952	MIPI_DSI_CLOCK_NON_CONTINUOUS,
	4953	+ .format = MIPI_DSI_FMT_RGB888,
	4954	+ .lanes = 4,
	4955	+};
	4956	+
	4957	+static const struct drm_display_mode lg_acx467akm_7_mode = {
	4958	+ .clock = 150000,
	4959	+ .hdisplay = 1080,
	4960	+ .hsync_start = 1080 + 2,
	4961	+ .hsync_end = 1080 + 2 + 2,
	4962	+ .htotal = 1080 + 2 + 2 + 2,
	4963	+ .vdisplay = 1920,
	4964	+ .vsync_start = 1920 + 2,
	4965	+ .vsync_end = 1920 + 2 + 2,
	4966	+ .vtotal = 1920 + 2 + 2 + 2,
	4967	+};
	4968	+
	4969	+static const struct panel_desc_dsi lg_acx467akm_7 = {
	4970	+ .desc = {
	4971	+ .modes = &lg_acx467akm_7_mode,
	4972	+ .num_modes = 1,
	4973	+ .bpc = 8,
	4974	+ .size = {
	4975	+ .width = 62,
	4976	+ .height = 110,
	4977	+ },
	4978	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
	4979	+ },
	4980	+ .flags = 0,
	4981	+ .format = MIPI_DSI_FMT_RGB888,
	4982	+ .lanes = 4,
	4983	+};
	4984	+
	4985	+static const struct drm_display_mode osd101t2045_53ts_mode = {
	4986	+ .clock = 154500,
	4987	+ .hdisplay = 1920,
	4988	+ .hsync_start = 1920 + 112,
	4989	+ .hsync_end = 1920 + 112 + 16,
	4990	+ .htotal = 1920 + 112 + 16 + 32,
	4991	+ .vdisplay = 1200,
	4992	+ .vsync_start = 1200 + 16,
	4993	+ .vsync_end = 1200 + 16 + 2,
	4994	+ .vtotal = 1200 + 16 + 2 + 16,
	4995	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	4996	+};
	4997	+
	4998	+static const struct panel_desc_dsi osd101t2045_53ts = {
	4999	+ .desc = {
	5000	+ .modes = &osd101t2045_53ts_mode,
	5001	+ .num_modes = 1,
	5002	+ .bpc = 8,
	5003	+ .size = {
	5004	+ .width = 217,
	5005	+ .height = 136,
	5006	+ },
	5007	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
	5008	+ },
	5009	+ .flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|
	5010	+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
	5011	+ MIPI_DSI_MODE_EOT_PACKET,
3345	5012	.format = MIPI_DSI_FMT_RGB888,
3346	5013	.lanes = 4,
3347	5014	};
..	..	@@ -3350,7 +5017,6 @@
3350	5017	{
3351	5018	.compatible = "simple-panel-dsi",
3352	5019	.data = NULL,
3353		-#ifndef CONFIG_DRM_PANEL_SIMPLE_OF_ONLY
3354	5020	}, {
3355	5021	.compatible = "auo,b080uan01",
3356	5022	.data = &auo_b080uan01
..	..	@@ -3366,7 +5032,12 @@
3366	5032	}, {
3367	5033	.compatible = "panasonic,vvx10f004b00",
3368	5034	.data = &panasonic_vvx10f004b00
3369		-#endif /* !CONFIG_DRM_PANEL_SIMPLE_OF_ONLY */
	5035	+ }, {
	5036	+ .compatible = "lg,acx467akm-7",
	5037	+ .data = &lg_acx467akm_7
	5038	+ }, {
	5039	+ .compatible = "osddisplays,osd101t2045-53ts",
	5040	+ .data = &osd101t2045_53ts
3370	5041	}, {
3371	5042	/* sentinel */
3372	5043	}
..	..	@@ -3428,6 +5099,26 @@
3428	5099	panel = dev_get_drvdata(dev);
3429	5100	panel->dsi = dsi;
3430	5101
	5102	+ if (!panel->base.backlight) {
	5103	+ struct backlight_properties props;
	5104	+
	5105	+ memset(&props, 0, sizeof(props));
	5106	+ props.type = BACKLIGHT_RAW;
	5107	+ props.brightness = 255;
	5108	+ props.max_brightness = 255;
	5109	+
	5110	+ panel->base.backlight =
	5111	+ devm_backlight_device_register(dev, "dcs-backlight",
	5112	+ dev, panel, &dcs_bl_ops,
	5113	+ &props);
	5114	+ if (IS_ERR(panel->base.backlight)) {
	5115	+ err = PTR_ERR(panel->base.backlight);
	5116	+ dev_err(dev, "failed to register dcs backlight: %d\n",
	5117	+ err);
	5118	+ return err;
	5119	+ }
	5120	+ }
	5121	+
3431	5122	dsi->mode_flags = desc->flags;
3432	5123	dsi->format = desc->format;
3433	5124	dsi->lanes = desc->lanes;
..	..	@@ -3468,6 +5159,113 @@
3468	5159	.shutdown = panel_simple_dsi_shutdown,
3469	5160	};
3470	5161
	5162	+static int panel_simple_spi_read(struct device dev, const u8 cmd, u8 data)
	5163	+{
	5164	+ return 0;
	5165	+}
	5166	+
	5167	+static int panel_simple_spi_write_word(struct device *dev, u16 data)
	5168	+{
	5169	+ struct spi_device *spi = to_spi_device(dev);
	5170	+ struct spi_transfer xfer = {
	5171	+ .len = 2,
	5172	+ .tx_buf = &data,
	5173	+ };
	5174	+ struct spi_message msg;
	5175	+
	5176	+ spi_message_init(&msg);
	5177	+ spi_message_add_tail(&xfer, &msg);
	5178	+
	5179	+ return spi_sync(spi, &msg);
	5180	+}
	5181	+
	5182	+static int panel_simple_spi_write(struct device dev, const u8 data, size_t len, u8 type)
	5183	+{
	5184	+ int ret = 0;
	5185	+ int i;
	5186	+ u16 mask = type ? 0x100 : 0;
	5187	+
	5188	+ for (i = 0; i < len; i++) {
	5189	+ ret = panel_simple_spi_write_word(dev, *data \| mask);
	5190	+ if (ret) {
	5191	+ dev_err(dev, "failed to write spi seq: %*ph\n", (int)len, data);
	5192	+ return ret;
	5193	+ }
	5194	+ data++;
	5195	+ }
	5196	+
	5197	+ return ret;
	5198	+}
	5199	+
	5200	+static const struct of_device_id panel_simple_spi_of_match[] = {
	5201	+ { .compatible = "simple-panel-spi", .data = NULL },
	5202	+ { /* sentinel */ }
	5203	+};
	5204	+MODULE_DEVICE_TABLE(of, panel_simple_spi_of_match);
	5205	+
	5206	+static int panel_simple_spi_probe(struct spi_device *spi)
	5207	+{
	5208	+ struct device *dev = &spi->dev;
	5209	+ const struct of_device_id *id;
	5210	+ const struct panel_desc *desc;
	5211	+ struct panel_desc *d;
	5212	+ int ret;
	5213	+
	5214	+ id = of_match_node(panel_simple_spi_of_match, dev->of_node);
	5215	+ if (!id)
	5216	+ return -ENODEV;
	5217	+
	5218	+ if (!id->data) {
	5219	+ d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
	5220	+ if (!d)
	5221	+ return -ENOMEM;
	5222	+
	5223	+ ret = panel_simple_of_get_desc_data(dev, d);
	5224	+ if (ret) {
	5225	+ dev_err(dev, "failed to get desc data: %d\n", ret);
	5226	+ return ret;
	5227	+ }
	5228	+
	5229	+ d->spi_write = panel_simple_spi_write;
	5230	+ d->spi_read = panel_simple_spi_read;
	5231	+ d->cmd_type = CMD_TYPE_SPI;
	5232	+ }
	5233	+ desc = id->data ? id->data : d;
	5234	+
	5235	+ /*
	5236	+ * Set spi to 3 lines and 9bits/word mode.
	5237	+ */
	5238	+ spi->bits_per_word = 9;
	5239	+ spi->mode = SPI_MODE_3;
	5240	+ ret = spi_setup(spi);
	5241	+ if (ret < 0) {
	5242	+ dev_err(dev, "spi setup failed.\n");
	5243	+ return ret;
	5244	+ }
	5245	+
	5246	+ return panel_simple_probe(dev, desc);
	5247	+}
	5248	+
	5249	+static int panel_simple_spi_remove(struct spi_device *spi)
	5250	+{
	5251	+ return panel_simple_remove(&spi->dev);
	5252	+}
	5253	+
	5254	+static void panel_simple_spi_shutdown(struct spi_device *spi)
	5255	+{
	5256	+ panel_simple_shutdown(&spi->dev);
	5257	+}
	5258	+
	5259	+static struct spi_driver panel_simple_spi_driver = {
	5260	+ .driver = {
	5261	+ .name = "panel-simple-spi",
	5262	+ .of_match_table = panel_simple_spi_of_match,
	5263	+ },
	5264	+ .probe = panel_simple_spi_probe,
	5265	+ .remove = panel_simple_spi_remove,
	5266	+ .shutdown = panel_simple_spi_shutdown,
	5267	+};
	5268	+
3471	5269	static int __init panel_simple_init(void)
3472	5270	{
3473	5271	int err;
..	..	@@ -3475,6 +5273,12 @@
3475	5273	err = platform_driver_register(&panel_simple_platform_driver);
3476	5274	if (err < 0)
3477	5275	return err;
	5276	+
	5277	+ if (IS_ENABLED(CONFIG_SPI_MASTER)) {
	5278	+ err = spi_register_driver(&panel_simple_spi_driver);
	5279	+ if (err < 0)
	5280	+ return err;
	5281	+ }
3478	5282
3479	5283	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3480	5284	err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
..	..	@@ -3484,17 +5288,16 @@
3484	5288
3485	5289	return 0;
3486	5290	}
3487		-#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
3488		-rootfs_initcall(panel_simple_init);
3489		-#else
3490	5291	module_init(panel_simple_init);
3491		-#endif
3492	5292
3493	5293	static void __exit panel_simple_exit(void)
3494	5294	{
3495	5295	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3496	5296	mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3497	5297
	5298	+ if (IS_ENABLED(CONFIG_SPI_MASTER))
	5299	+ spi_unregister_driver(&panel_simple_spi_driver);
	5300	+
3498	5301	platform_driver_unregister(&panel_simple_platform_driver);
3499	5302	}
3500	5303	module_exit(panel_simple_exit);