forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/gpio/gpio-rockchip.c
....@@ -1,31 +1,35 @@
11 // SPDX-License-Identifier: GPL-2.0-only
22 /*
3
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
3
+ * Copyright (c) 2013 MundoReader S.L.
4
+ * Author: Heiko Stuebner <heiko@sntech.de>
5
+ *
6
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
47  */
58 
6
-#include <linux/init.h>
7
-#include <linux/module.h>
9
+#include <linux/acpi.h>
810 #include <linux/bitops.h>
911 #include <linux/clk.h>
10
-#include <linux/err.h>
1112 #include <linux/device.h>
13
+#include <linux/err.h>
1214 #include <linux/gpio/driver.h>
15
+#include <linux/init.h>
1316 #include <linux/interrupt.h>
1417 #include <linux/io.h>
18
+#include <linux/module.h>
1519 #include <linux/of.h>
16
-#include <linux/of_address.h>
17
-#include <linux/of_device.h>
18
-#include <linux/of_irq.h>
20
+#include <linux/pinctrl/pinconf-generic.h>
21
+#include <linux/platform_device.h>
22
+#include <linux/property.h>
1923 #include <linux/regmap.h>
2024 
2125 #include "../pinctrl/core.h"
2226 #include "../pinctrl/pinctrl-rockchip.h"
2327 
24
-#define GPIO_TYPE_V1	(0)           /* GPIO Version ID reserved */
25
-#define GPIO_TYPE_V2	(0x01000C2B)  /* GPIO Version ID 0x01000C2B */
26
-#define GPIO_TYPE_V2_1	(0x0101157C)  /* GPIO Version ID 0x0101157C */
28
+#define GPIO_TYPE_V1		(0)           /* GPIO Version ID reserved */
29
+#define GPIO_TYPE_V2		(0x01000C2B)  /* GPIO Version ID 0x01000C2B */
30
+#define GPIO_TYPE_V2_1		(0x0101157C)  /* GPIO Version ID 0x0101157C */
2731 
28
-#define GPIO_BANK_PIN_NUM	(32)
32
+#define GPIO_MAX_PINS	(32)
2933 
3034 static const struct rockchip_gpio_regs gpio_regs_v1 = {
3135 	.port_dr = 0x00,
....@@ -134,7 +138,35 @@
134138 	return data & (0x1);
135139 }
136140 
137
-static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
141
+static int rockchip_gpio_get_direction(struct gpio_chip *chip,
142
+				       unsigned int offset)
143
+{
144
+	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
145
+	u32 data;
146
+
147
+	data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
148
+	if (data)
149
+		return GPIO_LINE_DIRECTION_OUT;
150
+
151
+	return GPIO_LINE_DIRECTION_IN;
152
+}
153
+
154
+static int rockchip_gpio_set_direction(struct gpio_chip *chip,
155
+				       unsigned int offset, bool input)
156
+{
157
+	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
158
+	unsigned long flags;
159
+	u32 data = input ? 0 : 1;
160
+
161
+	raw_spin_lock_irqsave(&bank->slock, flags);
162
+	rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
163
+	raw_spin_unlock_irqrestore(&bank->slock, flags);
164
+
165
+	return 0;
166
+}
167
+
168
+static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
169
+			      int value)
138170 {
139171 	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
140172 	unsigned long flags;
....@@ -156,41 +188,9 @@
156188 	return data;
157189 }
158190 
159
-static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
160
-{
161
-	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
162
-	u32 data;
163
-
164
-	data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
165
-
166
-	return !data;
167
-}
168
-
169
-static int rockchip_gpio_set_direction(struct gpio_chip *chip, unsigned int offset, bool input)
170
-{
171
-	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
172
-	u32 data = input ? 0 : 1;
173
-
174
-	rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
175
-
176
-	return 0;
177
-}
178
-
179
-static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
180
-{
181
-	return rockchip_gpio_set_direction(gc, offset, true);
182
-}
183
-
184
-static int rockchip_gpio_direction_output(struct gpio_chip *gc,
185
-					  unsigned int offset, int value)
186
-{
187
-	rockchip_gpio_set(gc, offset, value);
188
-
189
-	return rockchip_gpio_set_direction(gc, offset, false);
190
-}
191
-
192191 static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
193
-				       unsigned int offset, unsigned int debounce)
192
+				      unsigned int offset,
193
+				      unsigned int debounce)
194194 {
195195 	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
196196 	const struct rockchip_gpio_regs	*reg = bank->gpio_regs;
....@@ -199,11 +199,13 @@
199199 	unsigned int cur_div_reg;
200200 	u64 div;
201201 
202
-	if (!IS_ERR(bank->db_clk)) {
202
+	if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
203203 		div_debounce_support = true;
204204 		freq = clk_get_rate(bank->db_clk);
205
+		if (!freq)
206
+			return -EINVAL;
205207 		max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
206
-		if (debounce > max_debounce)
208
+		if ((unsigned long)debounce > max_debounce)
207209 			return -EINVAL;
208210 
209211 		div = debounce * freq;
....@@ -218,9 +220,11 @@
218220 	if (debounce) {
219221 		if (div_debounce_support) {
220222 			/* Configure the max debounce from consumers */
221
-			cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con);
223
+			cur_div_reg = readl(bank->reg_base +
224
+					    reg->dbclk_div_con);
222225 			if (cur_div_reg < div_reg)
223
-				writel(div_reg, bank->reg_base + reg->dbclk_div_con);
226
+				writel(div_reg, bank->reg_base +
227
+				       reg->dbclk_div_con);
224228 			rockchip_gpio_writel_bit(bank, offset, 1,
225229 						 reg->dbclk_div_en);
226230 		}
....@@ -247,6 +251,20 @@
247251 	return 0;
248252 }
249253 
254
+static int rockchip_gpio_direction_input(struct gpio_chip *gc,
255
+					 unsigned int offset)
256
+{
257
+	return rockchip_gpio_set_direction(gc, offset, true);
258
+}
259
+
260
+static int rockchip_gpio_direction_output(struct gpio_chip *gc,
261
+					  unsigned int offset, int value)
262
+{
263
+	rockchip_gpio_set(gc, offset, value);
264
+
265
+	return rockchip_gpio_set_direction(gc, offset, false);
266
+}
267
+
250268 /*
251269  * gpiolib set_config callback function. The setting of the pin
252270  * mux function as 'gpio output' will be handled by the pinctrl subsystem
....@@ -257,10 +275,10 @@
257275 {
258276 	enum pin_config_param param = pinconf_to_config_param(config);
259277 	unsigned int debounce = pinconf_to_config_argument(config);
260
-	int ret = 0;
261278 
262279 	switch (param) {
263280 	case PIN_CONFIG_INPUT_DEBOUNCE:
281
+		rockchip_gpio_set_debounce(gc, offset, debounce);
264282 		/*
265283 		 * Rockchip's gpio could only support up to one period
266284 		 * of the debounce clock(pclk), which is far away from
....@@ -272,15 +290,10 @@
272290 		 * still return -ENOTSUPP as before, to make sure the caller
273291 		 * of gpiod_set_debounce won't change its behaviour.
274292 		 */
275
-		rockchip_gpio_set_debounce(gc, offset, debounce);
276
-		ret = -ENOTSUPP;
277
-		break;
293
+		return -ENOTSUPP;
278294 	default:
279
-		ret = -ENOTSUPP;
280
-		break;
295
+		return -ENOTSUPP;
281296 	}
282
-
283
-	return ret;
284297 }
285298 
286299 /*
....@@ -317,14 +330,13 @@
317330 {
318331 	struct irq_chip *chip = irq_desc_get_chip(desc);
319332 	struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
320
-	const struct rockchip_gpio_regs	*reg = bank->gpio_regs;
321333 	u32 pend;
322334 
323335 	dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
324336 
325337 	chained_irq_enter(chip, desc);
326338 
327
-	pend = readl_relaxed(bank->reg_base + reg->int_status);
339
+	pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
328340 
329341 	while (pend) {
330342 		unsigned int irq, virq;
....@@ -348,24 +360,26 @@
348360 			u32 data, data_old, polarity;
349361 			unsigned long flags;
350362 
351
-			data = readl_relaxed(bank->reg_base + reg->ext_port);
363
+			data = readl_relaxed(bank->reg_base +
364
+					     bank->gpio_regs->ext_port);
352365 			do {
353366 				raw_spin_lock_irqsave(&bank->slock, flags);
354367 
355368 				polarity = readl_relaxed(bank->reg_base +
356
-							 reg->int_polarity);
369
+							 bank->gpio_regs->int_polarity);
357370 				if (data & BIT(irq))
358371 					polarity &= ~BIT(irq);
359372 				else
360373 					polarity |= BIT(irq);
361
-				writel(polarity, bank->reg_base +
362
-				       reg->int_polarity);
374
+				writel(polarity,
375
+				       bank->reg_base +
376
+				       bank->gpio_regs->int_polarity);
363377 
364378 				raw_spin_unlock_irqrestore(&bank->slock, flags);
365379 
366380 				data_old = data;
367381 				data = readl_relaxed(bank->reg_base +
368
-						     reg->ext_port);
382
+						     bank->gpio_regs->ext_port);
369383 			} while ((data & BIT(irq)) != (data_old & BIT(irq)));
370384 		}
371385 
....@@ -415,8 +429,8 @@
415429 			level |= mask;
416430 
417431 			/*
418
-			 * Determine gpio state. If 1 next interrupt should be falling
419
-			 * otherwise rising.
432
+			 * Determine gpio state. If 1 next interrupt should be
433
+			 * falling otherwise rising.
420434 			 */
421435 			data = readl(bank->reg_base + bank->gpio_regs->ext_port);
422436 			if (data & mask)
....@@ -475,26 +489,39 @@
475489 	irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
476490 }
477491 
492
+static void rockchip_irq_enable(struct irq_data *d)
493
+{
494
+	irq_gc_mask_clr_bit(d);
495
+}
496
+
497
+static void rockchip_irq_disable(struct irq_data *d)
498
+{
499
+	irq_gc_mask_set_bit(d);
500
+}
501
+
478502 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
479503 {
480504 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
481505 	struct irq_chip_generic *gc;
482506 	int ret;
483507 
484
-	bank->domain = irq_domain_add_linear(bank->of_node, 32,
485
-					     &irq_generic_chip_ops, NULL);
508
+	bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32,
509
+					&irq_generic_chip_ops, NULL);
486510 	if (!bank->domain) {
487
-		dev_warn(bank->dev, "could not initialize irq domain for bank %s\n", bank->name);
511
+		dev_warn(bank->dev, "could not init irq domain for bank %s\n",
512
+			 bank->name);
488513 		return -EINVAL;
489514 	}
490515 
491516 	ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
492
-					     bank->name, handle_level_irq,
517
+					     "rockchip_gpio_irq",
518
+					     handle_level_irq,
493519 					     clr, 0, 0);
494520 	if (ret) {
495
-		dev_err(bank->dev, "could not alloc generic chips for bank %s\n", bank->name);
521
+		dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
522
+			bank->name);
496523 		irq_domain_remove(bank->domain);
497
-		return ret;
524
+		return -EINVAL;
498525 	}
499526 
500527 	gc = irq_get_domain_generic_chip(bank->domain, 0);
....@@ -502,6 +529,7 @@
502529 		gc->reg_writel = gpio_writel_v2;
503530 		gc->reg_readl = gpio_readl_v2;
504531 	}
532
+
505533 	gc->reg_base = bank->reg_base;
506534 	gc->private = bank;
507535 	gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
....@@ -509,8 +537,8 @@
509537 	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
510538 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
511539 	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
512
-	gc->chip_types[0].chip.irq_enable = irq_gc_mask_clr_bit;
513
-	gc->chip_types[0].chip.irq_disable = irq_gc_mask_set_bit;
540
+	gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
541
+	gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
514542 	gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
515543 	gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
516544 	gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
....@@ -545,42 +573,22 @@
545573 	gc->ngpio = bank->nr_pins;
546574 	gc->label = bank->name;
547575 	gc->parent = bank->dev;
548
-#ifdef CONFIG_OF_GPIO
549
-	gc->of_node = of_node_get(bank->of_node);
550
-#endif
576
+
577
+	if (!gc->base)
578
+		gc->base = GPIO_MAX_PINS * bank->bank_num;
579
+	if (!gc->ngpio)
580
+		gc->ngpio = GPIO_MAX_PINS;
581
+	if (!gc->label) {
582
+		gc->label = kasprintf(GFP_KERNEL, "gpio%d", bank->bank_num);
583
+		if (!gc->label)
584
+			return -ENOMEM;
585
+	}
551586 
552587 	ret = gpiochip_add_data(gc, bank);
553588 	if (ret) {
554
-		dev_err(bank->dev, "failed to add gpiochip %s, %d\n", gc->label, ret);
589
+		dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
590
+			gc->label, ret);
555591 		return ret;
556
-	}
557
-
558
-	/*
559
-	 * For DeviceTree-supported systems, the gpio core checks the
560
-	 * pinctrl's device node for the "gpio-ranges" property.
561
-	 * If it is present, it takes care of adding the pin ranges
562
-	 * for the driver. In this case the driver can skip ahead.
563
-	 *
564
-	 * In order to remain compatible with older, existing DeviceTree
565
-	 * files which don't set the "gpio-ranges" property or systems that
566
-	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
567
-	 */
568
-	if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
569
-		struct device_node *pctlnp = of_get_parent(bank->of_node);
570
-		struct pinctrl_dev *pctldev = NULL;
571
-
572
-		if (!pctlnp)
573
-			return -ENODATA;
574
-
575
-		pctldev = of_pinctrl_get(pctlnp);
576
-		if (!pctldev)
577
-			return -ENODEV;
578
-
579
-		ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, gc->base, gc->ngpio);
580
-		if (ret) {
581
-			dev_err(bank->dev, "Failed to add pin range\n");
582
-			goto fail;
583
-		}
584592 	}
585593 
586594 	ret = rockchip_interrupts_register(bank);
....@@ -597,48 +605,22 @@
597605 	return ret;
598606 }
599607 
600
-static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
608
+static void rockchip_gpio_get_ver(struct rockchip_pin_bank *bank)
601609 {
602
-	struct resource res;
603
-	int id = 0;
604
-
605
-	if (of_address_to_resource(bank->of_node, 0, &res))
606
-		return -ENOENT;
607
-
608
-	bank->reg_base = devm_ioremap_resource(bank->dev, &res);
609
-	if (IS_ERR(bank->reg_base))
610
-		return PTR_ERR(bank->reg_base);
611
-
612
-	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
613
-	if (!bank->irq)
614
-		return -EINVAL;
615
-
616
-	bank->clk = of_clk_get(bank->of_node, 0);
617
-	if (IS_ERR(bank->clk))
618
-		return PTR_ERR(bank->clk);
619
-
620
-	clk_prepare_enable(bank->clk);
621
-	id = readl(bank->reg_base + gpio_regs_v2.version_id);
610
+	int id = readl(bank->reg_base + gpio_regs_v2.version_id);
622611 
623612 	/* If not gpio v2, that is default to v1. */
624613 	if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
625614 		bank->gpio_regs = &gpio_regs_v2;
626615 		bank->gpio_type = GPIO_TYPE_V2;
627
-		bank->db_clk = of_clk_get(bank->of_node, 1);
628
-		if (IS_ERR(bank->db_clk)) {
629
-			dev_err(bank->dev, "cannot find debounce clk\n");
630
-			bank->db_clk = NULL;
631
-			return -EINVAL;
632
-		}
633616 	} else {
634617 		bank->gpio_regs = &gpio_regs_v1;
635618 		bank->gpio_type = GPIO_TYPE_V1;
636619 	}
637
-
638
-	return 0;
639620 }
640621 
641
-static struct rockchip_pin_bank *rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
622
+static struct rockchip_pin_bank *
623
+rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
642624 {
643625 	struct rockchip_pinctrl *info;
644626 	struct rockchip_pin_bank *bank;
....@@ -656,50 +638,175 @@
656638 	return found ? bank : NULL;
657639 }
658640 
641
+static int rockchip_gpio_of_get_bank_id(struct device *dev)
642
+{
643
+	static int gpio;
644
+	int bank_id = -1;
645
+
646
+	if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
647
+		bank_id = of_alias_get_id(dev->of_node, "gpio");
648
+		if (bank_id < 0)
649
+			bank_id = gpio++;
650
+	}
651
+
652
+	return bank_id;
653
+}
654
+
655
+#ifdef CONFIG_ACPI
656
+static int rockchip_gpio_acpi_get_bank_id(struct device *dev)
657
+{
658
+	struct acpi_device *adev;
659
+	unsigned long bank_id = -1;
660
+	const char *uid;
661
+	int ret;
662
+
663
+	adev = ACPI_COMPANION(dev);
664
+	if (!adev)
665
+		return -ENXIO;
666
+
667
+	uid = acpi_device_uid(adev);
668
+	if (!uid || !(*uid)) {
669
+		dev_err(dev, "Cannot retrieve UID\n");
670
+		return -ENODEV;
671
+	}
672
+
673
+	ret = kstrtoul(uid, 0, &bank_id);
674
+
675
+	return !ret ? bank_id : -ERANGE;
676
+}
677
+#else
678
+static int rockchip_gpio_acpi_get_bank_id(struct device *dev)
679
+{
680
+	return -ENOENT;
681
+}
682
+#endif /* CONFIG_ACPI */
683
+
659684 static int rockchip_gpio_probe(struct platform_device *pdev)
660685 {
661686 	struct device *dev = &pdev->dev;
662
-	struct device_node *np = pdev->dev.of_node;
663
-	struct device_node *pctlnp = of_get_parent(np);
664687 	struct pinctrl_dev *pctldev = NULL;
665688 	struct rockchip_pin_bank *bank = NULL;
666
-	static int gpio;
667
-	int id, ret;
689
+	int bank_id = 0;
690
+	int ret;
668691 
669
-	if (!np || !pctlnp)
670
-		return -ENODEV;
692
+	bank_id = rockchip_gpio_acpi_get_bank_id(dev);
693
+	if (bank_id < 0) {
694
+		bank_id = rockchip_gpio_of_get_bank_id(dev);
695
+		if (bank_id < 0)
696
+			return bank_id;
697
+	}
671698 
672
-	pctldev = of_pinctrl_get(pctlnp);
673
-	if (!pctldev)
674
-		return -EPROBE_DEFER;
699
+	if (!ACPI_COMPANION(dev)) {
700
+		struct device_node *pctlnp = of_get_parent(dev->of_node);
675701 
676
-	id = of_alias_get_id(np, "gpio");
677
-	if (id < 0)
678
-		id = gpio++;
702
+		pctldev = of_pinctrl_get(pctlnp);
703
+		if (!pctldev)
704
+			return -EPROBE_DEFER;
679705 
680
-	bank = rockchip_gpio_find_bank(pctldev, id);
681
-	if (!bank)
682
-		return -EINVAL;
706
+		bank = rockchip_gpio_find_bank(pctldev, bank_id);
707
+		if (!bank)
708
+			return -ENODEV;
709
+	}
683710 
711
+	if (!bank) {
712
+		bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
713
+		if (!bank)
714
+			return -ENOMEM;
715
+	}
716
+
717
+	bank->bank_num = bank_id;
684718 	bank->dev = dev;
685
-	bank->of_node = dev->of_node;
719
+
720
+	bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
721
+	if (IS_ERR(bank->reg_base))
722
+		return PTR_ERR(bank->reg_base);
723
+
724
+	bank->irq = platform_get_irq(pdev, 0);
725
+	if (bank->irq < 0)
726
+		return bank->irq;
686727 
687728 	raw_spin_lock_init(&bank->slock);
688729 
689
-	ret = rockchip_get_bank_data(bank);
690
-	if (ret)
691
-		return ret;
730
+	if (!ACPI_COMPANION(dev)) {
731
+		bank->clk = devm_clk_get(dev, "bus");
732
+		if (IS_ERR(bank->clk)) {
733
+			bank->clk = of_clk_get(dev->of_node, 0);
734
+			if (IS_ERR(bank->clk)) {
735
+				dev_err(dev, "fail to get apb clock\n");
736
+				return PTR_ERR(bank->clk);
737
+			}
738
+		}
739
+
740
+		bank->db_clk = devm_clk_get(dev, "db");
741
+		if (IS_ERR(bank->db_clk)) {
742
+			bank->db_clk = of_clk_get(dev->of_node, 1);
743
+			if (IS_ERR(bank->db_clk))
744
+				bank->db_clk = NULL;
745
+		}
746
+	}
747
+
748
+	clk_prepare_enable(bank->clk);
749
+	clk_prepare_enable(bank->db_clk);
750
+
751
+	rockchip_gpio_get_ver(bank);
752
+
753
+	/*
754
+	 * Prevent clashes with a deferred output setting
755
+	 * being added right at this moment.
756
+	 */
757
+	mutex_lock(&bank->deferred_lock);
692758 
693759 	ret = rockchip_gpiolib_register(bank);
694
-	if (ret)
695
-		goto err_clk;
760
+	if (ret) {
761
+		dev_err(bank->dev, "Failed to register gpio %d\n", ret);
762
+		goto err_unlock;
763
+	}
764
+
765
+	if (!device_property_read_bool(bank->dev, "gpio-ranges") && pctldev) {
766
+		struct gpio_chip *gc = &bank->gpio_chip;
767
+
768
+		ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
769
+					     gc->base, gc->ngpio);
770
+		if (ret) {
771
+			dev_err(bank->dev, "Failed to add pin range\n");
772
+			goto err_unlock;
773
+		}
774
+	}
775
+
776
+	while (!list_empty(&bank->deferred_pins)) {
777
+		struct rockchip_pin_deferred *cfg;
778
+
779
+		cfg = list_first_entry(&bank->deferred_pins,
780
+				       struct rockchip_pin_deferred, head);
781
+		if (!cfg)
782
+			break;
783
+
784
+		list_del(&cfg->head);
785
+
786
+		switch (cfg->param) {
787
+		case PIN_CONFIG_OUTPUT:
788
+			ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
789
+			if (ret)
790
+				dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
791
+					 cfg->arg);
792
+			break;
793
+		default:
794
+			dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
795
+			break;
796
+		}
797
+		kfree(cfg);
798
+	}
799
+
800
+	mutex_unlock(&bank->deferred_lock);
696801 
697802 	platform_set_drvdata(pdev, bank);
698
-	dev_info(dev, "probed %s (%s)\n", bank->name, dev_name(dev));
803
+	dev_info(dev, "probed %pfw\n", dev_fwnode(dev));
699804 
700805 	return 0;
701
-err_clk:
806
+err_unlock:
807
+	mutex_unlock(&bank->deferred_lock);
702808 	clk_disable_unprepare(bank->clk);
809
+	clk_disable_unprepare(bank->db_clk);
703810 
704811 	return ret;
705812 }
....@@ -709,6 +816,7 @@
709816 	struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
710817 
711818 	clk_disable_unprepare(bank->clk);
819
+	clk_disable_unprepare(bank->db_clk);
712820 	gpiochip_remove(&bank->gpio_chip);
713821 
714822 	return 0;