forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/gpio/gpio-ep93xx.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Generic EP93xx GPIO handling
34  *
....@@ -6,10 +7,6 @@
67  *
78  * Based on code originally from:
89  *  linux/arch/arm/mach-ep93xx/core.c
9
- *
10
- *  This program is free software; you can redistribute it and/or modify
11
- *  it under the terms of the GNU General Public License version 2 as
12
- *  published by the Free Software Foundation.
1310  */
1411 
1512 #include <linux/init.h>
....@@ -19,86 +16,125 @@
1916 #include <linux/irq.h>
2017 #include <linux/slab.h>
2118 #include <linux/gpio/driver.h>
22
-/* FIXME: this is here for gpio_to_irq() - get rid of this! */
23
-#include <linux/gpio.h>
19
+#include <linux/bitops.h>
2420 
25
-#include <mach/hardware.h>
26
-#include <mach/gpio-ep93xx.h>
21
+#define EP93XX_GPIO_F_INT_STATUS 0x5c
22
+#define EP93XX_GPIO_A_INT_STATUS 0xa0
23
+#define EP93XX_GPIO_B_INT_STATUS 0xbc
2724 
28
-#define irq_to_gpio(irq)	((irq) - gpio_to_irq(0))
25
+/* Maximum value for gpio line identifiers */
26
+#define EP93XX_GPIO_LINE_MAX 63
27
+
28
+/* Number of GPIO chips in EP93XX */
29
+#define EP93XX_GPIO_CHIP_NUM 8
30
+
31
+/* Maximum value for irq capable line identifiers */
32
+#define EP93XX_GPIO_LINE_MAX_IRQ 23
33
+
34
+/*
35
+ * Static mapping of GPIO bank F IRQS:
36
+ * F0..F7 (16..24) to irq 80..87.
37
+ */
38
+#define EP93XX_GPIO_F_IRQ_BASE 80
39
+
40
+struct ep93xx_gpio_irq_chip {
41
+	struct irq_chip ic;
42
+	u8 irq_offset;
43
+	u8 int_unmasked;
44
+	u8 int_enabled;
45
+	u8 int_type1;
46
+	u8 int_type2;
47
+	u8 int_debounce;
48
+};
49
+
50
+struct ep93xx_gpio_chip {
51
+	struct gpio_chip		gc;
52
+	struct ep93xx_gpio_irq_chip	*eic;
53
+};
2954 
3055 struct ep93xx_gpio {
31
-	void __iomem		*mmio_base;
32
-	struct gpio_chip	gc[8];
56
+	void __iomem		*base;
57
+	struct ep93xx_gpio_chip	gc[EP93XX_GPIO_CHIP_NUM];
3358 };
59
+
60
+#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
61
+
62
+static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
63
+{
64
+	struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
65
+
66
+	return egc->eic;
67
+}
3468 
3569 /*************************************************************************
3670  * Interrupt handling for EP93xx on-chip GPIOs
3771  *************************************************************************/
38
-static unsigned char gpio_int_unmasked[3];
39
-static unsigned char gpio_int_enabled[3];
40
-static unsigned char gpio_int_type1[3];
41
-static unsigned char gpio_int_type2[3];
42
-static unsigned char gpio_int_debounce[3];
72
+#define EP93XX_INT_TYPE1_OFFSET		0x00
73
+#define EP93XX_INT_TYPE2_OFFSET		0x04
74
+#define EP93XX_INT_EOI_OFFSET		0x08
75
+#define EP93XX_INT_EN_OFFSET		0x0c
76
+#define EP93XX_INT_STATUS_OFFSET	0x10
77
+#define EP93XX_INT_RAW_STATUS_OFFSET	0x14
78
+#define EP93XX_INT_DEBOUNCE_OFFSET	0x18
4379 
44
-/* Port ordering is: A B F */
45
-static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
46
-static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
47
-static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
48
-static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
49
-static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };
50
-
51
-static void ep93xx_gpio_update_int_params(unsigned port)
80
+static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
81
+					  struct ep93xx_gpio_irq_chip *eic)
5282 {
53
-	BUG_ON(port > 2);
83
+	writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
5484 
55
-	writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
85
+	writeb_relaxed(eic->int_type2,
86
+		       epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
5687 
57
-	writeb_relaxed(gpio_int_type2[port],
58
-		EP93XX_GPIO_REG(int_type2_register_offset[port]));
88
+	writeb_relaxed(eic->int_type1,
89
+		       epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
5990 
60
-	writeb_relaxed(gpio_int_type1[port],
61
-		EP93XX_GPIO_REG(int_type1_register_offset[port]));
62
-
63
-	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
64
-		EP93XX_GPIO_REG(int_en_register_offset[port]));
91
+	writeb_relaxed(eic->int_unmasked & eic->int_enabled,
92
+		       epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
6593 }
6694 
67
-static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
95
+static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
96
+				     unsigned int offset, bool enable)
6897 {
69
-	int line = irq_to_gpio(irq);
70
-	int port = line >> 3;
71
-	int port_mask = 1 << (line & 7);
98
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
99
+	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
100
+	int port_mask = BIT(offset);
72101 
73102 	if (enable)
74
-		gpio_int_debounce[port] |= port_mask;
103
+		eic->int_debounce |= port_mask;
75104 	else
76
-		gpio_int_debounce[port] &= ~port_mask;
105
+		eic->int_debounce &= ~port_mask;
77106 
78
-	writeb(gpio_int_debounce[port],
79
-		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
107
+	writeb(eic->int_debounce,
108
+	       epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
80109 }
81110 
82111 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
83112 {
84
-	unsigned char status;
85
-	int i;
113
+	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
114
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
115
+	struct irq_chip *irqchip = irq_desc_get_chip(desc);
116
+	unsigned long stat;
117
+	int offset;
86118 
87
-	status = readb(EP93XX_GPIO_A_INT_STATUS);
88
-	for (i = 0; i < 8; i++) {
89
-		if (status & (1 << i)) {
90
-			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
91
-			generic_handle_irq(gpio_irq);
92
-		}
93
-	}
119
+	chained_irq_enter(irqchip, desc);
94120 
95
-	status = readb(EP93XX_GPIO_B_INT_STATUS);
96
-	for (i = 0; i < 8; i++) {
97
-		if (status & (1 << i)) {
98
-			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
99
-			generic_handle_irq(gpio_irq);
100
-		}
101
-	}
121
+	/*
122
+	 * Dispatch the IRQs to the irqdomain of each A and B
123
+	 * gpiochip irqdomains depending on what has fired.
124
+	 * The tricky part is that the IRQ line is shared
125
+	 * between bank A and B and each has their own gpiochip.
126
+	 */
127
+	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
128
+	for_each_set_bit(offset, &stat, 8)
129
+		generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
130
+						    offset));
131
+
132
+	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
133
+	for_each_set_bit(offset, &stat, 8)
134
+		generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
135
+						    offset));
136
+
137
+	chained_irq_exit(irqchip, desc);
102138 }
103139 
104140 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
....@@ -106,60 +142,67 @@
106142 	/*
107143 	 * map discontiguous hw irq range to continuous sw irq range:
108144 	 *
109
-	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
145
+	 *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
110146 	 */
147
+	struct irq_chip *irqchip = irq_desc_get_chip(desc);
111148 	unsigned int irq = irq_desc_get_irq(desc);
112149 	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
113
-	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
150
+	int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
114151 
152
+	chained_irq_enter(irqchip, desc);
115153 	generic_handle_irq(gpio_irq);
154
+	chained_irq_exit(irqchip, desc);
116155 }
117156 
118157 static void ep93xx_gpio_irq_ack(struct irq_data *d)
119158 {
120
-	int line = irq_to_gpio(d->irq);
121
-	int port = line >> 3;
122
-	int port_mask = 1 << (line & 7);
159
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160
+	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
161
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
162
+	int port_mask = BIT(d->irq & 7);
123163 
124164 	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
125
-		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
126
-		ep93xx_gpio_update_int_params(port);
165
+		eic->int_type2 ^= port_mask; /* switch edge direction */
166
+		ep93xx_gpio_update_int_params(epg, eic);
127167 	}
128168 
129
-	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
169
+	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
130170 }
131171 
132172 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
133173 {
134
-	int line = irq_to_gpio(d->irq);
135
-	int port = line >> 3;
136
-	int port_mask = 1 << (line & 7);
174
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175
+	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
176
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
177
+	int port_mask = BIT(d->irq & 7);
137178 
138179 	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
139
-		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
180
+		eic->int_type2 ^= port_mask; /* switch edge direction */
140181 
141
-	gpio_int_unmasked[port] &= ~port_mask;
142
-	ep93xx_gpio_update_int_params(port);
182
+	eic->int_unmasked &= ~port_mask;
183
+	ep93xx_gpio_update_int_params(epg, eic);
143184 
144
-	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
185
+	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
145186 }
146187 
147188 static void ep93xx_gpio_irq_mask(struct irq_data *d)
148189 {
149
-	int line = irq_to_gpio(d->irq);
150
-	int port = line >> 3;
190
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
191
+	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
192
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
151193 
152
-	gpio_int_unmasked[port] &= ~(1 << (line & 7));
153
-	ep93xx_gpio_update_int_params(port);
194
+	eic->int_unmasked &= ~BIT(d->irq & 7);
195
+	ep93xx_gpio_update_int_params(epg, eic);
154196 }
155197 
156198 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
157199 {
158
-	int line = irq_to_gpio(d->irq);
159
-	int port = line >> 3;
200
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
201
+	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
202
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
160203 
161
-	gpio_int_unmasked[port] |= 1 << (line & 7);
162
-	ep93xx_gpio_update_int_params(port);
204
+	eic->int_unmasked |= BIT(d->irq & 7);
205
+	ep93xx_gpio_update_int_params(epg, eic);
163206 }
164207 
165208 /*
....@@ -169,41 +212,43 @@
169212  */
170213 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
171214 {
172
-	const int gpio = irq_to_gpio(d->irq);
173
-	const int port = gpio >> 3;
174
-	const int port_mask = 1 << (gpio & 7);
215
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
216
+	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
217
+	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
218
+	int offset = d->irq & 7;
219
+	int port_mask = BIT(offset);
175220 	irq_flow_handler_t handler;
176221 
177
-	gpio_direction_input(gpio);
222
+	gc->direction_input(gc, offset);
178223 
179224 	switch (type) {
180225 	case IRQ_TYPE_EDGE_RISING:
181
-		gpio_int_type1[port] |= port_mask;
182
-		gpio_int_type2[port] |= port_mask;
226
+		eic->int_type1 |= port_mask;
227
+		eic->int_type2 |= port_mask;
183228 		handler = handle_edge_irq;
184229 		break;
185230 	case IRQ_TYPE_EDGE_FALLING:
186
-		gpio_int_type1[port] |= port_mask;
187
-		gpio_int_type2[port] &= ~port_mask;
231
+		eic->int_type1 |= port_mask;
232
+		eic->int_type2 &= ~port_mask;
188233 		handler = handle_edge_irq;
189234 		break;
190235 	case IRQ_TYPE_LEVEL_HIGH:
191
-		gpio_int_type1[port] &= ~port_mask;
192
-		gpio_int_type2[port] |= port_mask;
236
+		eic->int_type1 &= ~port_mask;
237
+		eic->int_type2 |= port_mask;
193238 		handler = handle_level_irq;
194239 		break;
195240 	case IRQ_TYPE_LEVEL_LOW:
196
-		gpio_int_type1[port] &= ~port_mask;
197
-		gpio_int_type2[port] &= ~port_mask;
241
+		eic->int_type1 &= ~port_mask;
242
+		eic->int_type2 &= ~port_mask;
198243 		handler = handle_level_irq;
199244 		break;
200245 	case IRQ_TYPE_EDGE_BOTH:
201
-		gpio_int_type1[port] |= port_mask;
246
+		eic->int_type1 |= port_mask;
202247 		/* set initial polarity based on current input level */
203
-		if (gpio_get_value(gpio))
204
-			gpio_int_type2[port] &= ~port_mask; /* falling */
248
+		if (gc->get(gc, offset))
249
+			eic->int_type2 &= ~port_mask; /* falling */
205250 		else
206
-			gpio_int_type2[port] |= port_mask; /* rising */
251
+			eic->int_type2 |= port_mask; /* rising */
207252 		handler = handle_edge_irq;
208253 		break;
209254 	default:
....@@ -212,53 +257,12 @@
212257 
213258 	irq_set_handler_locked(d, handler);
214259 
215
-	gpio_int_enabled[port] |= port_mask;
260
+	eic->int_enabled |= port_mask;
216261 
217
-	ep93xx_gpio_update_int_params(port);
262
+	ep93xx_gpio_update_int_params(epg, eic);
218263 
219264 	return 0;
220265 }
221
-
222
-static struct irq_chip ep93xx_gpio_irq_chip = {
223
-	.name		= "GPIO",
224
-	.irq_ack	= ep93xx_gpio_irq_ack,
225
-	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
226
-	.irq_mask	= ep93xx_gpio_irq_mask,
227
-	.irq_unmask	= ep93xx_gpio_irq_unmask,
228
-	.irq_set_type	= ep93xx_gpio_irq_type,
229
-};
230
-
231
-static void ep93xx_gpio_init_irq(void)
232
-{
233
-	int gpio_irq;
234
-
235
-	for (gpio_irq = gpio_to_irq(0);
236
-	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
237
-		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
238
-					 handle_level_irq);
239
-		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
240
-	}
241
-
242
-	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
243
-				ep93xx_gpio_ab_irq_handler);
244
-	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
245
-				ep93xx_gpio_f_irq_handler);
246
-	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
247
-				ep93xx_gpio_f_irq_handler);
248
-	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
249
-				ep93xx_gpio_f_irq_handler);
250
-	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
251
-				ep93xx_gpio_f_irq_handler);
252
-	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
253
-				ep93xx_gpio_f_irq_handler);
254
-	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
255
-				ep93xx_gpio_f_irq_handler);
256
-	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
257
-				ep93xx_gpio_f_irq_handler);
258
-	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
259
-				ep93xx_gpio_f_irq_handler);
260
-}
261
-
262266 
263267 /*************************************************************************
264268  * gpiolib interface for EP93xx on-chip GPIOs
....@@ -267,69 +271,77 @@
267271 	const char	*label;
268272 	int		data;
269273 	int		dir;
274
+	int		irq;
270275 	int		base;
271
-	bool		has_debounce;
276
+	bool		has_irq;
277
+	bool		has_hierarchical_irq;
278
+	unsigned int	irq_base;
272279 };
273280 
274
-#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce)	\
281
+#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
275282 	{							\
276283 		.label		= _label,			\
277284 		.data		= _data,			\
278285 		.dir		= _dir,				\
286
+		.irq		= _irq,				\
279287 		.base		= _base,			\
280
-		.has_debounce	= _debounce,			\
288
+		.has_irq	= _has_irq,			\
289
+		.has_hierarchical_irq = _has_hier,		\
290
+		.irq_base	= _irq_base,			\
281291 	}
282292 
283293 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
284
-	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
285
-	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
286
-	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
287
-	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
288
-	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
289
-	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
290
-	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
291
-	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
294
+	/* Bank A has 8 IRQs */
295
+	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64),
296
+	/* Bank B has 8 IRQs */
297
+	EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72),
298
+	EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
299
+	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
300
+	EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
301
+	/* Bank F has 8 IRQs */
302
+	EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0),
303
+	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
304
+	EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
292305 };
293306 
294
-static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset,
307
+static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
295308 				  unsigned long config)
296309 {
297
-	int gpio = chip->base + offset;
298
-	int irq = gpio_to_irq(gpio);
299310 	u32 debounce;
300311 
301312 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
302313 		return -ENOTSUPP;
303314 
304
-	if (irq < 0)
305
-		return -EINVAL;
306
-
307315 	debounce = pinconf_to_config_argument(config);
308
-	ep93xx_gpio_int_debounce(irq, debounce ? true : false);
316
+	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
309317 
310318 	return 0;
311319 }
312320 
313
-/*
314
- * Map GPIO A0..A7  (0..7)  to irq 64..71,
315
- *          B0..B7  (7..15) to irq 72..79, and
316
- *          F0..F7 (16..24) to irq 80..87.
317
- */
318
-static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
321
+static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
319322 {
320
-	int gpio = chip->base + offset;
321
-
322
-	if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
323
-		return -EINVAL;
324
-
325
-	return 64 + gpio;
323
+	return EP93XX_GPIO_F_IRQ_BASE + offset;
326324 }
327325 
328
-static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
329
-	void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
326
+static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic)
330327 {
331
-	void __iomem *data = mmio_base + bank->data;
332
-	void __iomem *dir =  mmio_base + bank->dir;
328
+	ic->irq_ack = ep93xx_gpio_irq_ack;
329
+	ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack;
330
+	ic->irq_mask = ep93xx_gpio_irq_mask;
331
+	ic->irq_unmask = ep93xx_gpio_irq_unmask;
332
+	ic->irq_set_type = ep93xx_gpio_irq_type;
333
+}
334
+
335
+static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
336
+				struct platform_device *pdev,
337
+				struct ep93xx_gpio *epg,
338
+				struct ep93xx_gpio_bank *bank)
339
+{
340
+	void __iomem *data = epg->base + bank->data;
341
+	void __iomem *dir = epg->base + bank->dir;
342
+	struct gpio_chip *gc = &egc->gc;
343
+	struct device *dev = &pdev->dev;
344
+	struct gpio_irq_chip *girq;
333345 	int err;
334346 
335347 	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
....@@ -339,41 +351,97 @@
339351 	gc->label = bank->label;
340352 	gc->base = bank->base;
341353 
342
-	if (bank->has_debounce) {
354
+	girq = &gc->irq;
355
+	if (bank->has_irq || bank->has_hierarchical_irq) {
356
+		struct irq_chip *ic;
357
+
343358 		gc->set_config = ep93xx_gpio_set_config;
344
-		gc->to_irq = ep93xx_gpio_to_irq;
359
+		egc->eic = devm_kcalloc(dev, 1,
360
+					sizeof(*egc->eic),
361
+					GFP_KERNEL);
362
+		if (!egc->eic)
363
+			return -ENOMEM;
364
+		egc->eic->irq_offset = bank->irq;
365
+		ic = &egc->eic->ic;
366
+		ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label);
367
+		if (!ic->name)
368
+			return -ENOMEM;
369
+		ep93xx_init_irq_chip(dev, ic);
370
+		girq->chip = ic;
345371 	}
346372 
347
-	return devm_gpiochip_add_data(dev, gc, NULL);
373
+	if (bank->has_irq) {
374
+		int ab_parent_irq = platform_get_irq(pdev, 0);
375
+
376
+		girq->parent_handler = ep93xx_gpio_ab_irq_handler;
377
+		girq->num_parents = 1;
378
+		girq->parents = devm_kcalloc(dev, 1,
379
+					     sizeof(*girq->parents),
380
+					     GFP_KERNEL);
381
+		if (!girq->parents)
382
+			return -ENOMEM;
383
+		girq->default_type = IRQ_TYPE_NONE;
384
+		girq->handler = handle_level_irq;
385
+		girq->parents[0] = ab_parent_irq;
386
+		girq->first = bank->irq_base;
387
+	}
388
+
389
+	/* Only bank F has especially funky IRQ handling */
390
+	if (bank->has_hierarchical_irq) {
391
+		int gpio_irq;
392
+		int i;
393
+
394
+		/*
395
+		 * FIXME: convert this to use hierarchical IRQ support!
396
+		 * this requires fixing the root irqchip to be hierarchial.
397
+		 */
398
+		girq->parent_handler = ep93xx_gpio_f_irq_handler;
399
+		girq->num_parents = 8;
400
+		girq->parents = devm_kcalloc(dev, 8,
401
+					     sizeof(*girq->parents),
402
+					     GFP_KERNEL);
403
+		if (!girq->parents)
404
+			return -ENOMEM;
405
+		/* Pick resources 1..8 for these IRQs */
406
+		for (i = 1; i <= 8; i++)
407
+			girq->parents[i - 1] = platform_get_irq(pdev, i);
408
+		for (i = 0; i < 8; i++) {
409
+			gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
410
+			irq_set_chip_data(gpio_irq, &epg->gc[5]);
411
+			irq_set_chip_and_handler(gpio_irq,
412
+						 girq->chip,
413
+						 handle_level_irq);
414
+			irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
415
+		}
416
+		girq->default_type = IRQ_TYPE_NONE;
417
+		girq->handler = handle_level_irq;
418
+		gc->to_irq = ep93xx_gpio_f_to_irq;
419
+	}
420
+
421
+	return devm_gpiochip_add_data(dev, gc, epg);
348422 }
349423 
350424 static int ep93xx_gpio_probe(struct platform_device *pdev)
351425 {
352
-	struct ep93xx_gpio *ep93xx_gpio;
353
-	struct resource *res;
426
+	struct ep93xx_gpio *epg;
354427 	int i;
355
-	struct device *dev = &pdev->dev;
356428 
357
-	ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
358
-	if (!ep93xx_gpio)
429
+	epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
430
+	if (!epg)
359431 		return -ENOMEM;
360432 
361
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
362
-	ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
363
-	if (IS_ERR(ep93xx_gpio->mmio_base))
364
-		return PTR_ERR(ep93xx_gpio->mmio_base);
433
+	epg->base = devm_platform_ioremap_resource(pdev, 0);
434
+	if (IS_ERR(epg->base))
435
+		return PTR_ERR(epg->base);
365436 
366437 	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
367
-		struct gpio_chip *gc = &ep93xx_gpio->gc[i];
438
+		struct ep93xx_gpio_chip *gc = &epg->gc[i];
368439 		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
369440 
370
-		if (ep93xx_gpio_add_bank(gc, &pdev->dev,
371
-					 ep93xx_gpio->mmio_base, bank))
441
+		if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
372442 			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
373
-				bank->label);
443
+				 bank->label);
374444 	}
375
-
376
-	ep93xx_gpio_init_irq();
377445 
378446 	return 0;
379447 }