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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/gpio/gpio-crystalcove.c
....@@ -1,28 +1,20 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
3
+ * Intel Crystal Cove GPIO Driver
34  *
45  * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License version
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- * 2 as published by the Free Software Foundation.
9
- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
146  *
157  * Author: Yang, Bin <bin.yang@intel.com>
168  */
179 
10
+#include <linux/bitops.h>
11
+#include <linux/gpio/driver.h>
1812 #include <linux/interrupt.h>
13
+#include <linux/mfd/intel_soc_pmic.h>
1914 #include <linux/module.h>
2015 #include <linux/platform_device.h>
21
-#include <linux/gpio/driver.h>
22
-#include <linux/seq_file.h>
23
-#include <linux/bitops.h>
2416 #include <linux/regmap.h>
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-#include <linux/mfd/intel_soc_pmic.h>
17
+#include <linux/seq_file.h>
2618 
2719 #define CRYSTALCOVE_GPIO_NUM	16
2820 #define CRYSTALCOVE_VGPIO_NUM	95
....@@ -137,7 +129,7 @@
137129 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
138130 }
139131 
140
-static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
132
+static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
141133 {
142134 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
143135 	int reg = to_reg(gpio, CTRL_OUT);
....@@ -148,7 +140,7 @@
148140 	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
149141 }
150142 
151
-static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
143
+static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
152144 				    int value)
153145 {
154146 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
....@@ -160,7 +152,7 @@
160152 	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
161153 }
162154 
163
-static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
155
+static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
164156 {
165157 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
166158 	unsigned int val;
....@@ -177,7 +169,7 @@
177169 }
178170 
179171 static void crystalcove_gpio_set(struct gpio_chip *chip,
180
-				 unsigned gpio, int value)
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+				 unsigned int gpio, int value)
181173 {
182174 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
183175 	int reg = to_reg(gpio, CTRL_OUT);
....@@ -191,7 +183,7 @@
191183 		regmap_update_bits(cg->regmap, reg, 1, 0);
192184 }
193185 
194
-static int crystalcove_irq_type(struct irq_data *data, unsigned type)
186
+static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
195187 {
196188 	struct crystalcove_gpio *cg =
197189 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
....@@ -279,8 +271,8 @@
279271 static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
280272 {
281273 	struct crystalcove_gpio *cg = data;
274
+	unsigned long pending;
282275 	unsigned int p0, p1;
283
-	int pending;
284276 	int gpio;
285277 	unsigned int virq;
286278 
....@@ -293,11 +285,9 @@
293285 
294286 	pending = p0 | p1 << 8;
295287 
296
-	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
297
-		if (pending & BIT(gpio)) {
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-			virq = irq_find_mapping(cg->chip.irq.domain, gpio);
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-			handle_nested_irq(virq);
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-		}
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+	for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
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+		virq = irq_find_mapping(cg->chip.irq.domain, gpio);
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+		handle_nested_irq(virq);
301291 	}
302292 
303293 	return IRQ_HANDLED;
....@@ -340,6 +330,7 @@
340330 	int retval;
341331 	struct device *dev = pdev->dev.parent;
342332 	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
333
+	struct gpio_irq_chip *girq;
343334 
344335 	if (irq < 0)
345336 		return irq;
....@@ -363,46 +354,39 @@
363354 	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
364355 	cg->regmap = pmic->regmap;
365356 
357
+	girq = &cg->chip.irq;
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+	girq->chip = &crystalcove_irqchip;
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+	/* This will let us handle the parent IRQ in the driver */
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+	girq->parent_handler = NULL;
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+	girq->num_parents = 0;
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+	girq->parents = NULL;
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+	girq->default_type = IRQ_TYPE_NONE;
364
+	girq->handler = handle_simple_irq;
365
+	girq->threaded = true;
366
+
367
+	retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
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+					   crystalcove_gpio_irq_handler,
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+					   IRQF_ONESHOT, KBUILD_MODNAME, cg);
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+	if (retval) {
371
+		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
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+		return retval;
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+	}
374
+
366375 	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
367376 	if (retval) {
368377 		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
369378 		return retval;
370379 	}
371380 
372
-	gpiochip_irqchip_add_nested(&cg->chip, &crystalcove_irqchip, 0,
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-				    handle_simple_irq, IRQ_TYPE_NONE);
374
-
375
-	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
376
-				      IRQF_ONESHOT, KBUILD_MODNAME, cg);
377
-
378
-	if (retval) {
379
-		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
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-		return retval;
381
-	}
382
-
383
-	gpiochip_set_nested_irqchip(&cg->chip, &crystalcove_irqchip, irq);
384
-
385
-	return 0;
386
-}
387
-
388
-static int crystalcove_gpio_remove(struct platform_device *pdev)
389
-{
390
-	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
391
-	int irq = platform_get_irq(pdev, 0);
392
-
393
-	if (irq >= 0)
394
-		free_irq(irq, cg);
395381 	return 0;
396382 }
397383 
398384 static struct platform_driver crystalcove_gpio_driver = {
399385 	.probe = crystalcove_gpio_probe,
400
-	.remove = crystalcove_gpio_remove,
401386 	.driver = {
402387 		.name = "crystal_cove_gpio",
403388 	},
404389 };
405
-
406390 module_platform_driver(crystalcove_gpio_driver);
407391 
408392 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");