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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (c) 2017, National Instruments Corp. |
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| 3 | 4 | * Copyright (c) 2017, Xilix Inc |
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| 4 | 5 | * |
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| 5 | 6 | * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration |
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| 6 | 7 | * Decoupler IP Core. |
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| 7 | | - * |
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| 8 | | - * This program is free software; you can redistribute it and/or modify |
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| 9 | | - * it under the terms of the GNU General Public License as published by |
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| 10 | | - * the Free Software Foundation; version 2 of the License. |
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| 11 | | - * |
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| 12 | | - * This program is distributed in the hope that it will be useful, |
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| 13 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 15 | | - * GNU General Public License for more details. |
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| 16 | 8 | */ |
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| 17 | 9 | |
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| 18 | 10 | #include <linux/clk.h> |
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| .. | .. |
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| 109 | 101 | |
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| 110 | 102 | priv->clk = devm_clk_get(&pdev->dev, "aclk"); |
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| 111 | 103 | if (IS_ERR(priv->clk)) { |
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| 112 | | - dev_err(&pdev->dev, "input clock not found\n"); |
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| 104 | + if (PTR_ERR(priv->clk) != -EPROBE_DEFER) |
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| 105 | + dev_err(&pdev->dev, "input clock not found\n"); |
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| 113 | 106 | return PTR_ERR(priv->clk); |
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| 114 | 107 | } |
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| 115 | 108 | |
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| .. | .. |
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| 121 | 114 | |
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| 122 | 115 | clk_disable(priv->clk); |
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| 123 | 116 | |
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| 124 | | - br = fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler", |
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| 125 | | - &xlnx_pr_decoupler_br_ops, priv); |
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| 117 | + br = devm_fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler", |
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| 118 | + &xlnx_pr_decoupler_br_ops, priv); |
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| 126 | 119 | if (!br) { |
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| 127 | 120 | err = -ENOMEM; |
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| 128 | 121 | goto err_clk; |
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