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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/fpga/altera-cvp.c
....@@ -1,18 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
34  *
45  * Copyright (C) 2017 DENX Software Engineering
56  *
67  * Anatolij Gustschin <agust@denx.de>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; version 2 of the License.
11
- *
12
- * This program is distributed in the hope that it will be useful,
13
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
- * GNU General Public License for more details.
168  *
179  * Manage Altera FPGA firmware using PCIe CvP.
1810  * Firmware must be in binary "rbf" format.
....@@ -30,10 +22,10 @@
3022 #define TIMEOUT_US	2000	/* CVP STATUS timeout for USERMODE polling */
3123 
3224 /* Vendor Specific Extended Capability Registers */
33
-#define VSE_PCIE_EXT_CAP_ID		0x200
25
+#define VSE_PCIE_EXT_CAP_ID		0x0
3426 #define VSE_PCIE_EXT_CAP_ID_VAL		0x000b	/* 16bit */
3527 
36
-#define VSE_CVP_STATUS			0x21c	/* 32bit */
28
+#define VSE_CVP_STATUS			0x1c	/* 32bit */
3729 #define VSE_CVP_STATUS_CFG_RDY		BIT(18)	/* CVP_CONFIG_READY */
3830 #define VSE_CVP_STATUS_CFG_ERR		BIT(19)	/* CVP_CONFIG_ERROR */
3931 #define VSE_CVP_STATUS_CVP_EN		BIT(20)	/* ctrl block is enabling CVP */
....@@ -41,41 +33,93 @@
4133 #define VSE_CVP_STATUS_CFG_DONE		BIT(23)	/* CVP_CONFIG_DONE */
4234 #define VSE_CVP_STATUS_PLD_CLK_IN_USE	BIT(24)	/* PLD_CLK_IN_USE */
4335 
44
-#define VSE_CVP_MODE_CTRL		0x220	/* 32bit */
36
+#define VSE_CVP_MODE_CTRL		0x20	/* 32bit */
4537 #define VSE_CVP_MODE_CTRL_CVP_MODE	BIT(0)	/* CVP (1) or normal mode (0) */
4638 #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL	BIT(1) /* PMA (1) or fabric clock (0) */
4739 #define VSE_CVP_MODE_CTRL_NUMCLKS_OFF	8	/* NUMCLKS bits offset */
4840 #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK	GENMASK(15, 8)
4941 
50
-#define VSE_CVP_DATA			0x228	/* 32bit */
51
-#define VSE_CVP_PROG_CTRL		0x22c	/* 32bit */
42
+#define VSE_CVP_DATA			0x28	/* 32bit */
43
+#define VSE_CVP_PROG_CTRL		0x2c	/* 32bit */
5244 #define VSE_CVP_PROG_CTRL_CONFIG	BIT(0)
5345 #define VSE_CVP_PROG_CTRL_START_XFER	BIT(1)
46
+#define VSE_CVP_PROG_CTRL_MASK		GENMASK(1, 0)
5447 
55
-#define VSE_UNCOR_ERR_STATUS		0x234	/* 32bit */
48
+#define VSE_UNCOR_ERR_STATUS		0x34	/* 32bit */
5649 #define VSE_UNCOR_ERR_CVP_CFG_ERR	BIT(5)	/* CVP_CONFIG_ERROR_LATCHED */
50
+
51
+#define V1_VSEC_OFFSET			0x200	/* Vendor Specific Offset V1 */
52
+/* V2 Defines */
53
+#define VSE_CVP_TX_CREDITS		0x49	/* 8bit */
54
+
55
+#define V2_CREDIT_TIMEOUT_US		20000
56
+#define V2_CHECK_CREDIT_US		10
57
+#define V2_POLL_TIMEOUT_US		1000000
58
+#define V2_USER_TIMEOUT_US		500000
59
+
60
+#define V1_POLL_TIMEOUT_US		10
5761 
5862 #define DRV_NAME		"altera-cvp"
5963 #define ALTERA_CVP_MGR_NAME	"Altera CvP FPGA Manager"
6064 
65
+/* Write block sizes */
66
+#define ALTERA_CVP_V1_SIZE	4
67
+#define ALTERA_CVP_V2_SIZE	4096
68
+
6169 /* Optional CvP config error status check for debugging */
6270 static bool altera_cvp_chkcfg;
71
+
72
+struct cvp_priv;
6373 
6474 struct altera_cvp_conf {
6575 	struct fpga_manager	*mgr;
6676 	struct pci_dev		*pci_dev;
6777 	void __iomem		*map;
68
-	void			(*write_data)(struct altera_cvp_conf *, u32);
78
+	void			(*write_data)(struct altera_cvp_conf *conf,
79
+					      u32 data);
6980 	char			mgr_name[64];
7081 	u8			numclks;
82
+	u32			sent_packets;
83
+	u32			vsec_offset;
84
+	const struct cvp_priv	*priv;
7185 };
86
+
87
+struct cvp_priv {
88
+	void	(*switch_clk)(struct altera_cvp_conf *conf);
89
+	int	(*clear_state)(struct altera_cvp_conf *conf);
90
+	int	(*wait_credit)(struct fpga_manager *mgr, u32 blocks);
91
+	size_t	block_size;
92
+	int	poll_time_us;
93
+	int	user_time_us;
94
+};
95
+
96
+static int altera_read_config_byte(struct altera_cvp_conf *conf,
97
+				   int where, u8 *val)
98
+{
99
+	return pci_read_config_byte(conf->pci_dev, conf->vsec_offset + where,
100
+				    val);
101
+}
102
+
103
+static int altera_read_config_dword(struct altera_cvp_conf *conf,
104
+				    int where, u32 *val)
105
+{
106
+	return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
107
+				     val);
108
+}
109
+
110
+static int altera_write_config_dword(struct altera_cvp_conf *conf,
111
+				     int where, u32 val)
112
+{
113
+	return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
114
+				      val);
115
+}
72116 
73117 static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
74118 {
75119 	struct altera_cvp_conf *conf = mgr->priv;
76120 	u32 status;
77121 
78
-	pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &status);
122
+	altera_read_config_dword(conf, VSE_CVP_STATUS, &status);
79123 
80124 	if (status & VSE_CVP_STATUS_CFG_DONE)
81125 		return FPGA_MGR_STATE_OPERATING;
....@@ -93,7 +137,8 @@
93137 
94138 static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
95139 {
96
-	pci_write_config_dword(conf->pci_dev, VSE_CVP_DATA, val);
140
+	pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
141
+			       val);
97142 }
98143 
99144 /* switches between CvP clock and internal clock */
....@@ -103,10 +148,10 @@
103148 	u32 val;
104149 
105150 	/* set 1 CVP clock cycle for every CVP Data Register Write */
106
-	pci_read_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, &val);
151
+	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
107152 	val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
108153 	val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
109
-	pci_write_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, val);
154
+	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
110155 
111156 	for (i = 0; i < CVP_DUMMY_WR; i++)
112157 		conf->write_data(conf, 0); /* dummy data, could be any value */
....@@ -123,7 +168,7 @@
123168 		retries++;
124169 
125170 	do {
126
-		pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val);
171
+		altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
127172 		if ((val & status_mask) == status_val)
128173 			return 0;
129174 
....@@ -134,32 +179,136 @@
134179 	return -ETIMEDOUT;
135180 }
136181 
182
+static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
183
+{
184
+	struct altera_cvp_conf *conf = mgr->priv;
185
+	u32 val;
186
+	int ret;
187
+
188
+	/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
189
+	ret = altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
190
+	if (ret || (val & VSE_CVP_STATUS_CFG_ERR)) {
191
+		dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
192
+			bytes);
193
+		return -EPROTO;
194
+	}
195
+	return 0;
196
+}
197
+
198
+/*
199
+ * CvP Version2 Functions
200
+ * Recent Intel FPGAs use a credit mechanism to throttle incoming
201
+ * bitstreams and a different method of clearing the state.
202
+ */
203
+
204
+static int altera_cvp_v2_clear_state(struct altera_cvp_conf *conf)
205
+{
206
+	u32 val;
207
+	int ret;
208
+
209
+	/* Clear the START_XFER and CVP_CONFIG bits */
210
+	ret = altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
211
+	if (ret) {
212
+		dev_err(&conf->pci_dev->dev,
213
+			"Error reading CVP Program Control Register\n");
214
+		return ret;
215
+	}
216
+
217
+	val &= ~VSE_CVP_PROG_CTRL_MASK;
218
+	ret = altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
219
+	if (ret) {
220
+		dev_err(&conf->pci_dev->dev,
221
+			"Error writing CVP Program Control Register\n");
222
+		return ret;
223
+	}
224
+
225
+	return altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
226
+				      conf->priv->poll_time_us);
227
+}
228
+
229
+static int altera_cvp_v2_wait_for_credit(struct fpga_manager *mgr,
230
+					 u32 blocks)
231
+{
232
+	u32 timeout = V2_CREDIT_TIMEOUT_US / V2_CHECK_CREDIT_US;
233
+	struct altera_cvp_conf *conf = mgr->priv;
234
+	int ret;
235
+	u8 val;
236
+
237
+	do {
238
+		ret = altera_read_config_byte(conf, VSE_CVP_TX_CREDITS, &val);
239
+		if (ret) {
240
+			dev_err(&conf->pci_dev->dev,
241
+				"Error reading CVP Credit Register\n");
242
+			return ret;
243
+		}
244
+
245
+		/* Return if there is space in FIFO */
246
+		if (val - (u8)conf->sent_packets)
247
+			return 0;
248
+
249
+		ret = altera_cvp_chk_error(mgr, blocks * ALTERA_CVP_V2_SIZE);
250
+		if (ret) {
251
+			dev_err(&conf->pci_dev->dev,
252
+				"CE Bit error credit reg[0x%x]:sent[0x%x]\n",
253
+				val, conf->sent_packets);
254
+			return -EAGAIN;
255
+		}
256
+
257
+		/* Limit the check credit byte traffic */
258
+		usleep_range(V2_CHECK_CREDIT_US, V2_CHECK_CREDIT_US + 1);
259
+	} while (timeout--);
260
+
261
+	dev_err(&conf->pci_dev->dev, "Timeout waiting for credit\n");
262
+	return -ETIMEDOUT;
263
+}
264
+
265
+static int altera_cvp_send_block(struct altera_cvp_conf *conf,
266
+				 const u32 *data, size_t len)
267
+{
268
+	u32 mask, words = len / sizeof(u32);
269
+	int i, remainder;
270
+
271
+	for (i = 0; i < words; i++)
272
+		conf->write_data(conf, *data++);
273
+
274
+	/* write up to 3 trailing bytes, if any */
275
+	remainder = len % sizeof(u32);
276
+	if (remainder) {
277
+		mask = BIT(remainder * 8) - 1;
278
+		if (mask)
279
+			conf->write_data(conf, *data & mask);
280
+	}
281
+
282
+	return 0;
283
+}
284
+
137285 static int altera_cvp_teardown(struct fpga_manager *mgr,
138286 			       struct fpga_image_info *info)
139287 {
140288 	struct altera_cvp_conf *conf = mgr->priv;
141
-	struct pci_dev *pdev = conf->pci_dev;
142289 	int ret;
143290 	u32 val;
144291 
145292 	/* STEP 12 - reset START_XFER bit */
146
-	pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
293
+	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
147294 	val &= ~VSE_CVP_PROG_CTRL_START_XFER;
148
-	pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
295
+	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
149296 
150297 	/* STEP 13 - reset CVP_CONFIG bit */
151298 	val &= ~VSE_CVP_PROG_CTRL_CONFIG;
152
-	pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
299
+	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
153300 
154301 	/*
155302 	 * STEP 14
156303 	 * - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
157304 	 *   writes to the HIP
158305 	 */
159
-	altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */
306
+	if (conf->priv->switch_clk)
307
+		conf->priv->switch_clk(conf);
160308 
161309 	/* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
162
-	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10);
310
+	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
311
+				     conf->priv->poll_time_us);
163312 	if (ret)
164313 		dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
165314 
....@@ -171,7 +320,6 @@
171320 				 const char *buf, size_t count)
172321 {
173322 	struct altera_cvp_conf *conf = mgr->priv;
174
-	struct pci_dev *pdev = conf->pci_dev;
175323 	u32 iflags, val;
176324 	int ret;
177325 
....@@ -191,7 +339,7 @@
191339 		conf->numclks = 1; /* for uncompressed and unencrypted images */
192340 
193341 	/* STEP 1 - read CVP status and check CVP_EN flag */
194
-	pci_read_config_dword(pdev, VSE_CVP_STATUS, &val);
342
+	altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
195343 	if (!(val & VSE_CVP_STATUS_CVP_EN)) {
196344 		dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
197345 		return -ENODEV;
....@@ -209,30 +357,42 @@
209357 	 * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
210358 	 */
211359 	/* switch from fabric to PMA clock */
212
-	pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
360
+	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
213361 	val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
214
-	pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
362
+	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
215363 
216364 	/* set CVP mode */
217
-	pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
365
+	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
218366 	val |= VSE_CVP_MODE_CTRL_CVP_MODE;
219
-	pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
367
+	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
220368 
221369 	/*
222370 	 * STEP 3
223371 	 * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
224372 	 */
225
-	altera_cvp_dummy_write(conf);
373
+	if (conf->priv->switch_clk)
374
+		conf->priv->switch_clk(conf);
375
+
376
+	if (conf->priv->clear_state) {
377
+		ret = conf->priv->clear_state(conf);
378
+		if (ret) {
379
+			dev_err(&mgr->dev, "Problem clearing out state\n");
380
+			return ret;
381
+		}
382
+	}
383
+
384
+	conf->sent_packets = 0;
226385 
227386 	/* STEP 4 - set CVP_CONFIG bit */
228
-	pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
387
+	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
229388 	/* request control block to begin transfer using CVP */
230389 	val |= VSE_CVP_PROG_CTRL_CONFIG;
231
-	pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
390
+	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
232391 
233
-	/* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
392
+	/* STEP 5 - poll CVP_CONFIG READY for 1 with timeout */
234393 	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
235
-				     VSE_CVP_STATUS_CFG_RDY, 10);
394
+				     VSE_CVP_STATUS_CFG_RDY,
395
+				     conf->priv->poll_time_us);
236396 	if (ret) {
237397 		dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
238398 		return ret;
....@@ -242,33 +402,28 @@
242402 	 * STEP 6
243403 	 * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
244404 	 */
245
-	altera_cvp_dummy_write(conf);
405
+	if (conf->priv->switch_clk)
406
+		conf->priv->switch_clk(conf);
407
+
408
+	if (altera_cvp_chkcfg) {
409
+		ret = altera_cvp_chk_error(mgr, 0);
410
+		if (ret) {
411
+			dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
412
+			return ret;
413
+		}
414
+	}
246415 
247416 	/* STEP 7 - set START_XFER */
248
-	pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
417
+	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
249418 	val |= VSE_CVP_PROG_CTRL_START_XFER;
250
-	pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
419
+	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
251420 
252421 	/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
253
-	pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
254
-	val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
255
-	val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
256
-	pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
257
-
258
-	return 0;
259
-}
260
-
261
-static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
262
-{
263
-	struct altera_cvp_conf *conf = mgr->priv;
264
-	u32 val;
265
-
266
-	/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
267
-	pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val);
268
-	if (val & VSE_CVP_STATUS_CFG_ERR) {
269
-		dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
270
-			bytes);
271
-		return -EPROTO;
422
+	if (conf->priv->switch_clk) {
423
+		altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
424
+		val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
425
+		val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
426
+		altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
272427 	}
273428 	return 0;
274429 }
....@@ -277,20 +432,32 @@
277432 			    size_t count)
278433 {
279434 	struct altera_cvp_conf *conf = mgr->priv;
435
+	size_t done, remaining, len;
280436 	const u32 *data;
281
-	size_t done, remaining;
282437 	int status = 0;
283
-	u32 mask;
284438 
285439 	/* STEP 9 - write 32-bit data from RBF file to CVP data register */
286440 	data = (u32 *)buf;
287441 	remaining = count;
288442 	done = 0;
289443 
290
-	while (remaining >= 4) {
291
-		conf->write_data(conf, *data++);
292
-		done += 4;
293
-		remaining -= 4;
444
+	while (remaining) {
445
+		/* Use credit throttling if available */
446
+		if (conf->priv->wait_credit) {
447
+			status = conf->priv->wait_credit(mgr, done);
448
+			if (status) {
449
+				dev_err(&conf->pci_dev->dev,
450
+					"Wait Credit ERR: 0x%x\n", status);
451
+				return status;
452
+			}
453
+		}
454
+
455
+		len = min(conf->priv->block_size, remaining);
456
+		altera_cvp_send_block(conf, data, len);
457
+		data += len / sizeof(u32);
458
+		done += len;
459
+		remaining -= len;
460
+		conf->sent_packets++;
294461 
295462 		/*
296463 		 * STEP 10 (optional) and STEP 11
....@@ -308,11 +475,6 @@
308475 		}
309476 	}
310477 
311
-	/* write up to 3 trailing bytes, if any */
312
-	mask = BIT(remaining * 8) - 1;
313
-	if (mask)
314
-		conf->write_data(conf, *data & mask);
315
-
316478 	if (altera_cvp_chkcfg)
317479 		status = altera_cvp_chk_error(mgr, count);
318480 
....@@ -323,31 +485,30 @@
323485 				     struct fpga_image_info *info)
324486 {
325487 	struct altera_cvp_conf *conf = mgr->priv;
326
-	struct pci_dev *pdev = conf->pci_dev;
488
+	u32 mask, val;
327489 	int ret;
328
-	u32 mask;
329
-	u32 val;
330490 
331491 	ret = altera_cvp_teardown(mgr, info);
332492 	if (ret)
333493 		return ret;
334494 
335495 	/* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
336
-	pci_read_config_dword(pdev, VSE_UNCOR_ERR_STATUS, &val);
496
+	altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
337497 	if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
338498 		dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
339499 		return -EPROTO;
340500 	}
341501 
342502 	/* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
343
-	pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
503
+	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
344504 	val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
345505 	val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
346
-	pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
506
+	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
347507 
348508 	/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
349509 	mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
350
-	ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US);
510
+	ret = altera_cvp_wait_status(conf, mask, mask,
511
+				     conf->priv->user_time_us);
351512 	if (ret)
352513 		dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
353514 
....@@ -359,6 +520,21 @@
359520 	.write_init	= altera_cvp_write_init,
360521 	.write		= altera_cvp_write,
361522 	.write_complete	= altera_cvp_write_complete,
523
+};
524
+
525
+static const struct cvp_priv cvp_priv_v1 = {
526
+	.switch_clk	= altera_cvp_dummy_write,
527
+	.block_size	= ALTERA_CVP_V1_SIZE,
528
+	.poll_time_us	= V1_POLL_TIMEOUT_US,
529
+	.user_time_us	= TIMEOUT_US,
530
+};
531
+
532
+static const struct cvp_priv cvp_priv_v2 = {
533
+	.clear_state	= altera_cvp_v2_clear_state,
534
+	.wait_credit	= altera_cvp_v2_wait_for_credit,
535
+	.block_size	= ALTERA_CVP_V2_SIZE,
536
+	.poll_time_us	= V2_POLL_TIMEOUT_US,
537
+	.user_time_us	= V2_USER_TIMEOUT_US,
362538 };
363539 
364540 static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
....@@ -402,22 +578,29 @@
402578 {
403579 	struct altera_cvp_conf *conf;
404580 	struct fpga_manager *mgr;
581
+	int ret, offset;
405582 	u16 cmd, val;
406583 	u32 regval;
407
-	int ret;
584
+
585
+	/* Discover the Vendor Specific Offset for this device */
586
+	offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
587
+	if (!offset) {
588
+		dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
589
+		return -ENODEV;
590
+	}
408591 
409592 	/*
410593 	 * First check if this is the expected FPGA device. PCI config
411594 	 * space access works without enabling the PCI device, memory
412595 	 * space access is enabled further down.
413596 	 */
414
-	pci_read_config_word(pdev, VSE_PCIE_EXT_CAP_ID, &val);
597
+	pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
415598 	if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
416599 		dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
417600 		return -ENODEV;
418601 	}
419602 
420
-	pci_read_config_dword(pdev, VSE_CVP_STATUS, &regval);
603
+	pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, &regval);
421604 	if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
422605 		dev_err(&pdev->dev,
423606 			"CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
....@@ -428,6 +611,8 @@
428611 	conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
429612 	if (!conf)
430613 		return -ENOMEM;
614
+
615
+	conf->vsec_offset = offset;
431616 
432617 	/*
433618 	 * Enable memory BAR access. We cannot use pci_enable_device() here
....@@ -453,6 +638,11 @@
453638 	conf->pci_dev = pdev;
454639 	conf->write_data = altera_cvp_write_data_iomem;
455640 
641
+	if (conf->vsec_offset == V1_VSEC_OFFSET)
642
+		conf->priv = &cvp_priv_v1;
643
+	else
644
+		conf->priv = &cvp_priv_v2;
645
+
456646 	conf->map = pci_iomap(pdev, CVP_BAR, 0);
457647 	if (!conf->map) {
458648 		dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
....@@ -462,8 +652,8 @@
462652 	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
463653 		 ALTERA_CVP_MGR_NAME, pci_name(pdev));
464654 
465
-	mgr = fpga_mgr_create(&pdev->dev, conf->mgr_name,
466
-			      &altera_cvp_ops, conf);
655
+	mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
656
+				   &altera_cvp_ops, conf);
467657 	if (!mgr) {
468658 		ret = -ENOMEM;
469659 		goto err_unmap;
....@@ -472,10 +662,8 @@
472662 	pci_set_drvdata(pdev, mgr);
473663 
474664 	ret = fpga_mgr_register(mgr);
475
-	if (ret) {
476
-		fpga_mgr_free(mgr);
665
+	if (ret)
477666 		goto err_unmap;
478
-	}
479667 
480668 	return 0;
481669