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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Driver for OHCI 1394 controllers |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License as published by |
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| 8 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 9 | | - * (at your option) any later version. |
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| 10 | | - * |
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| 11 | | - * This program is distributed in the hope that it will be useful, |
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| 12 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 14 | | - * GNU General Public License for more details. |
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| 15 | | - * |
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| 16 | | - * You should have received a copy of the GNU General Public License |
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| 17 | | - * along with this program; if not, write to the Free Software Foundation, |
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| 18 | | - * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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| 19 | 6 | */ |
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| 20 | 7 | |
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| 21 | 8 | #include <linux/bitops.h> |
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| .. | .. |
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| 124 | 111 | dma_addr_t buffer_bus; |
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| 125 | 112 | size_t buffer_size; |
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| 126 | 113 | size_t used; |
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| 127 | | - struct descriptor buffer[0]; |
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| 114 | + struct descriptor buffer[]; |
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| 128 | 115 | }; |
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| 129 | 116 | |
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| 130 | 117 | struct context { |
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| .. | .. |
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| 687 | 674 | |
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| 688 | 675 | static void ar_context_release(struct ar_context *ctx) |
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| 689 | 676 | { |
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| 677 | + struct device *dev = ctx->ohci->card.device; |
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| 690 | 678 | unsigned int i; |
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| 691 | 679 | |
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| 692 | 680 | vunmap(ctx->buffer); |
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| 693 | 681 | |
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| 694 | | - for (i = 0; i < AR_BUFFERS; i++) |
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| 695 | | - if (ctx->pages[i]) { |
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| 696 | | - dma_unmap_page(ctx->ohci->card.device, |
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| 697 | | - ar_buffer_bus(ctx, i), |
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| 698 | | - PAGE_SIZE, DMA_FROM_DEVICE); |
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| 699 | | - __free_page(ctx->pages[i]); |
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| 700 | | - } |
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| 682 | + for (i = 0; i < AR_BUFFERS; i++) { |
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| 683 | + if (ctx->pages[i]) |
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| 684 | + dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], |
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| 685 | + ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); |
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| 686 | + } |
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| 701 | 687 | } |
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| 702 | 688 | |
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| 703 | 689 | static void ar_context_abort(struct ar_context *ctx, const char *error_msg) |
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| .. | .. |
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| 983 | 969 | static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, |
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| 984 | 970 | unsigned int descriptors_offset, u32 regs) |
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| 985 | 971 | { |
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| 972 | + struct device *dev = ohci->card.device; |
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| 986 | 973 | unsigned int i; |
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| 987 | 974 | dma_addr_t dma_addr; |
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| 988 | 975 | struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; |
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| .. | .. |
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| 993 | 980 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
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| 994 | 981 | |
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| 995 | 982 | for (i = 0; i < AR_BUFFERS; i++) { |
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| 996 | | - ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); |
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| 983 | + ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, |
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| 984 | + DMA_FROM_DEVICE, GFP_KERNEL); |
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| 997 | 985 | if (!ctx->pages[i]) |
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| 998 | 986 | goto out_of_memory; |
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| 999 | | - dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], |
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| 1000 | | - 0, PAGE_SIZE, DMA_FROM_DEVICE); |
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| 1001 | | - if (dma_mapping_error(ohci->card.device, dma_addr)) { |
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| 1002 | | - __free_page(ctx->pages[i]); |
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| 1003 | | - ctx->pages[i] = NULL; |
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| 1004 | | - goto out_of_memory; |
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| 1005 | | - } |
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| 1006 | 987 | set_page_private(ctx->pages[i], dma_addr); |
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| 988 | + dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, |
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| 989 | + DMA_FROM_DEVICE); |
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| 1007 | 990 | } |
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| 1008 | 991 | |
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| 1009 | 992 | for (i = 0; i < AR_BUFFERS; i++) |
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| .. | .. |
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| 1112 | 1095 | static int context_add_buffer(struct context *ctx) |
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| 1113 | 1096 | { |
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| 1114 | 1097 | struct descriptor_buffer *desc; |
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| 1115 | | - dma_addr_t uninitialized_var(bus_addr); |
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| 1098 | + dma_addr_t bus_addr; |
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| 1116 | 1099 | int offset; |
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| 1117 | 1100 | |
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| 1118 | 1101 | /* |
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| .. | .. |
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| 1302 | 1285 | struct fw_packet *packet) |
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| 1303 | 1286 | { |
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| 1304 | 1287 | struct fw_ohci *ohci = ctx->ohci; |
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| 1305 | | - dma_addr_t d_bus, uninitialized_var(payload_bus); |
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| 1288 | + dma_addr_t d_bus, payload_bus; |
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| 1306 | 1289 | struct driver_data *driver_data; |
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| 1307 | 1290 | struct descriptor *d, *last; |
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| 1308 | 1291 | __le32 *header; |
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| .. | .. |
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| 1508 | 1491 | packet->ack = RCODE_GENERATION; |
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| 1509 | 1492 | break; |
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| 1510 | 1493 | } |
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| 1511 | | - /* fall through */ |
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| 1494 | + fallthrough; |
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| 1512 | 1495 | |
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| 1513 | 1496 | default: |
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| 1514 | 1497 | packet->ack = RCODE_SEND_ERROR; |
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| .. | .. |
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| 1765 | 1748 | |
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| 1766 | 1749 | if (unlikely(!ohci->bus_time_running)) { |
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| 1767 | 1750 | reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); |
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| 1768 | | - ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) | |
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| 1751 | + ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | |
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| 1769 | 1752 | (cycle_time_seconds & 0x40); |
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| 1770 | 1753 | ohci->bus_time_running = true; |
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| 1771 | 1754 | } |
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| .. | .. |
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| 2458 | 2441 | { |
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| 2459 | 2442 | struct fw_ohci *ohci; |
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| 2460 | 2443 | __be32 *next_config_rom; |
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| 2461 | | - dma_addr_t uninitialized_var(next_config_rom_bus); |
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| 2444 | + dma_addr_t next_config_rom_bus; |
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| 2462 | 2445 | |
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| 2463 | 2446 | ohci = fw_ohci(card); |
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| 2464 | 2447 | |
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| .. | .. |
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| 2939 | 2922 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); |
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| 2940 | 2923 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); |
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| 2941 | 2924 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); |
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| 2942 | | - mmiowb(); |
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| 2943 | 2925 | ohci->mc_channels = channels; |
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| 2944 | 2926 | } |
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| 2945 | 2927 | |
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| .. | .. |
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| 2947 | 2929 | int type, int channel, size_t header_size) |
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| 2948 | 2930 | { |
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| 2949 | 2931 | struct fw_ohci *ohci = fw_ohci(card); |
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| 2950 | | - struct iso_context *uninitialized_var(ctx); |
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| 2951 | | - descriptor_callback_t uninitialized_var(callback); |
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| 2952 | | - u64 *uninitialized_var(channels); |
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| 2953 | | - u32 *uninitialized_var(mask), uninitialized_var(regs); |
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| 2932 | + struct iso_context *ctx; |
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| 2933 | + descriptor_callback_t callback; |
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| 2934 | + u64 *channels; |
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| 2935 | + u32 *mask, regs; |
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| 2954 | 2936 | int index, ret = -EBUSY; |
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| 2955 | 2937 | |
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| 2956 | 2938 | spin_lock_irq(&ohci->lock); |
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| .. | .. |
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| 3068 | 3050 | |
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| 3069 | 3051 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: |
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| 3070 | 3052 | control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; |
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| 3071 | | - /* fall through */ |
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| 3053 | + fallthrough; |
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| 3072 | 3054 | case FW_ISO_CONTEXT_RECEIVE: |
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| 3073 | 3055 | index = ctx - ohci->ir_context_list; |
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| 3074 | 3056 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
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