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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/edac/altera_edac.h
....@@ -156,34 +156,6 @@
156156 #define A10_INTMASK_CLR_OFST       0x10
157157 #define A10_DDR0_IRQ_MASK          BIT(17)
158158 
159
-/************* Stratix10 Defines **************/
160
-
161
-/* SDRAM Controller EccCtrl Register */
162
-#define S10_ECCCTRL1_OFST          0xF8011100
163
-
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-/* SDRAM Controller DRAM IRQ Register */
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-#define S10_ERRINTEN_OFST          0xF8011110
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-
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-/* SDRAM Interrupt Mode Register */
168
-#define S10_INTMODE_OFST           0xF801111C
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-
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-/* SDRAM Controller Error Status Register */
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-#define S10_INTSTAT_OFST           0xF8011120
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-
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-/* SDRAM Controller ECC Error Address Register */
174
-#define S10_DERRADDR_OFST          0xF801112C
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-#define S10_SERRADDR_OFST          0xF8011130
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-
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-/* SDRAM Controller ECC Diagnostic Register */
178
-#define S10_DIAGINTTEST_OFST       0xF8011124
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-
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-/* SDRAM Single Bit Error Count Compare Set Register */
181
-#define S10_SERRCNTREG_OFST        0xF801113C
182
-
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-/* Sticky registers for Uncorrected Errors */
184
-#define S10_SYSMGR_UE_VAL_OFST     0xFFD12220
185
-#define S10_SYSMGR_UE_ADDR_OFST    0xFFD12224
186
-
187159 struct altr_sdram_prv_data {
188160 	int ecc_ctrl_offset;
189161 	int ecc_ctl_en_mask;
....@@ -317,16 +289,66 @@
317289 #define ALTR_A10_ECC_INIT_WATCHDOG_10US      10000
318290 
319291 /************* Stratix10 Defines **************/
292
+#define ALTR_S10_ECC_CTRL_SDRAM_OFST      0x00
293
+#define ALTR_S10_ECC_EN                   BIT(0)
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+
295
+#define ALTR_S10_ECC_ERRINTEN_OFST        0x10
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+#define ALTR_S10_ECC_ERRINTENS_OFST       0x14
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+#define ALTR_S10_ECC_ERRINTENR_OFST       0x18
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+#define ALTR_S10_ECC_SERRINTEN            BIT(0)
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+
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+#define ALTR_S10_ECC_INTMODE_OFST         0x1C
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+#define ALTR_S10_ECC_INTMODE              BIT(0)
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+
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+#define ALTR_S10_ECC_INTSTAT_OFST         0x20
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+#define ALTR_S10_ECC_SERRPENA             BIT(0)
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+#define ALTR_S10_ECC_DERRPENA             BIT(8)
306
+#define ALTR_S10_ECC_ERRPENA_MASK         (ALTR_S10_ECC_SERRPENA | \
307
+					   ALTR_S10_ECC_DERRPENA)
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+
309
+#define ALTR_S10_ECC_INTTEST_OFST         0x24
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+#define ALTR_S10_ECC_TSERRA               BIT(0)
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+#define ALTR_S10_ECC_TDERRA               BIT(8)
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+#define ALTR_S10_ECC_TSERRB               BIT(16)
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+#define ALTR_S10_ECC_TDERRB               BIT(24)
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+
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+#define ALTR_S10_DERR_ADDRA_OFST          0x2C
320316 
321317 /* Stratix10 ECC Manager Defines */
322
-#define S10_SYSMGR_ECC_INTMASK_VAL_OFST   0xFFD12090
323
-#define S10_SYSMGR_ECC_INTMASK_SET_OFST   0xFFD12094
324
-#define S10_SYSMGR_ECC_INTMASK_CLR_OFST   0xFFD12098
318
+#define S10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98
319
+#define S10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0
325320 
326
-#define S10_SYSMGR_ECC_INTSTAT_SERR_OFST  0xFFD1209C
327
-#define S10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xFFD120A0
321
+/* Sticky registers for Uncorrected Errors */
322
+#define S10_SYSMGR_UE_VAL_OFST            0x220
323
+#define S10_SYSMGR_UE_ADDR_OFST           0x224
328324 
329325 #define S10_DDR0_IRQ_MASK                 BIT(16)
326
+#define S10_DBE_IRQ_MASK                  0x3FFFE
327
+
328
+/* Define ECC Block Offsets for peripherals */
329
+#define ECC_BLK_ADDRESS_OFST              0x40
330
+#define ECC_BLK_RDATA0_OFST               0x44
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+#define ECC_BLK_RDATA1_OFST               0x48
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+#define ECC_BLK_RDATA2_OFST               0x4C
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+#define ECC_BLK_RDATA3_OFST               0x50
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+#define ECC_BLK_WDATA0_OFST               0x54
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+#define ECC_BLK_WDATA1_OFST               0x58
336
+#define ECC_BLK_WDATA2_OFST               0x5C
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+#define ECC_BLK_WDATA3_OFST               0x60
338
+#define ECC_BLK_RECC0_OFST                0x64
339
+#define ECC_BLK_RECC1_OFST                0x68
340
+#define ECC_BLK_WECC0_OFST                0x6C
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+#define ECC_BLK_WECC1_OFST                0x70
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+#define ECC_BLK_DBYTECTRL_OFST            0x74
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+#define ECC_BLK_ACCCTRL_OFST              0x78
344
+#define ECC_BLK_STARTACC_OFST             0x7C
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+
346
+#define ECC_XACT_KICK                     0x10000
347
+#define ECC_WORD_WRITE                    0xFF
348
+#define ECC_WRITE_DOVR                    0x101
349
+#define ECC_WRITE_EDOVR                   0x103
350
+#define ECC_READ_EOVR                     0x2
351
+#define ECC_READ_EDOVR                    0x3
330352 
331353 struct altr_edac_device_dev;
332354 
....@@ -370,79 +392,6 @@
370392 	struct irq_domain	*domain;
371393 	struct irq_chip		irq_chip;
372394 	struct list_head	a10_ecc_devices;
373
-};
374
-
375
-/*
376
- * Functions specified by ARM SMC Calling convention:
377
- *
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- * FAST call executes atomic operations, returns when the requested operation
379
- * has completed.
380
- * STD call starts a operation which can be preempted by a non-secure
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- * interrupt. The call can return before the requested operation has
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- * completed.
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- *
384
- * a0..a7 is used as register names in the descriptions below, on arm32
385
- * that translates to r0..r7 and on arm64 to w0..w7.
386
- */
387
-
388
-#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
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-	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
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-	ARM_SMCCC_OWNER_SIP, (func_num))
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-
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-#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
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-	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
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-	ARM_SMCCC_OWNER_SIP, (func_num))
395
-
396
-#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION		0xFFFFFFFF
397
-#define INTEL_SIP_SMC_STATUS_OK				0x0
398
-#define INTEL_SIP_SMC_REG_ERROR				0x5
399
-
400
-/*
401
- * Request INTEL_SIP_SMC_REG_READ
402
- *
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- * Read a protected register using SMCCC
404
- *
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- * Call register usage:
406
- * a0: INTEL_SIP_SMC_REG_READ.
407
- * a1: register address.
408
- * a2-7: not used.
409
- *
410
- * Return status:
411
- * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
412
- *     INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
413
- * a1: Value in the register
414
- * a2-3: not used.
415
- */
416
-#define INTEL_SIP_SMC_FUNCID_REG_READ 7
417
-#define INTEL_SIP_SMC_REG_READ \
418
-	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
419
-
420
-/*
421
- * Request INTEL_SIP_SMC_REG_WRITE
422
- *
423
- * Write a protected register using SMCCC
424
- *
425
- * Call register usage:
426
- * a0: INTEL_SIP_SMC_REG_WRITE.
427
- * a1: register address
428
- * a2: value to program into register.
429
- * a3-7: not used.
430
- *
431
- * Return status:
432
- * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
433
- *     INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
434
- * a1-3: not used.
435
- */
436
-#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
437
-#define INTEL_SIP_SMC_REG_WRITE \
438
-	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
439
-
440
-struct altr_stratix10_edac {
441
-	struct device		*dev;
442
-	int sb_irq;
443
-	struct irq_domain	*domain;
444
-	struct irq_chip		irq_chip;
445
-	struct list_head	s10_ecc_devices;
446395 	struct notifier_block	panic_notifier;
447396 };
448397