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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/edac/Kconfig
....@@ -44,7 +44,7 @@
4444 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
4545 	depends on CPU_SUP_AMD && X86_MCE_AMD
4646 	default y
47
-	---help---
47
+	help
4848 	  Enable this option if you want to decode Machine Check Exceptions
4949 	  occurring on your machine in human-readable form.
5050 
....@@ -99,6 +99,13 @@
9999 
100100 	  In addition, there are two control files, inject_read and inject_write,
101101 	  which trigger the DRAM ECC Read and Write respectively.
102
+
103
+config EDAC_AL_MC
104
+	tristate "Amazon's Annapurna Lab Memory Controller"
105
+	depends on (ARCH_ALPINE || COMPILE_TEST)
106
+	help
107
+	  Support for error detection and correction for Amazon's Annapurna
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+	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.
102109 
103110 config EDAC_AMD76X
104111 	tristate "AMD 76x (760, 762, 768)"
....@@ -231,12 +238,25 @@
231238 
232239 config EDAC_SKX
233240 	tristate "Intel Skylake server Integrated MC"
234
-	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
241
+	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
235242 	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
236243 	select DMI
244
+	select ACPI_ADXL
237245 	help
238246 	  Support for error detection and correction the Intel
239247 	  Skylake server Integrated Memory Controllers. If your
248
+	  system has non-volatile DIMMs you should also manually
249
+	  select CONFIG_ACPI_NFIT.
250
+
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+config EDAC_I10NM
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+	tristate "Intel 10nm server Integrated MC"
253
+	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
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+	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
255
+	select DMI
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+	select ACPI_ADXL
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+	help
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+	  Support for error detection and correction the Intel
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+	  10nm server Integrated Memory Controllers. If your
240260 	  system has non-volatile DIMMs you should also manually
241261 	  select CONFIG_ACPI_NFIT.
242262 
....@@ -378,9 +398,17 @@
378398 	depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
379399 	help
380400 	  Support for error detection and correction on the
381
-	  Altera SOCs. This must be selected for SDRAM ECC.
382
-	  Note that the preloader must initialize the SDRAM
383
-	  before loading the kernel.
401
+	  Altera SOCs. This is the global enable for the
402
+	  various Altera peripherals.
403
+
404
+config EDAC_ALTERA_SDRAM
405
+	bool "Altera SDRAM ECC"
406
+	depends on EDAC_ALTERA=y
407
+	help
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+	  Support for error detection and correction on the
409
+	  Altera SDRAM Memory for Altera SoCs. Note that the
410
+	  preloader must initialize the SDRAM before loading
411
+	  the kernel.
384412 
385413 config EDAC_ALTERA_L2C
386414 	bool "Altera L2 Cache ECC"
....@@ -439,9 +467,22 @@
439467 	  Support for error detection and correction on the
440468 	  Altera SDMMC FIFO Memory for Altera SoCs.
441469 
470
+config EDAC_SIFIVE
471
+	bool "Sifive platform EDAC driver"
472
+	depends on EDAC=y && SIFIVE_L2
473
+	help
474
+	  Support for error detection and correction on the SiFive SoCs.
475
+
476
+config EDAC_ARMADA_XP
477
+	bool "Marvell Armada XP DDR and L2 Cache ECC"
478
+	depends on MACH_MVEBU_V7
479
+	help
480
+	  Support for error correction and detection on the Marvell Aramada XP
481
+	  DDR RAM and L2 cache controllers.
482
+
442483 config EDAC_SYNOPSYS
443484 	tristate "Synopsys DDR Memory Controller"
444
-	depends on ARCH_ZYNQ
485
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP
445486 	help
446487 	  Support for error detection and correction on the Synopsys DDR
447488 	  memory controller.
....@@ -457,7 +498,50 @@
457498 	tristate "Texas Instruments DDR3 ECC Controller"
458499 	depends on ARCH_KEYSTONE || SOC_DRA7XX
459500 	help
501
+	  Support for error detection and correction on the TI SoCs.
502
+
503
+config EDAC_QCOM
504
+	tristate "QCOM EDAC Controller"
505
+	depends on ARCH_QCOM && QCOM_LLCC
506
+	help
460507 	  Support for error detection and correction on the
461
-          TI SoCs.
508
+	  Qualcomm Technologies, Inc. SoCs.
509
+
510
+	  This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
511
+	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
512
+	  of Tag RAM and Data RAM.
513
+
514
+	  For debugging issues having to do with stability and overall system
515
+	  health, you should probably say 'Y' here.
516
+
517
+config EDAC_ASPEED
518
+	tristate "Aspeed AST 2500 SoC"
519
+	depends on MACH_ASPEED_G5
520
+	help
521
+	  Support for error detection and correction on the Aspeed AST 2500 SoC.
522
+
523
+	  First, ECC must be configured in the bootloader. Then, this driver
524
+	  will expose error counters via the EDAC kernel framework.
525
+
526
+config EDAC_BLUEFIELD
527
+	tristate "Mellanox BlueField Memory ECC"
528
+	depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
529
+	help
530
+	  Support for error detection and correction on the
531
+	  Mellanox BlueField SoCs.
532
+
533
+config EDAC_DMC520
534
+	tristate "ARM DMC-520 ECC"
535
+	depends on ARM64
536
+	help
537
+	  Support for error detection and correction on the
538
+	  SoCs with ARM DMC-520 DRAM controller.
539
+
540
+config EDAC_ROCKCHIP
541
+	tristate "Rockchip DDR ECC"
542
+	depends on ARCH_ROCKCHIP && HAVE_ARM_SMCCC
543
+	help
544
+	  Support for error detection and correction on the
545
+	  rockchip family of SOCs.
462546 
463547 endif # EDAC