forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/dma/sun6i-dma.c
....@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
34  * Author: Sugar <shuge@allwinnertech.com>
45  *
56  * Copyright (C) 2014 Maxime Ripard
67  * Maxime Ripard <maxime.ripard@free-electrons.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
128  */
139 
1410 #include <linux/clk.h>
....@@ -68,17 +64,20 @@
6864 #define DMA_CHAN_LLI_ADDR	0x08
6965 
7066 #define DMA_CHAN_CUR_CFG	0x0c
71
-#define DMA_CHAN_MAX_DRQ		0x1f
72
-#define DMA_CHAN_CFG_SRC_DRQ(x)		((x) & DMA_CHAN_MAX_DRQ)
73
-#define DMA_CHAN_CFG_SRC_IO_MODE	BIT(5)
74
-#define DMA_CHAN_CFG_SRC_LINEAR_MODE	(0 << 5)
67
+#define DMA_CHAN_MAX_DRQ_A31		0x1f
68
+#define DMA_CHAN_MAX_DRQ_H6		0x3f
69
+#define DMA_CHAN_CFG_SRC_DRQ_A31(x)	((x) & DMA_CHAN_MAX_DRQ_A31)
70
+#define DMA_CHAN_CFG_SRC_DRQ_H6(x)	((x) & DMA_CHAN_MAX_DRQ_H6)
71
+#define DMA_CHAN_CFG_SRC_MODE_A31(x)	(((x) & 0x1) << 5)
72
+#define DMA_CHAN_CFG_SRC_MODE_H6(x)	(((x) & 0x1) << 8)
7573 #define DMA_CHAN_CFG_SRC_BURST_A31(x)	(((x) & 0x3) << 7)
7674 #define DMA_CHAN_CFG_SRC_BURST_H3(x)	(((x) & 0x3) << 6)
7775 #define DMA_CHAN_CFG_SRC_WIDTH(x)	(((x) & 0x3) << 9)
7876 
79
-#define DMA_CHAN_CFG_DST_DRQ(x)		(DMA_CHAN_CFG_SRC_DRQ(x) << 16)
80
-#define DMA_CHAN_CFG_DST_IO_MODE	(DMA_CHAN_CFG_SRC_IO_MODE << 16)
81
-#define DMA_CHAN_CFG_DST_LINEAR_MODE	(DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
77
+#define DMA_CHAN_CFG_DST_DRQ_A31(x)	(DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
78
+#define DMA_CHAN_CFG_DST_DRQ_H6(x)	(DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
79
+#define DMA_CHAN_CFG_DST_MODE_A31(x)	(DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
80
+#define DMA_CHAN_CFG_DST_MODE_H6(x)	(DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
8281 #define DMA_CHAN_CFG_DST_BURST_A31(x)	(DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
8382 #define DMA_CHAN_CFG_DST_BURST_H3(x)	(DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
8483 #define DMA_CHAN_CFG_DST_WIDTH(x)	(DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
....@@ -98,6 +97,8 @@
9897 #define LLI_LAST_ITEM	0xfffff800
9998 #define NORMAL_WAIT	8
10099 #define DRQ_SDRAM	1
100
+#define LINEAR_MODE     0
101
+#define IO_MODE         1
101102 
102103 /* forward declaration */
103104 struct sun6i_dma_dev;
....@@ -125,10 +126,13 @@
125126 	 */
126127 	void (*clock_autogate_enable)(struct sun6i_dma_dev *);
127128 	void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
129
+	void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
130
+	void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
128131 	u32 src_burst_lengths;
129132 	u32 dst_burst_lengths;
130133 	u32 src_addr_widths;
131134 	u32 dst_addr_widths;
135
+	bool has_mbus_clk;
132136 };
133137 
134138 /*
....@@ -182,6 +186,7 @@
182186 	struct dma_device	slave;
183187 	void __iomem		*base;
184188 	struct clk		*clk;
189
+	struct clk		*clk_mbus;
185190 	int			irq;
186191 	spinlock_t		lock;
187192 	struct reset_control	*rstc;
....@@ -307,6 +312,30 @@
307312 {
308313 	*p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
309314 		  DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
315
+}
316
+
317
+static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
318
+{
319
+	*p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
320
+		  DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
321
+}
322
+
323
+static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
324
+{
325
+	*p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
326
+		  DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
327
+}
328
+
329
+static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
330
+{
331
+	*p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
332
+		  DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
333
+}
334
+
335
+static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
336
+{
337
+	*p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
338
+		  DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
310339 }
311340 
312341 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
....@@ -438,9 +467,9 @@
438467 	return 0;
439468 }
440469 
441
-static void sun6i_dma_tasklet(unsigned long data)
470
+static void sun6i_dma_tasklet(struct tasklet_struct *t)
442471 {
443
-	struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data;
472
+	struct sun6i_dma_dev *sdev = from_tasklet(sdev, t, task);
444473 	struct sun6i_vchan *vchan;
445474 	struct sun6i_pchan *pchan;
446475 	unsigned int pchan_alloc = 0;
....@@ -632,14 +661,12 @@
632661 
633662 	burst = convert_burst(8);
634663 	width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
635
-	v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
636
-		DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
637
-		DMA_CHAN_CFG_DST_LINEAR_MODE |
638
-		DMA_CHAN_CFG_SRC_LINEAR_MODE |
639
-		DMA_CHAN_CFG_SRC_WIDTH(width) |
664
+	v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
640665 		DMA_CHAN_CFG_DST_WIDTH(width);
641666 
642667 	sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
668
+	sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
669
+	sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
643670 
644671 	sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
645672 
....@@ -691,11 +718,9 @@
691718 		if (dir == DMA_MEM_TO_DEV) {
692719 			v_lli->src = sg_dma_address(sg);
693720 			v_lli->dst = sconfig->dst_addr;
694
-			v_lli->cfg = lli_cfg |
695
-				DMA_CHAN_CFG_DST_IO_MODE |
696
-				DMA_CHAN_CFG_SRC_LINEAR_MODE |
697
-				DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
698
-				DMA_CHAN_CFG_DST_DRQ(vchan->port);
721
+			v_lli->cfg = lli_cfg;
722
+			sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
723
+			sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
699724 
700725 			dev_dbg(chan2dev(chan),
701726 				"%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
....@@ -706,11 +731,9 @@
706731 		} else {
707732 			v_lli->src = sconfig->src_addr;
708733 			v_lli->dst = sg_dma_address(sg);
709
-			v_lli->cfg = lli_cfg |
710
-				DMA_CHAN_CFG_DST_LINEAR_MODE |
711
-				DMA_CHAN_CFG_SRC_IO_MODE |
712
-				DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
713
-				DMA_CHAN_CFG_SRC_DRQ(vchan->port);
734
+			v_lli->cfg = lli_cfg;
735
+			sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
736
+			sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
714737 
715738 			dev_dbg(chan2dev(chan),
716739 				"%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
....@@ -776,19 +799,15 @@
776799 		if (dir == DMA_MEM_TO_DEV) {
777800 			v_lli->src = buf_addr + period_len * i;
778801 			v_lli->dst = sconfig->dst_addr;
779
-			v_lli->cfg = lli_cfg |
780
-				DMA_CHAN_CFG_DST_IO_MODE |
781
-				DMA_CHAN_CFG_SRC_LINEAR_MODE |
782
-				DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
783
-				DMA_CHAN_CFG_DST_DRQ(vchan->port);
802
+			v_lli->cfg = lli_cfg;
803
+			sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
804
+			sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
784805 		} else {
785806 			v_lli->src = sconfig->src_addr;
786807 			v_lli->dst = buf_addr + period_len * i;
787
-			v_lli->cfg = lli_cfg |
788
-				DMA_CHAN_CFG_DST_LINEAR_MODE |
789
-				DMA_CHAN_CFG_SRC_IO_MODE |
790
-				DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
791
-				DMA_CHAN_CFG_SRC_DRQ(vchan->port);
808
+			v_lli->cfg = lli_cfg;
809
+			sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
810
+			sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
792811 		}
793812 
794813 		prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
....@@ -1053,6 +1072,8 @@
10531072 	.nr_max_requests = 30,
10541073 	.nr_max_vchans   = 53,
10551074 	.set_burst_length = sun6i_set_burst_length_a31,
1075
+	.set_drq          = sun6i_set_drq_a31,
1076
+	.set_mode         = sun6i_set_mode_a31,
10561077 	.src_burst_lengths = BIT(1) | BIT(8),
10571078 	.dst_burst_lengths = BIT(1) | BIT(8),
10581079 	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
....@@ -1074,6 +1095,8 @@
10741095 	.nr_max_vchans   = 37,
10751096 	.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
10761097 	.set_burst_length = sun6i_set_burst_length_a31,
1098
+	.set_drq          = sun6i_set_drq_a31,
1099
+	.set_mode         = sun6i_set_mode_a31,
10771100 	.src_burst_lengths = BIT(1) | BIT(8),
10781101 	.dst_burst_lengths = BIT(1) | BIT(8),
10791102 	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
....@@ -1090,6 +1113,8 @@
10901113 	.nr_max_vchans   = 39,
10911114 	.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
10921115 	.set_burst_length = sun6i_set_burst_length_a31,
1116
+	.set_drq          = sun6i_set_drq_a31,
1117
+	.set_mode         = sun6i_set_mode_a31,
10931118 	.src_burst_lengths = BIT(1) | BIT(8),
10941119 	.dst_burst_lengths = BIT(1) | BIT(8),
10951120 	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
....@@ -1113,6 +1138,8 @@
11131138 	.nr_max_vchans   = 34,
11141139 	.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
11151140 	.set_burst_length = sun6i_set_burst_length_h3,
1141
+	.set_drq          = sun6i_set_drq_a31,
1142
+	.set_mode         = sun6i_set_mode_a31,
11161143 	.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
11171144 	.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
11181145 	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
....@@ -1132,6 +1159,8 @@
11321159 static struct sun6i_dma_config sun50i_a64_dma_cfg = {
11331160 	.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
11341161 	.set_burst_length = sun6i_set_burst_length_h3,
1162
+	.set_drq          = sun6i_set_drq_a31,
1163
+	.set_mode         = sun6i_set_mode_a31,
11351164 	.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
11361165 	.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
11371166 	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
....@@ -1145,6 +1174,28 @@
11451174 };
11461175 
11471176 /*
1177
+ * The H6 binding uses the number of dma channels from the
1178
+ * device tree node.
1179
+ */
1180
+static struct sun6i_dma_config sun50i_h6_dma_cfg = {
1181
+	.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1182
+	.set_burst_length = sun6i_set_burst_length_h3,
1183
+	.set_drq          = sun6i_set_drq_h6,
1184
+	.set_mode         = sun6i_set_mode_h6,
1185
+	.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1186
+	.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1187
+	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1188
+			     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1189
+			     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1190
+			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1191
+	.dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1192
+			     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1193
+			     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1194
+			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1195
+	.has_mbus_clk = true,
1196
+};
1197
+
1198
+/*
11481199  * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
11491200  * and a total of 24 usable source and destination endpoints.
11501201  */
....@@ -1155,6 +1206,8 @@
11551206 	.nr_max_vchans   = 24,
11561207 	.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
11571208 	.set_burst_length = sun6i_set_burst_length_a31,
1209
+	.set_drq          = sun6i_set_drq_a31,
1210
+	.set_mode         = sun6i_set_mode_a31,
11581211 	.src_burst_lengths = BIT(1) | BIT(8),
11591212 	.dst_burst_lengths = BIT(1) | BIT(8),
11601213 	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
....@@ -1172,6 +1225,7 @@
11721225 	{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
11731226 	{ .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
11741227 	{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
1228
+	{ .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
11751229 	{ /* sentinel */ }
11761230 };
11771231 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
....@@ -1197,15 +1251,21 @@
11971251 		return PTR_ERR(sdc->base);
11981252 
11991253 	sdc->irq = platform_get_irq(pdev, 0);
1200
-	if (sdc->irq < 0) {
1201
-		dev_err(&pdev->dev, "Cannot claim IRQ\n");
1254
+	if (sdc->irq < 0)
12021255 		return sdc->irq;
1203
-	}
12041256 
12051257 	sdc->clk = devm_clk_get(&pdev->dev, NULL);
12061258 	if (IS_ERR(sdc->clk)) {
12071259 		dev_err(&pdev->dev, "No clock specified\n");
12081260 		return PTR_ERR(sdc->clk);
1261
+	}
1262
+
1263
+	if (sdc->cfg->has_mbus_clk) {
1264
+		sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus");
1265
+		if (IS_ERR(sdc->clk_mbus)) {
1266
+			dev_err(&pdev->dev, "No mbus clock specified\n");
1267
+			return PTR_ERR(sdc->clk_mbus);
1268
+		}
12091269 	}
12101270 
12111271 	sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
....@@ -1262,8 +1322,8 @@
12621322 	ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
12631323 	if (ret && !sdc->max_request) {
12641324 		dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
1265
-			 DMA_CHAN_MAX_DRQ);
1266
-		sdc->max_request = DMA_CHAN_MAX_DRQ;
1325
+			 DMA_CHAN_MAX_DRQ_A31);
1326
+		sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
12671327 	}
12681328 
12691329 	/*
....@@ -1283,7 +1343,7 @@
12831343 	if (!sdc->vchans)
12841344 		return -ENOMEM;
12851345 
1286
-	tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc);
1346
+	tasklet_setup(&sdc->task, sun6i_dma_tasklet);
12871347 
12881348 	for (i = 0; i < sdc->num_pchans; i++) {
12891349 		struct sun6i_pchan *pchan = &sdc->pchans[i];
....@@ -1312,11 +1372,19 @@
13121372 		goto err_reset_assert;
13131373 	}
13141374 
1375
+	if (sdc->cfg->has_mbus_clk) {
1376
+		ret = clk_prepare_enable(sdc->clk_mbus);
1377
+		if (ret) {
1378
+			dev_err(&pdev->dev, "Couldn't enable mbus clock\n");
1379
+			goto err_clk_disable;
1380
+		}
1381
+	}
1382
+
13151383 	ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
13161384 			       dev_name(&pdev->dev), sdc);
13171385 	if (ret) {
13181386 		dev_err(&pdev->dev, "Cannot request IRQ\n");
1319
-		goto err_clk_disable;
1387
+		goto err_mbus_clk_disable;
13201388 	}
13211389 
13221390 	ret = dma_async_device_register(&sdc->slave);
....@@ -1341,6 +1409,8 @@
13411409 	dma_async_device_unregister(&sdc->slave);
13421410 err_irq_disable:
13431411 	sun6i_kill_tasklet(sdc);
1412
+err_mbus_clk_disable:
1413
+	clk_disable_unprepare(sdc->clk_mbus);
13441414 err_clk_disable:
13451415 	clk_disable_unprepare(sdc->clk);
13461416 err_reset_assert:
....@@ -1359,6 +1429,7 @@
13591429 
13601430 	sun6i_kill_tasklet(sdc);
13611431 
1432
+	clk_disable_unprepare(sdc->clk_mbus);
13621433 	clk_disable_unprepare(sdc->clk);
13631434 	reset_control_assert(sdc->rstc);
13641435