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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/dma/ste_dma40.c
....@@ -1,9 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) Ericsson AB 2007-2008
34  * Copyright (C) ST-Ericsson SA 2008-2010
45  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
56  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6
- * License terms: GNU General Public License (GPL) version 2
77  */
88 
99 #include <linux/dma-mapping.h>
....@@ -381,6 +381,7 @@
381381  * struct d40_lcla_pool - LCLA pool settings and data.
382382  *
383383  * @base: The virtual address of LCLA. 18 bit aligned.
384
+ * @dma_addr: DMA address, if mapped
384385  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
385386  * This pointer is only there for clean-up on error.
386387  * @pages: The number of pages needed for all physical channels.
....@@ -442,6 +443,7 @@
442443  * @queue: Queued jobs.
443444  * @prepare_queue: Prepared jobs.
444445  * @dma_cfg: The client configuration of this dma channel.
446
+ * @slave_config: DMA slave configuration.
445447  * @configured: whether the dma_cfg configuration is valid
446448  * @base: Pointer to the device instance struct.
447449  * @src_def_cfg: Default cfg register setting for src.
....@@ -468,6 +470,7 @@
468470 	struct list_head		 queue;
469471 	struct list_head		 prepare_queue;
470472 	struct stedma40_chan_cfg	 dma_cfg;
473
+	struct dma_slave_config		 slave_config;
471474 	bool				 configured;
472475 	struct d40_base			*base;
473476 	/* Default register configurations */
....@@ -573,7 +576,6 @@
573576 	int				  num_memcpy_chans;
574577 	int				  num_phy_chans;
575578 	int				  num_log_chans;
576
-	struct device_dma_parameters	  dma_parms;
577579 	struct dma_device		  dma_both;
578580 	struct dma_device		  dma_slave;
579581 	struct dma_device		  dma_memcpy;
....@@ -624,6 +626,10 @@
624626 
625627 #define chan_err(d40c, format, arg...)		\
626628 	d40_err(chan2dev(d40c), format, ## arg)
629
+
630
+static int d40_set_runtime_config_write(struct dma_chan *chan,
631
+				  struct dma_slave_config *config,
632
+				  enum dma_transfer_direction direction);
627633 
628634 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
629635 			      int lli_len)
....@@ -1565,9 +1571,9 @@
15651571 
15661572 }
15671573 
1568
-static void dma_tasklet(unsigned long data)
1574
+static void dma_tasklet(struct tasklet_struct *t)
15691575 {
1570
-	struct d40_chan *d40c = (struct d40_chan *) data;
1576
+	struct d40_chan *d40c = from_tasklet(d40c, t, tasklet);
15711577 	struct d40_desc *d40d;
15721578 	unsigned long flags;
15731579 	bool callback_active;
....@@ -2216,6 +2222,8 @@
22162222 		return NULL;
22172223 	}
22182224 
2225
+	d40_set_runtime_config_write(dchan, &chan->slave_config, direction);
2226
+
22192227 	spin_lock_irqsave(&chan->lock, flags);
22202228 
22212229 	desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
....@@ -2634,9 +2642,20 @@
26342642 	return 0;
26352643 }
26362644 
2637
-/* Runtime reconfiguration extension */
26382645 static int d40_set_runtime_config(struct dma_chan *chan,
26392646 				  struct dma_slave_config *config)
2647
+{
2648
+	struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2649
+
2650
+	memcpy(&d40c->slave_config, config, sizeof(*config));
2651
+
2652
+	return 0;
2653
+}
2654
+
2655
+/* Runtime reconfiguration extension */
2656
+static int d40_set_runtime_config_write(struct dma_chan *chan,
2657
+				  struct dma_slave_config *config,
2658
+				  enum dma_transfer_direction direction)
26402659 {
26412660 	struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
26422661 	struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
....@@ -2655,7 +2674,7 @@
26552674 	dst_addr_width = config->dst_addr_width;
26562675 	dst_maxburst = config->dst_maxburst;
26572676 
2658
-	if (config->direction == DMA_DEV_TO_MEM) {
2677
+	if (direction == DMA_DEV_TO_MEM) {
26592678 		config_addr = config->src_addr;
26602679 
26612680 		if (cfg->dir != DMA_DEV_TO_MEM)
....@@ -2671,7 +2690,7 @@
26712690 		if (dst_maxburst == 0)
26722691 			dst_maxburst = src_maxburst;
26732692 
2674
-	} else if (config->direction == DMA_MEM_TO_DEV) {
2693
+	} else if (direction == DMA_MEM_TO_DEV) {
26752694 		config_addr = config->dst_addr;
26762695 
26772696 		if (cfg->dir != DMA_MEM_TO_DEV)
....@@ -2689,7 +2708,7 @@
26892708 	} else {
26902709 		dev_err(d40c->base->dev,
26912710 			"unrecognized channel direction %d\n",
2692
-			config->direction);
2711
+			direction);
26932712 		return -EINVAL;
26942713 	}
26952714 
....@@ -2746,12 +2765,12 @@
27462765 
27472766 	/* These settings will take precedence later */
27482767 	d40c->runtime_addr = config_addr;
2749
-	d40c->runtime_direction = config->direction;
2768
+	d40c->runtime_direction = direction;
27502769 	dev_dbg(d40c->base->dev,
27512770 		"configured channel %s for %s, data width %d/%d, "
27522771 		"maxburst %d/%d elements, LE, no flow control\n",
27532772 		dma_chan_name(chan),
2754
-		(config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2773
+		(direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
27552774 		src_addr_width, dst_addr_width,
27562775 		src_maxburst, dst_maxburst);
27572776 
....@@ -2785,8 +2804,7 @@
27852804 		INIT_LIST_HEAD(&d40c->client);
27862805 		INIT_LIST_HEAD(&d40c->prepare_queue);
27872806 
2788
-		tasklet_init(&d40c->tasklet, dma_tasklet,
2789
-			     (unsigned long) d40c);
2807
+		tasklet_setup(&d40c->tasklet, dma_tasklet);
27902808 
27912809 		list_add_tail(&d40c->chan.device_node,
27922810 			      &dma->channels);
....@@ -2839,7 +2857,7 @@
28392857 
28402858 	d40_ops_init(base, &base->dma_slave);
28412859 
2842
-	err = dma_async_device_register(&base->dma_slave);
2860
+	err = dmaenginem_async_device_register(&base->dma_slave);
28432861 
28442862 	if (err) {
28452863 		d40_err(base->dev, "Failed to register slave channels\n");
....@@ -2854,12 +2872,12 @@
28542872 
28552873 	d40_ops_init(base, &base->dma_memcpy);
28562874 
2857
-	err = dma_async_device_register(&base->dma_memcpy);
2875
+	err = dmaenginem_async_device_register(&base->dma_memcpy);
28582876 
28592877 	if (err) {
28602878 		d40_err(base->dev,
28612879 			"Failed to register memcpy only channels\n");
2862
-		goto unregister_slave;
2880
+		goto exit;
28632881 	}
28642882 
28652883 	d40_chan_init(base, &base->dma_both, base->phy_chans,
....@@ -2871,18 +2889,14 @@
28712889 	dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
28722890 
28732891 	d40_ops_init(base, &base->dma_both);
2874
-	err = dma_async_device_register(&base->dma_both);
2892
+	err = dmaenginem_async_device_register(&base->dma_both);
28752893 
28762894 	if (err) {
28772895 		d40_err(base->dev,
28782896 			"Failed to register logical and physical capable channels\n");
2879
-		goto unregister_memcpy;
2897
+		goto exit;
28802898 	}
28812899 	return 0;
2882
- unregister_memcpy:
2883
-	dma_async_device_unregister(&base->dma_memcpy);
2884
- unregister_slave:
2885
-	dma_async_device_unregister(&base->dma_slave);
28862900  exit:
28872901 	return err;
28882902 }
....@@ -3624,7 +3638,6 @@
36243638 	if (ret)
36253639 		goto destroy_cache;
36263640 
3627
-	base->dev->dma_parms = &base->dma_parms;
36283641 	ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
36293642 	if (ret) {
36303643 		d40_err(&pdev->dev, "Failed to set dma max seg size\n");