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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or modify it |
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| 5 | | - * under the terms of the GNU General Public License as published by the Free |
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| 6 | | - * Software Foundation; either version 2 of the License, or (at your option) |
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| 7 | | - * any later version. |
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| 8 | | - * |
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| 9 | | - * This program is distributed in the hope that it will be useful, but WITHOUT |
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| 10 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 11 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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| 12 | | - * more details. |
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| 13 | | - * |
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| 14 | | - * The full GNU General Public License is included in this distribution in the |
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| 15 | | - * file called COPYING. |
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| 16 | 4 | */ |
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| 17 | 5 | #ifndef _IOAT_REGISTERS_H_ |
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| 18 | 6 | #define _IOAT_REGISTERS_H_ |
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| .. | .. |
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| 84 | 72 | #define IOAT_CAP_PQ 0x00000200 |
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| 85 | 73 | #define IOAT_CAP_DWBES 0x00002000 |
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| 86 | 74 | #define IOAT_CAP_RAID16SS 0x00020000 |
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| 75 | +#define IOAT_CAP_DPS 0x00800000 |
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| 76 | + |
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| 77 | +#define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */ |
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| 87 | 78 | |
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| 88 | 79 | #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ |
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| 89 | 80 | |
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| .. | .. |
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| 243 | 234 | |
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| 244 | 235 | #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ |
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| 245 | 236 | |
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| 237 | +#define IOAT_CHAN_DRSCTL_OFFSET 0xB6 |
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| 238 | +#define IOAT_CHAN_DRSZ_4KB 0x0000 |
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| 239 | +#define IOAT_CHAN_DRSZ_8KB 0x0001 |
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| 240 | +#define IOAT_CHAN_DRSZ_2MB 0x0009 |
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| 241 | +#define IOAT_CHAN_DRS_EN 0x0100 |
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| 242 | +#define IOAT_CHAN_DRS_AUTOWRAP 0x0200 |
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| 243 | + |
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| 244 | +#define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC |
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| 245 | +#define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0 |
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| 246 | +#define IOAT_CHAN_LTR_SWSEL_IDLE 0x1 |
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| 247 | + |
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| 248 | +#define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0 |
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| 249 | +#define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */ |
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| 250 | +#define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */ |
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| 251 | +#define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */ |
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| 252 | + |
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| 253 | +#define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4 |
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| 254 | +#define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */ |
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| 255 | +#define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */ |
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| 256 | +#define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */ |
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| 257 | + |
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| 246 | 258 | #endif /* _IOAT_REGISTERS_H_ */ |
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