~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,11 +1,12 @@
1	1	// SPDX-License-Identifier: GPL-2.0
2		-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
	2	+/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
3	3
4	4	#include <linux/kernel.h>
5	5	#include <linux/module.h>
6	6	#include <crypto/algapi.h>
7	7	#include <crypto/hash.h>
8	8	#include <crypto/md5.h>
	9	+#include <crypto/sm3.h>
9	10	#include <crypto/internal/hash.h>
10	11
11	12	#include "cc_driver.h"
..	..	@@ -16,33 +17,44 @@
16	17
17	18	#define CC_MAX_HASH_SEQ_LEN 12
18	19	#define CC_MAX_OPAD_KEYS_SIZE CC_MAX_HASH_BLCK_SIZE
	20	+#define CC_SM3_HASH_LEN_SIZE 8
19	21
20	22	struct cc_hash_handle {
21		- cc_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/
22		- cc_sram_addr_t larval_digest_sram_addr; /* const value in SRAM */
	23	+ u32 digest_len_sram_addr; /* const value in SRAM*/
	24	+ u32 larval_digest_sram_addr; /* const value in SRAM */
23	25	struct list_head hash_list;
24	26	};
25	27
26		-static const u32 digest_len_init[] = {
	28	+static const u32 cc_digest_len_init[] = {
27	29	0x00000040, 0x00000000, 0x00000000, 0x00000000 };
28		-static const u32 md5_init[] = {
	30	+static const u32 cc_md5_init[] = {
29	31	SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
30		-static const u32 sha1_init[] = {
	32	+static const u32 cc_sha1_init[] = {
31	33	SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
32		-static const u32 sha224_init[] = {
	34	+static const u32 cc_sha224_init[] = {
33	35	SHA224_H7, SHA224_H6, SHA224_H5, SHA224_H4,
34	36	SHA224_H3, SHA224_H2, SHA224_H1, SHA224_H0 };
35		-static const u32 sha256_init[] = {
	37	+static const u32 cc_sha256_init[] = {
36	38	SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4,
37	39	SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 };
38		-static const u32 digest_len_sha512_init[] = {
	40	+static const u32 cc_digest_len_sha512_init[] = {
39	41	0x00000080, 0x00000000, 0x00000000, 0x00000000 };
40		-static u64 sha384_init[] = {
41		- SHA384_H7, SHA384_H6, SHA384_H5, SHA384_H4,
42		- SHA384_H3, SHA384_H2, SHA384_H1, SHA384_H0 };
43		-static u64 sha512_init[] = {
44		- SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4,
45		- SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 };
	42	+
	43	+/*
	44	+ * Due to the way the HW works, every double word in the SHA384 and SHA512
	45	+ * larval hashes must be stored in hi/lo order
	46	+ */
	47	+#define hilo(x) upper_32_bits(x), lower_32_bits(x)
	48	+static const u32 cc_sha384_init[] = {
	49	+ hilo(SHA384_H7), hilo(SHA384_H6), hilo(SHA384_H5), hilo(SHA384_H4),
	50	+ hilo(SHA384_H3), hilo(SHA384_H2), hilo(SHA384_H1), hilo(SHA384_H0) };
	51	+static const u32 cc_sha512_init[] = {
	52	+ hilo(SHA512_H7), hilo(SHA512_H6), hilo(SHA512_H5), hilo(SHA512_H4),
	53	+ hilo(SHA512_H3), hilo(SHA512_H2), hilo(SHA512_H1), hilo(SHA512_H0) };
	54	+
	55	+static const u32 cc_sm3_init[] = {
	56	+ SM3_IVH, SM3_IVG, SM3_IVF, SM3_IVE,
	57	+ SM3_IVD, SM3_IVC, SM3_IVB, SM3_IVA };
46	58
47	59	static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],
48	60	unsigned int *seq_size);
..	..	@@ -83,6 +95,7 @@
83	95	int hash_mode;
84	96	int hw_mode;
85	97	int inter_digestsize;
	98	+ unsigned int hash_len;
86	99	struct completion setkey_comp;
87	100	bool is_hmac;
88	101	};
..	..	@@ -138,11 +151,12 @@
138	151	if (ctx->hash_mode == DRV_HASH_SHA512 \|\|
139	152	ctx->hash_mode == DRV_HASH_SHA384)
140	153	memcpy(state->digest_bytes_len,
141		- digest_len_sha512_init,
142		- ctx->drvdata->hash_len_sz);
	154	+ cc_digest_len_sha512_init,
	155	+ ctx->hash_len);
143	156	else
144		- memcpy(state->digest_bytes_len, digest_len_init,
145		- ctx->drvdata->hash_len_sz);
	157	+ memcpy(state->digest_bytes_len,
	158	+ cc_digest_len_init,
	159	+ ctx->hash_len);
146	160	}
147	161
148	162	if (ctx->hash_mode != DRV_HASH_NULL) {
..	..	@@ -275,9 +289,13 @@
275	289
276	290	dev_dbg(dev, "req=%pK\n", req);
277	291
278		- cc_unmap_hash_request(dev, state, req->src, false);
279		- cc_unmap_req(dev, state, ctx);
280		- req->base.complete(&req->base, err);
	292	+ if (err != -EINPROGRESS) {
	293	+ /* Not a BACKLOG notification */
	294	+ cc_unmap_hash_request(dev, state, req->src, false);
	295	+ cc_unmap_req(dev, state, ctx);
	296	+ }
	297	+
	298	+ ahash_request_complete(req, err);
281	299	}
282	300
283	301	static void cc_digest_complete(struct device dev, void cc_req, int err)
..	..	@@ -290,10 +308,14 @@
290	308
291	309	dev_dbg(dev, "req=%pK\n", req);
292	310
293		- cc_unmap_hash_request(dev, state, req->src, false);
294		- cc_unmap_result(dev, state, digestsize, req->result);
295		- cc_unmap_req(dev, state, ctx);
296		- req->base.complete(&req->base, err);
	311	+ if (err != -EINPROGRESS) {
	312	+ /* Not a BACKLOG notification */
	313	+ cc_unmap_hash_request(dev, state, req->src, false);
	314	+ cc_unmap_result(dev, state, digestsize, req->result);
	315	+ cc_unmap_req(dev, state, ctx);
	316	+ }
	317	+
	318	+ ahash_request_complete(req, err);
297	319	}
298	320
299	321	static void cc_hash_complete(struct device dev, void cc_req, int err)
..	..	@@ -306,10 +328,14 @@
306	328
307	329	dev_dbg(dev, "req=%pK\n", req);
308	330
309		- cc_unmap_hash_request(dev, state, req->src, false);
310		- cc_unmap_result(dev, state, digestsize, req->result);
311		- cc_unmap_req(dev, state, ctx);
312		- req->base.complete(&req->base, err);
	331	+ if (err != -EINPROGRESS) {
	332	+ /* Not a BACKLOG notification */
	333	+ cc_unmap_hash_request(dev, state, req->src, false);
	334	+ cc_unmap_result(dev, state, digestsize, req->result);
	335	+ cc_unmap_req(dev, state, ctx);
	336	+ }
	337	+
	338	+ ahash_request_complete(req, err);
313	339	}
314	340
315	341	static int cc_fin_result(struct cc_hw_desc desc, struct ahash_request req,
..	..	@@ -322,8 +348,7 @@
322	348
323	349	/* Get final MAC result */
324	350	hw_desc_init(&desc[idx]);
325		- set_cipher_mode(&desc[idx], ctx->hw_mode);
326		- /* TODO */
	351	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
327	352	set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize,
328	353	NS_BIT, 1);
329	354	set_queue_last_ind(ctx->drvdata, &desc[idx]);
..	..	@@ -368,7 +393,7 @@
368	393	set_cipher_mode(&desc[idx], ctx->hw_mode);
369	394	set_din_sram(&desc[idx],
370	395	cc_digest_len_addr(ctx->drvdata, ctx->hash_mode),
371		- ctx->drvdata->hash_len_sz);
	396	+ ctx->hash_len);
372	397	set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
373	398	set_flow_mode(&desc[idx], S_DIN_to_HASH);
374	399	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
..	..	@@ -403,8 +428,7 @@
403	428	bool is_hmac = ctx->is_hmac;
404	429	struct cc_crypto_req cc_req = {};
405	430	struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
406		- cc_sram_addr_t larval_digest_addr =
407		- cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
	431	+ u32 larval_digest_addr;
408	432	int idx = 0;
409	433	int rc = 0;
410	434	gfp_t flags = cc_gfp_flags(&req->base);
..	..	@@ -441,11 +465,13 @@
441	465	* digest
442	466	*/
443	467	hw_desc_init(&desc[idx]);
444		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	468	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
445	469	if (is_hmac) {
446	470	set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
447	471	ctx->inter_digestsize, NS_BIT);
448	472	} else {
	473	+ larval_digest_addr = cc_larval_digest_addr(ctx->drvdata,
	474	+ ctx->hash_mode);
449	475	set_din_sram(&desc[idx], larval_digest_addr,
450	476	ctx->inter_digestsize);
451	477	}
..	..	@@ -455,14 +481,14 @@
455	481
456	482	/* Load the hash current length */
457	483	hw_desc_init(&desc[idx]);
458		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	484	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
459	485
460	486	if (is_hmac) {
461	487	set_din_type(&desc[idx], DMA_DLLI,
462	488	state->digest_bytes_len_dma_addr,
463		- ctx->drvdata->hash_len_sz, NS_BIT);
	489	+ ctx->hash_len, NS_BIT);
464	490	} else {
465		- set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz);
	491	+ set_din_const(&desc[idx], 0, ctx->hash_len);
466	492	if (nbytes)
467	493	set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
468	494	else
..	..	@@ -479,7 +505,7 @@
479	505	hw_desc_init(&desc[idx]);
480	506	set_cipher_mode(&desc[idx], ctx->hw_mode);
481	507	set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
482		- ctx->drvdata->hash_len_sz, NS_BIT, 0);
	508	+ ctx->hash_len, NS_BIT, 0);
483	509	set_flow_mode(&desc[idx], S_HASH_to_DOUT);
484	510	set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
485	511	set_cipher_do(&desc[idx], DO_PAD);
..	..	@@ -505,7 +531,7 @@
505	531	{
506	532	/* Restore hash digest */
507	533	hw_desc_init(&desc[idx]);
508		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	534	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
509	535	set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
510	536	ctx->inter_digestsize, NS_BIT);
511	537	set_flow_mode(&desc[idx], S_DIN_to_HASH);
..	..	@@ -514,10 +540,10 @@
514	540
515	541	/* Restore hash current length */
516	542	hw_desc_init(&desc[idx]);
517		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	543	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
518	544	set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
519	545	set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr,
520		- ctx->drvdata->hash_len_sz, NS_BIT);
	546	+ ctx->hash_len, NS_BIT);
521	547	set_flow_mode(&desc[idx], S_DIN_to_HASH);
522	548	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
523	549	idx++;
..	..	@@ -577,7 +603,7 @@
577	603
578	604	/* store the hash digest result in context */
579	605	hw_desc_init(&desc[idx]);
580		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	606	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
581	607	set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
582	608	ctx->inter_digestsize, NS_BIT, 0);
583	609	set_flow_mode(&desc[idx], S_HASH_to_DOUT);
..	..	@@ -586,9 +612,9 @@
586	612
587	613	/* store current hash length in context */
588	614	hw_desc_init(&desc[idx]);
589		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	615	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
590	616	set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr,
591		- ctx->drvdata->hash_len_sz, NS_BIT, 1);
	617	+ ctx->hash_len, NS_BIT, 1);
592	618	set_queue_last_ind(ctx->drvdata, &desc[idx]);
593	619	set_flow_mode(&desc[idx], S_HASH_to_DOUT);
594	620	set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
..	..	@@ -650,9 +676,9 @@
650	676	/* Pad the hash */
651	677	hw_desc_init(&desc[idx]);
652	678	set_cipher_do(&desc[idx], DO_PAD);
653		- set_cipher_mode(&desc[idx], ctx->hw_mode);
	679	+ set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
654	680	set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr,
655		- ctx->drvdata->hash_len_sz, NS_BIT, 0);
	681	+ ctx->hash_len, NS_BIT, 0);
656	682	set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
657	683	set_flow_mode(&desc[idx], S_HASH_to_DOUT);
658	684	idx++;
..	..	@@ -707,7 +733,7 @@
707	733	int digestsize = 0;
708	734	int i, idx = 0, rc = 0;
709	735	struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
710		- cc_sram_addr_t larval_addr;
	736	+ u32 larval_addr;
711	737	struct device *dev;
712	738
713	739	ctx = crypto_ahash_ctx(ahash);
..	..	@@ -733,12 +759,12 @@
733	759	return -ENOMEM;
734	760
735	761	ctx->key_params.key_dma_addr =
736		- dma_map_single(dev, (void *)ctx->key_params.key, keylen,
	762	+ dma_map_single(dev, ctx->key_params.key, keylen,
737	763	DMA_TO_DEVICE);
738	764	if (dma_mapping_error(dev, ctx->key_params.key_dma_addr)) {
739	765	dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n",
740	766	ctx->key_params.key, keylen);
741		- kzfree(ctx->key_params.key);
	767	+ kfree_sensitive(ctx->key_params.key);
742	768	return -ENOMEM;
743	769	}
744	770	dev_dbg(dev, "mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
..	..	@@ -757,7 +783,7 @@
757	783	/* Load the hash current length*/
758	784	hw_desc_init(&desc[idx]);
759	785	set_cipher_mode(&desc[idx], ctx->hw_mode);
760		- set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz);
	786	+ set_din_const(&desc[idx], 0, ctx->hash_len);
761	787	set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
762	788	set_flow_mode(&desc[idx], S_DIN_to_HASH);
763	789	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
..	..	@@ -839,7 +865,7 @@
839	865	/* Load the hash current length*/
840	866	hw_desc_init(&desc[idx]);
841	867	set_cipher_mode(&desc[idx], ctx->hw_mode);
842		- set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz);
	868	+ set_din_const(&desc[idx], 0, ctx->hash_len);
843	869	set_flow_mode(&desc[idx], S_DIN_to_HASH);
844	870	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
845	871	idx++;
..	..	@@ -880,9 +906,6 @@
880	906	rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);
881	907
882	908	out:
883		- if (rc)
884		- crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
885		-
886	909	if (ctx->key_params.key_dma_addr) {
887	910	dma_unmap_single(dev, ctx->key_params.key_dma_addr,
888	911	ctx->key_params.keylen, DMA_TO_DEVICE);
..	..	@@ -890,7 +913,7 @@
890	913	&ctx->key_params.key_dma_addr, ctx->key_params.keylen);
891	914	}
892	915
893		- kzfree(ctx->key_params.key);
	916	+ kfree_sensitive(ctx->key_params.key);
894	917
895	918	return rc;
896	919	}
..	..	@@ -927,7 +950,7 @@
927	950	if (dma_mapping_error(dev, ctx->key_params.key_dma_addr)) {
928	951	dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n",
929	952	key, keylen);
930		- kzfree(ctx->key_params.key);
	953	+ kfree_sensitive(ctx->key_params.key);
931	954	return -ENOMEM;
932	955	}
933	956	dev_dbg(dev, "mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
..	..	@@ -971,15 +994,12 @@
971	994
972	995	rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);
973	996
974		- if (rc)
975		- crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
976		-
977	997	dma_unmap_single(dev, ctx->key_params.key_dma_addr,
978	998	ctx->key_params.keylen, DMA_TO_DEVICE);
979	999	dev_dbg(dev, "Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n",
980	1000	&ctx->key_params.key_dma_addr, ctx->key_params.keylen);
981	1001
982		- kzfree(ctx->key_params.key);
	1002	+ kfree_sensitive(ctx->key_params.key);
983	1003
984	1004	return rc;
985	1005	}
..	..	@@ -1054,8 +1074,8 @@
1054	1074	ctx->key_params.keylen = 0;
1055	1075
1056	1076	ctx->digest_buff_dma_addr =
1057		- dma_map_single(dev, (void *)ctx->digest_buff,
1058		- sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL);
	1077	+ dma_map_single(dev, ctx->digest_buff, sizeof(ctx->digest_buff),
	1078	+ DMA_BIDIRECTIONAL);
1059	1079	if (dma_mapping_error(dev, ctx->digest_buff_dma_addr)) {
1060	1080	dev_err(dev, "Mapping digest len %zu B at va=%pK for DMA failed\n",
1061	1081	sizeof(ctx->digest_buff), ctx->digest_buff);
..	..	@@ -1066,7 +1086,7 @@
1066	1086	&ctx->digest_buff_dma_addr);
1067	1087
1068	1088	ctx->opad_tmp_keys_dma_addr =
1069		- dma_map_single(dev, (void *)ctx->opad_tmp_keys_buff,
	1089	+ dma_map_single(dev, ctx->opad_tmp_keys_buff,
1070	1090	sizeof(ctx->opad_tmp_keys_buff),
1071	1091	DMA_BIDIRECTIONAL);
1072	1092	if (dma_mapping_error(dev, ctx->opad_tmp_keys_dma_addr)) {
..	..	@@ -1087,6 +1107,16 @@
1087	1107	return -ENOMEM;
1088	1108	}
1089	1109
	1110	+static int cc_get_hash_len(struct crypto_tfm *tfm)
	1111	+{
	1112	+ struct cc_hash_ctx *ctx = crypto_tfm_ctx(tfm);
	1113	+
	1114	+ if (ctx->hash_mode == DRV_HASH_SM3)
	1115	+ return CC_SM3_HASH_LEN_SIZE;
	1116	+ else
	1117	+ return cc_get_default_hash_len(ctx->drvdata);
	1118	+}
	1119	+
1090	1120	static int cc_cra_init(struct crypto_tfm *tfm)
1091	1121	{
1092	1122	struct cc_hash_ctx *ctx = crypto_tfm_ctx(tfm);
..	..	@@ -1104,7 +1134,7 @@
1104	1134	ctx->hw_mode = cc_alg->hw_mode;
1105	1135	ctx->inter_digestsize = cc_alg->inter_digestsize;
1106	1136	ctx->drvdata = cc_alg->drvdata;
1107		-
	1137	+ ctx->hash_len = cc_get_hash_len(tfm);
1108	1138	return cc_alloc_ctx(ctx);
1109	1139	}
1110	1140
..	..	@@ -1173,8 +1203,8 @@
1173	1203	idx++;
1174	1204
1175	1205	/* Setup request structure */
1176		- cc_req.user_cb = (void *)cc_update_complete;
1177		- cc_req.user_arg = (void *)req;
	1206	+ cc_req.user_cb = cc_update_complete;
	1207	+ cc_req.user_arg = req;
1178	1208
1179	1209	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
1180	1210	if (rc != -EINPROGRESS && rc != -EBUSY) {
..	..	@@ -1231,8 +1261,8 @@
1231	1261	}
1232	1262
1233	1263	/* Setup request structure */
1234		- cc_req.user_cb = (void *)cc_hash_complete;
1235		- cc_req.user_arg = (void *)req;
	1264	+ cc_req.user_cb = cc_hash_complete;
	1265	+ cc_req.user_arg = req;
1236	1266
1237	1267	if (state->xcbc_count && rem_cnt == 0) {
1238	1268	/* Load key for ECB decryption */
..	..	@@ -1288,7 +1318,6 @@
1288	1318
1289	1319	/* Get final MAC result */
1290	1320	hw_desc_init(&desc[idx]);
1291		- /* TODO */
1292	1321	set_dout_dlli(&desc[idx], state->digest_result_dma_addr,
1293	1322	digestsize, NS_BIT, 1);
1294	1323	set_queue_last_ind(ctx->drvdata, &desc[idx]);
..	..	@@ -1346,8 +1375,8 @@
1346	1375	}
1347	1376
1348	1377	/* Setup request structure */
1349		- cc_req.user_cb = (void *)cc_hash_complete;
1350		- cc_req.user_arg = (void *)req;
	1378	+ cc_req.user_cb = cc_hash_complete;
	1379	+ cc_req.user_arg = req;
1351	1380
1352	1381	if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) {
1353	1382	key_len = CC_AES_128_BIT_KEY_SIZE;
..	..	@@ -1370,7 +1399,6 @@
1370	1399
1371	1400	/* Get final MAC result */
1372	1401	hw_desc_init(&desc[idx]);
1373		- /* TODO */
1374	1402	set_dout_dlli(&desc[idx], state->digest_result_dma_addr,
1375	1403	digestsize, NS_BIT, 1);
1376	1404	set_queue_last_ind(ctx->drvdata, &desc[idx]);
..	..	@@ -1425,8 +1453,8 @@
1425	1453	}
1426	1454
1427	1455	/* Setup request structure */
1428		- cc_req.user_cb = (void *)cc_digest_complete;
1429		- cc_req.user_arg = (void *)req;
	1456	+ cc_req.user_cb = cc_digest_complete;
	1457	+ cc_req.user_arg = req;
1430	1458
1431	1459	if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) {
1432	1460	key_len = CC_AES_128_BIT_KEY_SIZE;
..	..	@@ -1483,8 +1511,8 @@
1483	1511	memcpy(out, state->digest_buff, ctx->inter_digestsize);
1484	1512	out += ctx->inter_digestsize;
1485	1513
1486		- memcpy(out, state->digest_bytes_len, ctx->drvdata->hash_len_sz);
1487		- out += ctx->drvdata->hash_len_sz;
	1514	+ memcpy(out, state->digest_bytes_len, ctx->hash_len);
	1515	+ out += ctx->hash_len;
1488	1516
1489	1517	memcpy(out, &curr_buff_cnt, sizeof(u32));
1490	1518	out += sizeof(u32);
..	..	@@ -1512,8 +1540,8 @@
1512	1540	memcpy(state->digest_buff, in, ctx->inter_digestsize);
1513	1541	in += ctx->inter_digestsize;
1514	1542
1515		- memcpy(state->digest_bytes_len, in, ctx->drvdata->hash_len_sz);
1516		- in += ctx->drvdata->hash_len_sz;
	1543	+ memcpy(state->digest_bytes_len, in, ctx->hash_len);
	1544	+ in += ctx->hash_len;
1517	1545
1518	1546	/* Sanity check the data as much as possible */
1519	1547	memcpy(&tmp, in, sizeof(u32));
..	..	@@ -1533,6 +1561,7 @@
1533	1561	char mac_name[CRYPTO_MAX_ALG_NAME];
1534	1562	char mac_driver_name[CRYPTO_MAX_ALG_NAME];
1535	1563	unsigned int blocksize;
	1564	+ bool is_mac;
1536	1565	bool synchronize;
1537	1566	struct ahash_alg template_ahash;
1538	1567	int hash_mode;
..	..	@@ -1540,6 +1569,7 @@
1540	1569	int inter_digestsize;
1541	1570	struct cc_drvdata *drvdata;
1542	1571	u32 min_hw_rev;
	1572	+ enum cc_std_body std_body;
1543	1573	};
1544	1574
1545	1575	#define CC_STATE_SIZE(_x) \
..	..	@@ -1554,6 +1584,7 @@
1554	1584	.mac_name = "hmac(sha1)",
1555	1585	.mac_driver_name = "hmac-sha1-ccree",
1556	1586	.blocksize = SHA1_BLOCK_SIZE,
	1587	+ .is_mac = true,
1557	1588	.synchronize = false,
1558	1589	.template_ahash = {
1559	1590	.init = cc_hash_init,
..	..	@@ -1573,6 +1604,7 @@
1573	1604	.hw_mode = DRV_HASH_HW_SHA1,
1574	1605	.inter_digestsize = SHA1_DIGEST_SIZE,
1575	1606	.min_hw_rev = CC_HW_REV_630,
	1607	+ .std_body = CC_STD_NIST,
1576	1608	},
1577	1609	{
1578	1610	.name = "sha256",
..	..	@@ -1580,6 +1612,7 @@
1580	1612	.mac_name = "hmac(sha256)",
1581	1613	.mac_driver_name = "hmac-sha256-ccree",
1582	1614	.blocksize = SHA256_BLOCK_SIZE,
	1615	+ .is_mac = true,
1583	1616	.template_ahash = {
1584	1617	.init = cc_hash_init,
1585	1618	.update = cc_hash_update,
..	..	@@ -1598,6 +1631,7 @@
1598	1631	.hw_mode = DRV_HASH_HW_SHA256,
1599	1632	.inter_digestsize = SHA256_DIGEST_SIZE,
1600	1633	.min_hw_rev = CC_HW_REV_630,
	1634	+ .std_body = CC_STD_NIST,
1601	1635	},
1602	1636	{
1603	1637	.name = "sha224",
..	..	@@ -1605,6 +1639,7 @@
1605	1639	.mac_name = "hmac(sha224)",
1606	1640	.mac_driver_name = "hmac-sha224-ccree",
1607	1641	.blocksize = SHA224_BLOCK_SIZE,
	1642	+ .is_mac = true,
1608	1643	.template_ahash = {
1609	1644	.init = cc_hash_init,
1610	1645	.update = cc_hash_update,
..	..	@@ -1623,6 +1658,7 @@
1623	1658	.hw_mode = DRV_HASH_HW_SHA256,
1624	1659	.inter_digestsize = SHA256_DIGEST_SIZE,
1625	1660	.min_hw_rev = CC_HW_REV_630,
	1661	+ .std_body = CC_STD_NIST,
1626	1662	},
1627	1663	{
1628	1664	.name = "sha384",
..	..	@@ -1630,6 +1666,7 @@
1630	1666	.mac_name = "hmac(sha384)",
1631	1667	.mac_driver_name = "hmac-sha384-ccree",
1632	1668	.blocksize = SHA384_BLOCK_SIZE,
	1669	+ .is_mac = true,
1633	1670	.template_ahash = {
1634	1671	.init = cc_hash_init,
1635	1672	.update = cc_hash_update,
..	..	@@ -1648,6 +1685,7 @@
1648	1685	.hw_mode = DRV_HASH_HW_SHA512,
1649	1686	.inter_digestsize = SHA512_DIGEST_SIZE,
1650	1687	.min_hw_rev = CC_HW_REV_712,
	1688	+ .std_body = CC_STD_NIST,
1651	1689	},
1652	1690	{
1653	1691	.name = "sha512",
..	..	@@ -1655,6 +1693,7 @@
1655	1693	.mac_name = "hmac(sha512)",
1656	1694	.mac_driver_name = "hmac-sha512-ccree",
1657	1695	.blocksize = SHA512_BLOCK_SIZE,
	1696	+ .is_mac = true,
1658	1697	.template_ahash = {
1659	1698	.init = cc_hash_init,
1660	1699	.update = cc_hash_update,
..	..	@@ -1673,6 +1712,7 @@
1673	1712	.hw_mode = DRV_HASH_HW_SHA512,
1674	1713	.inter_digestsize = SHA512_DIGEST_SIZE,
1675	1714	.min_hw_rev = CC_HW_REV_712,
	1715	+ .std_body = CC_STD_NIST,
1676	1716	},
1677	1717	{
1678	1718	.name = "md5",
..	..	@@ -1680,6 +1720,7 @@
1680	1720	.mac_name = "hmac(md5)",
1681	1721	.mac_driver_name = "hmac-md5-ccree",
1682	1722	.blocksize = MD5_HMAC_BLOCK_SIZE,
	1723	+ .is_mac = true,
1683	1724	.template_ahash = {
1684	1725	.init = cc_hash_init,
1685	1726	.update = cc_hash_update,
..	..	@@ -1698,11 +1739,38 @@
1698	1739	.hw_mode = DRV_HASH_HW_MD5,
1699	1740	.inter_digestsize = MD5_DIGEST_SIZE,
1700	1741	.min_hw_rev = CC_HW_REV_630,
	1742	+ .std_body = CC_STD_NIST,
	1743	+ },
	1744	+ {
	1745	+ .name = "sm3",
	1746	+ .driver_name = "sm3-ccree",
	1747	+ .blocksize = SM3_BLOCK_SIZE,
	1748	+ .is_mac = false,
	1749	+ .template_ahash = {
	1750	+ .init = cc_hash_init,
	1751	+ .update = cc_hash_update,
	1752	+ .final = cc_hash_final,
	1753	+ .finup = cc_hash_finup,
	1754	+ .digest = cc_hash_digest,
	1755	+ .export = cc_hash_export,
	1756	+ .import = cc_hash_import,
	1757	+ .setkey = cc_hash_setkey,
	1758	+ .halg = {
	1759	+ .digestsize = SM3_DIGEST_SIZE,
	1760	+ .statesize = CC_STATE_SIZE(SM3_DIGEST_SIZE),
	1761	+ },
	1762	+ },
	1763	+ .hash_mode = DRV_HASH_SM3,
	1764	+ .hw_mode = DRV_HASH_HW_SM3,
	1765	+ .inter_digestsize = SM3_DIGEST_SIZE,
	1766	+ .min_hw_rev = CC_HW_REV_713,
	1767	+ .std_body = CC_STD_OSCCA,
1701	1768	},
1702	1769	{
1703	1770	.mac_name = "xcbc(aes)",
1704	1771	.mac_driver_name = "xcbc-aes-ccree",
1705	1772	.blocksize = AES_BLOCK_SIZE,
	1773	+ .is_mac = true,
1706	1774	.template_ahash = {
1707	1775	.init = cc_hash_init,
1708	1776	.update = cc_mac_update,
..	..	@@ -1721,11 +1789,13 @@
1721	1789	.hw_mode = DRV_CIPHER_XCBC_MAC,
1722	1790	.inter_digestsize = AES_BLOCK_SIZE,
1723	1791	.min_hw_rev = CC_HW_REV_630,
	1792	+ .std_body = CC_STD_NIST,
1724	1793	},
1725	1794	{
1726	1795	.mac_name = "cmac(aes)",
1727	1796	.mac_driver_name = "cmac-aes-ccree",
1728	1797	.blocksize = AES_BLOCK_SIZE,
	1798	+ .is_mac = true,
1729	1799	.template_ahash = {
1730	1800	.init = cc_hash_init,
1731	1801	.update = cc_mac_update,
..	..	@@ -1744,6 +1814,7 @@
1744	1814	.hw_mode = DRV_CIPHER_CMAC,
1745	1815	.inter_digestsize = AES_BLOCK_SIZE,
1746	1816	.min_hw_rev = CC_HW_REV_630,
	1817	+ .std_body = CC_STD_NIST,
1747	1818	},
1748	1819	};
1749	1820
..	..	@@ -1754,7 +1825,7 @@
1754	1825	struct crypto_alg *alg;
1755	1826	struct ahash_alg *halg;
1756	1827
1757		- t_crypto_alg = kzalloc(sizeof(*t_crypto_alg), GFP_KERNEL);
	1828	+ t_crypto_alg = devm_kzalloc(dev, sizeof(*t_crypto_alg), GFP_KERNEL);
1758	1829	if (!t_crypto_alg)
1759	1830	return ERR_PTR(-ENOMEM);
1760	1831
..	..	@@ -1791,92 +1862,85 @@
1791	1862	return t_crypto_alg;
1792	1863	}
1793	1864
	1865	+static int cc_init_copy_sram(struct cc_drvdata drvdata, const u32 data,
	1866	+ unsigned int size, u32 *sram_buff_ofs)
	1867	+{
	1868	+ struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)];
	1869	+ unsigned int larval_seq_len = 0;
	1870	+ int rc;
	1871	+
	1872	+ cc_set_sram_desc(data, sram_buff_ofs, size / sizeof(data),
	1873	+ larval_seq, &larval_seq_len);
	1874	+ rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1875	+ if (rc)
	1876	+ return rc;
	1877	+
	1878	+ *sram_buff_ofs += size;
	1879	+ return 0;
	1880	+}
	1881	+
1794	1882	int cc_init_hash_sram(struct cc_drvdata *drvdata)
1795	1883	{
1796	1884	struct cc_hash_handle *hash_handle = drvdata->hash_handle;
1797		- cc_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr;
1798		- unsigned int larval_seq_len = 0;
1799		- struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)];
	1885	+ u32 sram_buff_ofs = hash_handle->digest_len_sram_addr;
1800	1886	bool large_sha_supported = (drvdata->hw_rev >= CC_HW_REV_712);
	1887	+ bool sm3_supported = (drvdata->hw_rev >= CC_HW_REV_713);
1801	1888	int rc = 0;
1802	1889
1803	1890	/* Copy-to-sram digest-len */
1804		- cc_set_sram_desc(digest_len_init, sram_buff_ofs,
1805		- ARRAY_SIZE(digest_len_init), larval_seq,
1806		- &larval_seq_len);
1807		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1891	+ rc = cc_init_copy_sram(drvdata, cc_digest_len_init,
	1892	+ sizeof(cc_digest_len_init), &sram_buff_ofs);
1808	1893	if (rc)
1809	1894	goto init_digest_const_err;
1810	1895
1811		- sram_buff_ofs += sizeof(digest_len_init);
1812		- larval_seq_len = 0;
1813		-
1814	1896	if (large_sha_supported) {
1815	1897	/* Copy-to-sram digest-len for sha384/512 */
1816		- cc_set_sram_desc(digest_len_sha512_init, sram_buff_ofs,
1817		- ARRAY_SIZE(digest_len_sha512_init),
1818		- larval_seq, &larval_seq_len);
1819		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1898	+ rc = cc_init_copy_sram(drvdata, cc_digest_len_sha512_init,
	1899	+ sizeof(cc_digest_len_sha512_init),
	1900	+ &sram_buff_ofs);
1820	1901	if (rc)
1821	1902	goto init_digest_const_err;
1822		-
1823		- sram_buff_ofs += sizeof(digest_len_sha512_init);
1824		- larval_seq_len = 0;
1825	1903	}
1826	1904
1827	1905	/* The initial digests offset */
1828	1906	hash_handle->larval_digest_sram_addr = sram_buff_ofs;
1829	1907
1830	1908	/* Copy-to-sram initial SHA* digests */
1831		- cc_set_sram_desc(md5_init, sram_buff_ofs, ARRAY_SIZE(md5_init),
1832		- larval_seq, &larval_seq_len);
1833		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1909	+ rc = cc_init_copy_sram(drvdata, cc_md5_init, sizeof(cc_md5_init),
	1910	+ &sram_buff_ofs);
1834	1911	if (rc)
1835	1912	goto init_digest_const_err;
1836		- sram_buff_ofs += sizeof(md5_init);
1837		- larval_seq_len = 0;
1838	1913
1839		- cc_set_sram_desc(sha1_init, sram_buff_ofs,
1840		- ARRAY_SIZE(sha1_init), larval_seq,
1841		- &larval_seq_len);
1842		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1914	+ rc = cc_init_copy_sram(drvdata, cc_sha1_init, sizeof(cc_sha1_init),
	1915	+ &sram_buff_ofs);
1843	1916	if (rc)
1844	1917	goto init_digest_const_err;
1845		- sram_buff_ofs += sizeof(sha1_init);
1846		- larval_seq_len = 0;
1847	1918
1848		- cc_set_sram_desc(sha224_init, sram_buff_ofs,
1849		- ARRAY_SIZE(sha224_init), larval_seq,
1850		- &larval_seq_len);
1851		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1919	+ rc = cc_init_copy_sram(drvdata, cc_sha224_init, sizeof(cc_sha224_init),
	1920	+ &sram_buff_ofs);
1852	1921	if (rc)
1853	1922	goto init_digest_const_err;
1854		- sram_buff_ofs += sizeof(sha224_init);
1855		- larval_seq_len = 0;
1856	1923
1857		- cc_set_sram_desc(sha256_init, sram_buff_ofs,
1858		- ARRAY_SIZE(sha256_init), larval_seq,
1859		- &larval_seq_len);
1860		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1924	+ rc = cc_init_copy_sram(drvdata, cc_sha256_init, sizeof(cc_sha256_init),
	1925	+ &sram_buff_ofs);
1861	1926	if (rc)
1862	1927	goto init_digest_const_err;
1863		- sram_buff_ofs += sizeof(sha256_init);
1864		- larval_seq_len = 0;
1865	1928
1866		- if (large_sha_supported) {
1867		- cc_set_sram_desc((u32 *)sha384_init, sram_buff_ofs,
1868		- (ARRAY_SIZE(sha384_init) * 2), larval_seq,
1869		- &larval_seq_len);
1870		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1929	+ if (sm3_supported) {
	1930	+ rc = cc_init_copy_sram(drvdata, cc_sm3_init,
	1931	+ sizeof(cc_sm3_init), &sram_buff_ofs);
1871	1932	if (rc)
1872	1933	goto init_digest_const_err;
1873		- sram_buff_ofs += sizeof(sha384_init);
1874		- larval_seq_len = 0;
	1934	+ }
1875	1935
1876		- cc_set_sram_desc((u32 *)sha512_init, sram_buff_ofs,
1877		- (ARRAY_SIZE(sha512_init) * 2), larval_seq,
1878		- &larval_seq_len);
1879		- rc = send_request_init(drvdata, larval_seq, larval_seq_len);
	1936	+ if (large_sha_supported) {
	1937	+ rc = cc_init_copy_sram(drvdata, cc_sha384_init,
	1938	+ sizeof(cc_sha384_init), &sram_buff_ofs);
	1939	+ if (rc)
	1940	+ goto init_digest_const_err;
	1941	+
	1942	+ rc = cc_init_copy_sram(drvdata, cc_sha512_init,
	1943	+ sizeof(cc_sha512_init), &sram_buff_ofs);
1880	1944	if (rc)
1881	1945	goto init_digest_const_err;
1882	1946	}
..	..	@@ -1885,57 +1949,37 @@
1885	1949	return rc;
1886	1950	}
1887	1951
1888		-static void __init cc_swap_dwords(u32 *buf, unsigned long size)
1889		-{
1890		- int i;
1891		- u32 tmp;
1892		-
1893		- for (i = 0; i < size; i += 2) {
1894		- tmp = buf[i];
1895		- buf[i] = buf[i + 1];
1896		- buf[i + 1] = tmp;
1897		- }
1898		-}
1899		-
1900		-/*
1901		- * Due to the way the HW works we need to swap every
1902		- * double word in the SHA384 and SHA512 larval hashes
1903		- */
1904		-void __init cc_hash_global_init(void)
1905		-{
1906		- cc_swap_dwords((u32 )&sha384_init, (ARRAY_SIZE(sha384_init) 2));
1907		- cc_swap_dwords((u32 )&sha512_init, (ARRAY_SIZE(sha512_init) 2));
1908		-}
1909		-
1910	1952	int cc_hash_alloc(struct cc_drvdata *drvdata)
1911	1953	{
1912	1954	struct cc_hash_handle *hash_handle;
1913		- cc_sram_addr_t sram_buff;
	1955	+ u32 sram_buff;
1914	1956	u32 sram_size_to_alloc;
1915	1957	struct device *dev = drvdata_to_dev(drvdata);
1916	1958	int rc = 0;
1917	1959	int alg;
1918	1960
1919		- hash_handle = kzalloc(sizeof(*hash_handle), GFP_KERNEL);
	1961	+ hash_handle = devm_kzalloc(dev, sizeof(*hash_handle), GFP_KERNEL);
1920	1962	if (!hash_handle)
1921	1963	return -ENOMEM;
1922	1964
1923	1965	INIT_LIST_HEAD(&hash_handle->hash_list);
1924	1966	drvdata->hash_handle = hash_handle;
1925	1967
1926		- sram_size_to_alloc = sizeof(digest_len_init) +
1927		- sizeof(md5_init) +
1928		- sizeof(sha1_init) +
1929		- sizeof(sha224_init) +
1930		- sizeof(sha256_init);
	1968	+ sram_size_to_alloc = sizeof(cc_digest_len_init) +
	1969	+ sizeof(cc_md5_init) +
	1970	+ sizeof(cc_sha1_init) +
	1971	+ sizeof(cc_sha224_init) +
	1972	+ sizeof(cc_sha256_init);
	1973	+
	1974	+ if (drvdata->hw_rev >= CC_HW_REV_713)
	1975	+ sram_size_to_alloc += sizeof(cc_sm3_init);
1931	1976
1932	1977	if (drvdata->hw_rev >= CC_HW_REV_712)
1933		- sram_size_to_alloc += sizeof(digest_len_sha512_init) +
1934		- sizeof(sha384_init) + sizeof(sha512_init);
	1978	+ sram_size_to_alloc += sizeof(cc_digest_len_sha512_init) +
	1979	+ sizeof(cc_sha384_init) + sizeof(cc_sha512_init);
1935	1980
1936	1981	sram_buff = cc_sram_alloc(drvdata, sram_size_to_alloc);
1937	1982	if (sram_buff == NULL_SRAM_ADDR) {
1938		- dev_err(dev, "SRAM pool exhausted\n");
1939	1983	rc = -ENOMEM;
1940	1984	goto fail;
1941	1985	}
..	..	@@ -1955,30 +1999,31 @@
1955	1999	struct cc_hash_alg *t_alg;
1956	2000	int hw_mode = driver_hash[alg].hw_mode;
1957	2001
1958		- /* We either support both HASH and MAC or none */
1959		- if (driver_hash[alg].min_hw_rev > drvdata->hw_rev)
	2002	+ /* Check that the HW revision and variants are suitable */
	2003	+ if ((driver_hash[alg].min_hw_rev > drvdata->hw_rev) \|\|
	2004	+ !(drvdata->std_bodies & driver_hash[alg].std_body))
1960	2005	continue;
1961	2006
1962		- /* register hmac version */
1963		- t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, true);
1964		- if (IS_ERR(t_alg)) {
1965		- rc = PTR_ERR(t_alg);
1966		- dev_err(dev, "%s alg allocation failed\n",
1967		- driver_hash[alg].driver_name);
1968		- goto fail;
1969		- }
1970		- t_alg->drvdata = drvdata;
	2007	+ if (driver_hash[alg].is_mac) {
	2008	+ /* register hmac version */
	2009	+ t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, true);
	2010	+ if (IS_ERR(t_alg)) {
	2011	+ rc = PTR_ERR(t_alg);
	2012	+ dev_err(dev, "%s alg allocation failed\n",
	2013	+ driver_hash[alg].driver_name);
	2014	+ goto fail;
	2015	+ }
	2016	+ t_alg->drvdata = drvdata;
1971	2017
1972		- rc = crypto_register_ahash(&t_alg->ahash_alg);
1973		- if (rc) {
1974		- dev_err(dev, "%s alg registration failed\n",
1975		- driver_hash[alg].driver_name);
1976		- kfree(t_alg);
1977		- goto fail;
1978		- } else {
	2018	+ rc = crypto_register_ahash(&t_alg->ahash_alg);
	2019	+ if (rc) {
	2020	+ dev_err(dev, "%s alg registration failed\n",
	2021	+ driver_hash[alg].driver_name);
	2022	+ goto fail;
	2023	+ }
	2024	+
1979	2025	list_add_tail(&t_alg->entry, &hash_handle->hash_list);
1980	2026	}
1981		-
1982	2027	if (hw_mode == DRV_CIPHER_XCBC_MAC \|\|
1983	2028	hw_mode == DRV_CIPHER_CMAC)
1984	2029	continue;
..	..	@@ -1997,18 +2042,16 @@
1997	2042	if (rc) {
1998	2043	dev_err(dev, "%s alg registration failed\n",
1999	2044	driver_hash[alg].driver_name);
2000		- kfree(t_alg);
2001	2045	goto fail;
2002		- } else {
2003		- list_add_tail(&t_alg->entry, &hash_handle->hash_list);
2004	2046	}
	2047	+
	2048	+ list_add_tail(&t_alg->entry, &hash_handle->hash_list);
2005	2049	}
2006	2050
2007	2051	return 0;
2008	2052
2009	2053	fail:
2010		- kfree(drvdata->hash_handle);
2011		- drvdata->hash_handle = NULL;
	2054	+ cc_hash_free(drvdata);
2012	2055	return rc;
2013	2056	}
2014	2057
..	..	@@ -2017,17 +2060,12 @@
2017	2060	struct cc_hash_alg t_hash_alg, hash_n;
2018	2061	struct cc_hash_handle *hash_handle = drvdata->hash_handle;
2019	2062
2020		- if (hash_handle) {
2021		- list_for_each_entry_safe(t_hash_alg, hash_n,
2022		- &hash_handle->hash_list, entry) {
2023		- crypto_unregister_ahash(&t_hash_alg->ahash_alg);
2024		- list_del(&t_hash_alg->entry);
2025		- kfree(t_hash_alg);
2026		- }
2027		-
2028		- kfree(hash_handle);
2029		- drvdata->hash_handle = NULL;
	2063	+ list_for_each_entry_safe(t_hash_alg, hash_n, &hash_handle->hash_list,
	2064	+ entry) {
	2065	+ crypto_unregister_ahash(&t_hash_alg->ahash_alg);
	2066	+ list_del(&t_hash_alg->entry);
2030	2067	}
	2068	+
2031	2069	return 0;
2032	2070	}
2033	2071
..	..	@@ -2045,7 +2083,7 @@
2045	2083	XCBC_MAC_K1_OFFSET),
2046	2084	CC_AES_128_BIT_KEY_SIZE, NS_BIT);
2047	2085	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
2048		- set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
	2086	+ set_hash_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC, ctx->hash_mode);
2049	2087	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2050	2088	set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
2051	2089	set_flow_mode(&desc[idx], S_DIN_to_AES);
..	..	@@ -2169,37 +2207,42 @@
2169	2207	{
2170	2208	switch (mode) {
2171	2209	case DRV_HASH_MD5:
2172		- return md5_init;
	2210	+ return cc_md5_init;
2173	2211	case DRV_HASH_SHA1:
2174		- return sha1_init;
	2212	+ return cc_sha1_init;
2175	2213	case DRV_HASH_SHA224:
2176		- return sha224_init;
	2214	+ return cc_sha224_init;
2177	2215	case DRV_HASH_SHA256:
2178		- return sha256_init;
	2216	+ return cc_sha256_init;
2179	2217	case DRV_HASH_SHA384:
2180		- return sha384_init;
	2218	+ return cc_sha384_init;
2181	2219	case DRV_HASH_SHA512:
2182		- return sha512_init;
	2220	+ return cc_sha512_init;
	2221	+ case DRV_HASH_SM3:
	2222	+ return cc_sm3_init;
2183	2223	default:
2184	2224	dev_err(dev, "Invalid hash mode (%d)\n", mode);
2185		- return md5_init;
	2225	+ return cc_md5_init;
2186	2226	}
2187	2227	}
2188	2228
2189		-/*!
2190		- * Gets the address of the initial digest in SRAM
	2229	+/**
	2230	+ * cc_larval_digest_addr() - Get the address of the initial digest in SRAM
2191	2231	* according to the given hash mode
2192	2232	*
2193		- * \param drvdata
2194		- * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256
	2233	+ * @drvdata: Associated device driver context
	2234	+ * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256
2195	2235	*
2196		- * \return u32 The address of the initial digest in SRAM
	2236	+ * Return:
	2237	+ * The address of the initial digest in SRAM
2197	2238	*/
2198		-cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode)
	2239	+u32 cc_larval_digest_addr(void *drvdata, u32 mode)
2199	2240	{
2200	2241	struct cc_drvdata _drvdata = (struct cc_drvdata )drvdata;
2201	2242	struct cc_hash_handle *hash_handle = _drvdata->hash_handle;
2202	2243	struct device *dev = drvdata_to_dev(_drvdata);
	2244	+ bool sm3_supported = (_drvdata->hw_rev >= CC_HW_REV_713);
	2245	+ u32 addr;
2203	2246
2204	2247	switch (mode) {
2205	2248	case DRV_HASH_NULL:
..	..	@@ -2208,29 +2251,41 @@
2208	2251	return (hash_handle->larval_digest_sram_addr);
2209	2252	case DRV_HASH_SHA1:
2210	2253	return (hash_handle->larval_digest_sram_addr +
2211		- sizeof(md5_init));
	2254	+ sizeof(cc_md5_init));
2212	2255	case DRV_HASH_SHA224:
2213	2256	return (hash_handle->larval_digest_sram_addr +
2214		- sizeof(md5_init) +
2215		- sizeof(sha1_init));
	2257	+ sizeof(cc_md5_init) +
	2258	+ sizeof(cc_sha1_init));
2216	2259	case DRV_HASH_SHA256:
2217	2260	return (hash_handle->larval_digest_sram_addr +
2218		- sizeof(md5_init) +
2219		- sizeof(sha1_init) +
2220		- sizeof(sha224_init));
	2261	+ sizeof(cc_md5_init) +
	2262	+ sizeof(cc_sha1_init) +
	2263	+ sizeof(cc_sha224_init));
	2264	+ case DRV_HASH_SM3:
	2265	+ return (hash_handle->larval_digest_sram_addr +
	2266	+ sizeof(cc_md5_init) +
	2267	+ sizeof(cc_sha1_init) +
	2268	+ sizeof(cc_sha224_init) +
	2269	+ sizeof(cc_sha256_init));
2221	2270	case DRV_HASH_SHA384:
2222		- return (hash_handle->larval_digest_sram_addr +
2223		- sizeof(md5_init) +
2224		- sizeof(sha1_init) +
2225		- sizeof(sha224_init) +
2226		- sizeof(sha256_init));
	2271	+ addr = (hash_handle->larval_digest_sram_addr +
	2272	+ sizeof(cc_md5_init) +
	2273	+ sizeof(cc_sha1_init) +
	2274	+ sizeof(cc_sha224_init) +
	2275	+ sizeof(cc_sha256_init));
	2276	+ if (sm3_supported)
	2277	+ addr += sizeof(cc_sm3_init);
	2278	+ return addr;
2227	2279	case DRV_HASH_SHA512:
2228		- return (hash_handle->larval_digest_sram_addr +
2229		- sizeof(md5_init) +
2230		- sizeof(sha1_init) +
2231		- sizeof(sha224_init) +
2232		- sizeof(sha256_init) +
2233		- sizeof(sha384_init));
	2280	+ addr = (hash_handle->larval_digest_sram_addr +
	2281	+ sizeof(cc_md5_init) +
	2282	+ sizeof(cc_sha1_init) +
	2283	+ sizeof(cc_sha224_init) +
	2284	+ sizeof(cc_sha256_init) +
	2285	+ sizeof(cc_sha384_init));
	2286	+ if (sm3_supported)
	2287	+ addr += sizeof(cc_sm3_init);
	2288	+ return addr;
2234	2289	default:
2235	2290	dev_err(dev, "Invalid hash mode (%d)\n", mode);
2236	2291	}
..	..	@@ -2239,12 +2294,11 @@
2239	2294	return hash_handle->larval_digest_sram_addr;
2240	2295	}
2241	2296
2242		-cc_sram_addr_t
2243		-cc_digest_len_addr(void *drvdata, u32 mode)
	2297	+u32 cc_digest_len_addr(void *drvdata, u32 mode)
2244	2298	{
2245	2299	struct cc_drvdata _drvdata = (struct cc_drvdata )drvdata;
2246	2300	struct cc_hash_handle *hash_handle = _drvdata->hash_handle;
2247		- cc_sram_addr_t digest_len_addr = hash_handle->digest_len_sram_addr;
	2301	+ u32 digest_len_addr = hash_handle->digest_len_sram_addr;
2248	2302
2249	2303	switch (mode) {
2250	2304	case DRV_HASH_SHA1:
..	..	@@ -2252,11 +2306,9 @@
2252	2306	case DRV_HASH_SHA256:
2253	2307	case DRV_HASH_MD5:
2254	2308	return digest_len_addr;
2255		-#if (CC_DEV_SHA_MAX > 256)
2256	2309	case DRV_HASH_SHA384:
2257	2310	case DRV_HASH_SHA512:
2258		- return digest_len_addr + sizeof(digest_len_init);
2259		-#endif
	2311	+ return digest_len_addr + sizeof(cc_digest_len_init);
2260	2312	default:
2261	2313	return digest_len_addr; /to avoid kernel crash/
2262	2314	}