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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/crypto/caam/regs.h
....@@ -3,6 +3,7 @@
33  * CAAM hardware register-level view
44  *
55  * Copyright 2008-2011 Freescale Semiconductor, Inc.
6
+ * Copyright 2018 NXP
67  */
78 
89 #ifndef REGS_H
....@@ -11,6 +12,7 @@
1112 #include <linux/types.h>
1213 #include <linux/bitops.h>
1314 #include <linux/io.h>
15
+#include <linux/io-64-nonatomic-hi-lo.h>
1416 
1517 /*
1618  * Architecture-specific register access methods
....@@ -69,6 +71,7 @@
6971 
7072 extern bool caam_little_end;
7173 extern bool caam_imx;
74
+extern size_t caam_ptr_sz;
7275 
7376 #define caam_to_cpu(len)						\
7477 static inline u##len caam##len ## _to_cpu(u##len val)			\
....@@ -136,51 +139,48 @@
136139  *    base + 0x0000 : least-significant 32 bits
137140  *    base + 0x0004 : most-significant 32 bits
138141  */
139
-#ifdef CONFIG_64BIT
140142 static inline void wr_reg64(void __iomem *reg, u64 data)
141143 {
142
-	if (caam_little_end)
143
-		iowrite64(data, reg);
144
-	else
145
-		iowrite64be(data, reg);
146
-}
147
-
148
-static inline u64 rd_reg64(void __iomem *reg)
149
-{
150
-	if (caam_little_end)
151
-		return ioread64(reg);
152
-	else
153
-		return ioread64be(reg);
154
-}
155
-
156
-#else /* CONFIG_64BIT */
157
-static inline void wr_reg64(void __iomem *reg, u64 data)
158
-{
159
-	if (!caam_imx && caam_little_end) {
160
-		wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
161
-		wr_reg32((u32 __iomem *)(reg), data);
144
+	if (caam_little_end) {
145
+		if (caam_imx) {
146
+			iowrite32(data >> 32, (u32 __iomem *)(reg));
147
+			iowrite32(data, (u32 __iomem *)(reg) + 1);
148
+		} else {
149
+			iowrite64(data, reg);
150
+		}
162151 	} else {
163
-		wr_reg32((u32 __iomem *)(reg), data >> 32);
164
-		wr_reg32((u32 __iomem *)(reg) + 1, data);
152
+		iowrite64be(data, reg);
165153 	}
166154 }
167155 
168156 static inline u64 rd_reg64(void __iomem *reg)
169157 {
170
-	if (!caam_imx && caam_little_end)
171
-		return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
172
-			(u64)rd_reg32((u32 __iomem *)(reg)));
158
+	if (caam_little_end) {
159
+		if (caam_imx) {
160
+			u32 low, high;
173161 
174
-	return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
175
-		(u64)rd_reg32((u32 __iomem *)(reg) + 1));
162
+			high = ioread32(reg);
163
+			low  = ioread32(reg + sizeof(u32));
164
+
165
+			return low + ((u64)high << 32);
166
+		} else {
167
+			return ioread64(reg);
168
+		}
169
+	} else {
170
+		return ioread64be(reg);
171
+	}
176172 }
177
-#endif /* CONFIG_64BIT  */
178173 
179174 static inline u64 cpu_to_caam_dma64(dma_addr_t value)
180175 {
181
-	if (caam_imx)
182
-		return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
183
-			 (u64)cpu_to_caam32(upper_32_bits(value)));
176
+	if (caam_imx) {
177
+		u64 ret_val = (u64)cpu_to_caam32(lower_32_bits(value)) << 32;
178
+
179
+		if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
180
+			ret_val |= (u64)cpu_to_caam32(upper_32_bits(value));
181
+
182
+		return ret_val;
183
+	}
184184 
185185 	return cpu_to_caam64(value);
186186 }
....@@ -194,22 +194,136 @@
194194 	return caam64_to_cpu(value);
195195 }
196196 
197
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
198
-#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
199
-#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
200
-#else
201
-#define cpu_to_caam_dma(value) cpu_to_caam32(value)
202
-#define caam_dma_to_cpu(value) caam32_to_cpu(value)
203
-#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
197
+static inline u64 cpu_to_caam_dma(u64 value)
198
+{
199
+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
200
+	    caam_ptr_sz == sizeof(u64))
201
+		return cpu_to_caam_dma64(value);
202
+	else
203
+		return cpu_to_caam32(value);
204
+}
205
+
206
+static inline u64 caam_dma_to_cpu(u64 value)
207
+{
208
+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
209
+	    caam_ptr_sz == sizeof(u64))
210
+		return caam_dma64_to_cpu(value);
211
+	else
212
+		return caam32_to_cpu(value);
213
+}
204214 
205215 /*
206216  * jr_outentry
207217  * Represents each entry in a JobR output ring
208218  */
209
-struct jr_outentry {
210
-	dma_addr_t desc;/* Pointer to completed descriptor */
211
-	u32 jrstatus;	/* Status for completed descriptor */
212
-} __packed;
219
+
220
+static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
221
+				   u32 *jrstatus)
222
+{
223
+
224
+	if (caam_ptr_sz == sizeof(u32)) {
225
+		struct {
226
+			u32 desc;
227
+			u32 jrstatus;
228
+		} __packed *outentry = outring;
229
+
230
+		*desc = outentry[hw_idx].desc;
231
+		*jrstatus = outentry[hw_idx].jrstatus;
232
+	} else {
233
+		struct {
234
+			dma_addr_t desc;/* Pointer to completed descriptor */
235
+			u32 jrstatus;	/* Status for completed descriptor */
236
+		} __packed *outentry = outring;
237
+
238
+		*desc = outentry[hw_idx].desc;
239
+		*jrstatus = outentry[hw_idx].jrstatus;
240
+	}
241
+}
242
+
243
+#define SIZEOF_JR_OUTENTRY	(caam_ptr_sz + sizeof(u32))
244
+
245
+static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx)
246
+{
247
+	dma_addr_t desc;
248
+	u32 unused;
249
+
250
+	jr_outentry_get(outring, hw_idx, &desc, &unused);
251
+
252
+	return desc;
253
+}
254
+
255
+static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
256
+{
257
+	dma_addr_t unused;
258
+	u32 jrstatus;
259
+
260
+	jr_outentry_get(outring, hw_idx, &unused, &jrstatus);
261
+
262
+	return jrstatus;
263
+}
264
+
265
+static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
266
+{
267
+	if (caam_ptr_sz == sizeof(u32)) {
268
+		u32 *inpentry = inpring;
269
+
270
+		inpentry[hw_idx] = val;
271
+	} else {
272
+		dma_addr_t *inpentry = inpring;
273
+
274
+		inpentry[hw_idx] = val;
275
+	}
276
+}
277
+
278
+#define SIZEOF_JR_INPENTRY	caam_ptr_sz
279
+
280
+
281
+/* Version registers (Era 10+)	e80-eff */
282
+struct version_regs {
283
+	u32 crca;	/* CRCA_VERSION */
284
+	u32 afha;	/* AFHA_VERSION */
285
+	u32 kfha;	/* KFHA_VERSION */
286
+	u32 pkha;	/* PKHA_VERSION */
287
+	u32 aesa;	/* AESA_VERSION */
288
+	u32 mdha;	/* MDHA_VERSION */
289
+	u32 desa;	/* DESA_VERSION */
290
+	u32 snw8a;	/* SNW8A_VERSION */
291
+	u32 snw9a;	/* SNW9A_VERSION */
292
+	u32 zuce;	/* ZUCE_VERSION */
293
+	u32 zuca;	/* ZUCA_VERSION */
294
+	u32 ccha;	/* CCHA_VERSION */
295
+	u32 ptha;	/* PTHA_VERSION */
296
+	u32 rng;	/* RNG_VERSION */
297
+	u32 trng;	/* TRNG_VERSION */
298
+	u32 aaha;	/* AAHA_VERSION */
299
+	u32 rsvd[10];
300
+	u32 sr;		/* SR_VERSION */
301
+	u32 dma;	/* DMA_VERSION */
302
+	u32 ai;		/* AI_VERSION */
303
+	u32 qi;		/* QI_VERSION */
304
+	u32 jr;		/* JR_VERSION */
305
+	u32 deco;	/* DECO_VERSION */
306
+};
307
+
308
+/* Version registers bitfields */
309
+
310
+/* Number of CHAs instantiated */
311
+#define CHA_VER_NUM_MASK	0xffull
312
+/* CHA Miscellaneous Information */
313
+#define CHA_VER_MISC_SHIFT	8
314
+#define CHA_VER_MISC_MASK	(0xffull << CHA_VER_MISC_SHIFT)
315
+/* CHA Revision Number */
316
+#define CHA_VER_REV_SHIFT	16
317
+#define CHA_VER_REV_MASK	(0xffull << CHA_VER_REV_SHIFT)
318
+/* CHA Version ID */
319
+#define CHA_VER_VID_SHIFT	24
320
+#define CHA_VER_VID_MASK	(0xffull << CHA_VER_VID_SHIFT)
321
+
322
+/* CHA Miscellaneous Information - AESA_MISC specific */
323
+#define CHA_VER_MISC_AES_GCM	BIT(1 + CHA_VER_MISC_SHIFT)
324
+
325
+/* CHA Miscellaneous Information - PKHA_MISC specific */
326
+#define CHA_VER_MISC_PKHA_NO_CRYPT	BIT(7 + CHA_VER_MISC_SHIFT)
213327 
214328 /*
215329  * caam_perfmon - Performance Monitor/Secure Memory Status/
....@@ -223,15 +337,13 @@
223337 #define CHA_NUM_MS_DECONUM_MASK	(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
224338 
225339 /*
226
- * CHA version IDs / instantiation bitfields
340
+ * CHA version IDs / instantiation bitfields (< Era 10)
227341  * Defined for use with the cha_id fields in perfmon, but the same shift/mask
228342  * selectors can be used to pull out the number of instantiated blocks within
229343  * cha_num fields in perfmon because the locations are the same.
230344  */
231345 #define CHA_ID_LS_AES_SHIFT	0
232346 #define CHA_ID_LS_AES_MASK	(0xfull << CHA_ID_LS_AES_SHIFT)
233
-#define CHA_ID_LS_AES_LP	(0x3ull << CHA_ID_LS_AES_SHIFT)
234
-#define CHA_ID_LS_AES_HP	(0x4ull << CHA_ID_LS_AES_SHIFT)
235347 
236348 #define CHA_ID_LS_DES_SHIFT	4
237349 #define CHA_ID_LS_DES_MASK	(0xfull << CHA_ID_LS_DES_SHIFT)
....@@ -241,9 +353,6 @@
241353 
242354 #define CHA_ID_LS_MD_SHIFT	12
243355 #define CHA_ID_LS_MD_MASK	(0xfull << CHA_ID_LS_MD_SHIFT)
244
-#define CHA_ID_LS_MD_LP256	(0x0ull << CHA_ID_LS_MD_SHIFT)
245
-#define CHA_ID_LS_MD_LP512	(0x1ull << CHA_ID_LS_MD_SHIFT)
246
-#define CHA_ID_LS_MD_HP		(0x2ull << CHA_ID_LS_MD_SHIFT)
247356 
248357 #define CHA_ID_LS_RNG_SHIFT	16
249358 #define CHA_ID_LS_RNG_MASK	(0xfull << CHA_ID_LS_RNG_SHIFT)
....@@ -269,6 +378,13 @@
269378 #define CHA_ID_MS_JR_SHIFT	28
270379 #define CHA_ID_MS_JR_MASK	(0xfull << CHA_ID_MS_JR_SHIFT)
271380 
381
+/* Specific CHA version IDs */
382
+#define CHA_VER_VID_AES_LP	0x3ull
383
+#define CHA_VER_VID_AES_HP	0x4ull
384
+#define CHA_VER_VID_MD_LP256	0x0ull
385
+#define CHA_VER_VID_MD_LP512	0x1ull
386
+#define CHA_VER_VID_MD_HP	0x2ull
387
+
272388 struct sec_vid {
273389 	u16 ip_id;
274390 	u8 maj_rev;
....@@ -291,6 +407,7 @@
291407 	u32 cha_rev_ls;		/* CRNR - CHA Rev No. Least significant half*/
292408 #define CTPR_MS_QI_SHIFT	25
293409 #define CTPR_MS_QI_MASK		(0x1ull << CTPR_MS_QI_SHIFT)
410
+#define CTPR_MS_PS		BIT(17)
294411 #define CTPR_MS_DPAA2		BIT(13)
295412 #define CTPR_MS_VIRT_EN_INCL	0x00000001
296413 #define CTPR_MS_VIRT_EN_POR	0x00000002
....@@ -378,7 +495,8 @@
378495 
379496 /* RNG4 TRNG test registers */
380497 struct rng4tst {
381
-#define RTMCTL_PRGM	0x00010000	/* 1 -> program mode, 0 -> run mode */
498
+#define RTMCTL_ACC  BIT(5)  /* TRNG access mode */
499
+#define RTMCTL_PRGM BIT(16) /* 1 -> program mode, 0 -> run mode */
382500 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC	0 /* use von Neumann data in
383501 						     both entropy shifter and
384502 						     statistical checker */
....@@ -414,9 +532,11 @@
414532 	u32 rsvd1[40];
415533 #define RDSTA_SKVT 0x80000000
416534 #define RDSTA_SKVN 0x40000000
535
+#define RDSTA_PR0 BIT(4)
536
+#define RDSTA_PR1 BIT(5)
417537 #define RDSTA_IF0 0x00000001
418538 #define RDSTA_IF1 0x00000002
419
-#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
539
+#define RDSTA_MASK (RDSTA_PR1 | RDSTA_PR0 | RDSTA_IF1 | RDSTA_IF0)
420540 	u32 rdsta;
421541 	u32 rsvd2[15];
422542 };
....@@ -479,8 +599,10 @@
479599 		struct rng4tst r4tst[2];
480600 	};
481601 
482
-	u32 rsvd9[448];
602
+	u32 rsvd9[416];
483603 
604
+	/* Version registers - introduced with era 10		e80-eff */
605
+	struct version_regs vreg;
484606 	/* Performance Monitor                                  f00-fff */
485607 	struct caam_perfmon perfmon;
486608 };
....@@ -570,8 +692,10 @@
570692 	u32 rsvd11;
571693 	u32 jrcommand;	/* JRCRx - JobR command */
572694 
573
-	u32 rsvd12[932];
695
+	u32 rsvd12[900];
574696 
697
+	/* Version registers - introduced with era 10           e80-eff */
698
+	struct version_regs vreg;
575699 	/* Performance Monitor                                  f00-fff */
576700 	struct caam_perfmon perfmon;
577701 };
....@@ -590,6 +714,7 @@
590714 #define JRSTA_SSRC_CCB_ERROR        0x20000000
591715 #define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
592716 #define JRSTA_SSRC_DECO             0x40000000
717
+#define JRSTA_SSRC_QI               0x50000000
593718 #define JRSTA_SSRC_JRERROR          0x60000000
594719 #define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
595720 
....@@ -632,6 +757,8 @@
632757 #define JRSTA_DECOERR_SEQOVF        0x85
633758 #define JRSTA_DECOERR_INVSIGN       0x86
634759 #define JRSTA_DECOERR_DSASIGN       0x87
760
+
761
+#define JRSTA_QIERR_ERROR_MASK      0x00ff
635762 
636763 #define JRSTA_CCBERR_JUMP           0x08000000
637764 #define JRSTA_CCBERR_INDEX_MASK     0xff00
....@@ -876,13 +1003,19 @@
8761003 	u32 rsvd29[48];
8771004 	u32 descbuf[64];	/* DxDESB - Descriptor buffer */
8781005 	u32 rscvd30[193];
879
-#define DESC_DBG_DECO_STAT_HOST_ERR	0x00D00000
8801006 #define DESC_DBG_DECO_STAT_VALID	0x80000000
8811007 #define DESC_DBG_DECO_STAT_MASK		0x00F00000
1008
+#define DESC_DBG_DECO_STAT_SHIFT	20
8821009 	u32 desc_dbg;		/* DxDDR - DECO Debug Register */
883
-	u32 rsvd31[126];
1010
+	u32 rsvd31[13];
1011
+#define DESC_DER_DECO_STAT_MASK		0x000F0000
1012
+#define DESC_DER_DECO_STAT_SHIFT	16
1013
+	u32 dbg_exec;		/* DxDER - DECO Debug Exec Register */
1014
+	u32 rsvd32[112];
8841015 };
8851016 
1017
+#define DECO_STAT_HOST_ERR	0xD
1018
+
8861019 #define DECO_JQCR_WHL		0x20000000
8871020 #define DECO_JQCR_FOUR		0x10000000
8881021