mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/cpufreq/s3c2412-cpufreq.c
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@@ -1,13 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright 2008 Simtec Electronics
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  *	http://armlinux.simtec.co.uk/
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  *	Ben Dooks <ben@simtec.co.uk>
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  *
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  * S3C2412 CPU Frequency scalling
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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 */
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 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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@@ -22,15 +19,24 @@
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 #include <linux/clk.h>
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 #include <linux/err.h>
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 #include <linux/io.h>
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+#include <linux/soc/samsung/s3c-cpufreq-core.h>
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+#include <linux/soc/samsung/s3c-pm.h>
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 #include <asm/mach/arch.h>
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 #include <asm/mach/map.h>
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-#include <mach/regs-clock.h>
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-#include <mach/s3c2412.h>
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-
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-#include <plat/cpu.h>
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-#include <plat/cpu-freq-core.h>
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+#define S3C2412_CLKDIVN_PDIVN		(1<<2)
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+#define S3C2412_CLKDIVN_HDIVN_MASK	(3<<0)
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+#define S3C2412_CLKDIVN_ARMDIVN		(1<<3)
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+#define S3C2412_CLKDIVN_DVSEN		(1<<4)
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+#define S3C2412_CLKDIVN_HALFHCLK	(1<<5)
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+#define S3C2412_CLKDIVN_USB48DIV	(1<<6)
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+#define S3C2412_CLKDIVN_UARTDIV_MASK	(15<<8)
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+#define S3C2412_CLKDIVN_UARTDIV_SHIFT	(8)
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+#define S3C2412_CLKDIVN_I2SDIV_MASK	(15<<12)
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+#define S3C2412_CLKDIVN_I2SDIV_SHIFT	(12)
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+#define S3C2412_CLKDIVN_CAMDIV_MASK	(15<<16)
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+#define S3C2412_CLKDIVN_CAMDIV_SHIFT	(16)
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 /* our clock resources. */
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 static struct clk *xtal;
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@@ -120,7 +126,7 @@
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 	unsigned long clkdiv;
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 	unsigned long olddiv;
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-	olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
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+	olddiv = clkdiv = s3c24xx_read_clkdivn();
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 	/* clear off current clock info */
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@@ -137,30 +143,9 @@
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 		clkdiv |= S3C2412_CLKDIVN_PDIVN;
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 	s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
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-	__raw_writel(clkdiv, S3C2410_CLKDIVN);
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+	s3c24xx_write_clkdivn(clkdiv);
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 	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
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-}
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-
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-static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
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-{
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-	struct s3c_cpufreq_board *board = cfg->board;
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-	unsigned long refresh;
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-
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-	s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
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-		     board->refresh, cfg->freq.hclk);
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-
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-	/* Reduce both the refresh time (in ns) and the frequency (in MHz)
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-	 * by 10 each to ensure that we do not overflow 32 bit numbers. This
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-	 * should work for HCLK up to 133MHz and refresh period up to 30usec.
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-	 */
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-
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-	refresh = (board->refresh / 10);
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-	refresh *= (cfg->freq.hclk / 100);
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-	refresh /= (1 * 1000 * 1000);	/* 10^6 */
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-
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-	s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
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-	__raw_writel(refresh, S3C2412_REFRESH);
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 }
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 /* set the default cpu frequency information, based on an 200MHz part