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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/clk/ti/dpll3xxx.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * OMAP3/4 - specific DPLL control functions
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  *
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@@ -12,10 +13,6 @@
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  *
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  * Parts of this code are based on code written by
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  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/kernel.h>
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@@ -731,7 +728,7 @@
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 	do {
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 		do {
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 			hw = clk_hw_get_parent(hw);
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-		} while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
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+		} while (hw && (!omap2_clk_is_hw_omap(hw)));
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 		if (!hw)
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 			break;
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 		pclk = to_clk_hw_omap(hw);
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@@ -782,6 +779,130 @@
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 	return rate;
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 }
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+/**
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+ * omap3_core_dpll_save_context - Save the m and n values of the divider
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+ * @hw: pointer  struct clk_hw
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+ *
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+ * Before the dpll registers are lost save the last rounded rate m and n
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+ * and the enable mask.
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+ */
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+int omap3_core_dpll_save_context(struct clk_hw *hw)
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+{
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+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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+	struct dpll_data *dd;
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+	u32 v;
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+
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+	dd = clk->dpll_data;
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+
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+	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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+	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
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+
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+	if (clk->context == DPLL_LOCKED) {
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+		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
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+		dd->last_rounded_m = (v & dd->mult_mask) >>
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+						__ffs(dd->mult_mask);
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+		dd->last_rounded_n = ((v & dd->div1_mask) >>
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+						__ffs(dd->div1_mask)) + 1;
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+	}
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+
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+	return 0;
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+}
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+
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+/**
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+ * omap3_core_dpll_restore_context - restore the m and n values of the divider
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+ * @hw: pointer  struct clk_hw
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+ *
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+ * Restore the last rounded rate m and n
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+ * and the enable mask.
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+ */
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+void omap3_core_dpll_restore_context(struct clk_hw *hw)
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+{
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+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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+	const struct dpll_data *dd;
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+	u32 v;
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+
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+	dd = clk->dpll_data;
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+
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+	if (clk->context == DPLL_LOCKED) {
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+		_omap3_dpll_write_clken(clk, 0x4);
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+		_omap3_wait_dpll_status(clk, 0);
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+
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+		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
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+		v &= ~(dd->mult_mask | dd->div1_mask);
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+		v |= dd->last_rounded_m << __ffs(dd->mult_mask);
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+		v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
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+		ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
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+
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+		_omap3_dpll_write_clken(clk, DPLL_LOCKED);
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+		_omap3_wait_dpll_status(clk, 1);
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+	} else {
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+		_omap3_dpll_write_clken(clk, clk->context);
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+	}
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+}
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+
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+/**
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+ * omap3_non_core_dpll_save_context - Save the m and n values of the divider
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+ * @hw: pointer  struct clk_hw
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+ *
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+ * Before the dpll registers are lost save the last rounded rate m and n
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+ * and the enable mask.
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+ */
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+int omap3_noncore_dpll_save_context(struct clk_hw *hw)
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+{
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+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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+	struct dpll_data *dd;
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+	u32 v;
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+
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+	dd = clk->dpll_data;
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+
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+	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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+	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
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+
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+	if (clk->context == DPLL_LOCKED) {
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+		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
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+		dd->last_rounded_m = (v & dd->mult_mask) >>
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+						__ffs(dd->mult_mask);
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+		dd->last_rounded_n = ((v & dd->div1_mask) >>
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+						__ffs(dd->div1_mask)) + 1;
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+	}
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+
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+	return 0;
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+}
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+
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+/**
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+ * omap3_core_dpll_restore_context - restore the m and n values of the divider
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+ * @hw: pointer  struct clk_hw
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+ *
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+ * Restore the last rounded rate m and n
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+ * and the enable mask.
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+ */
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+void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
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+{
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+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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+	const struct dpll_data *dd;
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+	u32 ctrl, mult_div1;
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+
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+	dd = clk->dpll_data;
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+
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+	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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+	mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
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+
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+	if (clk->context == ((ctrl & dd->enable_mask) >>
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+			     __ffs(dd->enable_mask)) &&
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+	    dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
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+				   __ffs(dd->mult_mask)) &&
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+	    dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
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+				   __ffs(dd->div1_mask)) + 1) {
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+		/* nothing to be done */
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+		return;
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+	}
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+
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+	if (clk->context == DPLL_LOCKED)
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+		omap3_noncore_dpll_program(clk, 0);
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+	else
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+		_omap3_dpll_write_clken(clk, clk->context);
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+}
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+
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 /* OMAP3/4 non-CORE DPLL clkops */
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 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
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 	.allow_idle	= omap3_dpll_allow_idle,