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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
....@@ -1,17 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3
- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk-provider.h>
7
+#include <linux/io.h>
158 #include <linux/of_address.h>
169 
1710 #include "ccu_common.h"
....@@ -51,18 +44,29 @@
5144  * the base (2x, 4x and 8x), and one variable divider (the one true
5245  * pll audio).
5346  *
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- * We don't have any need for the variable divider for now, so we just
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- * hardcode it to match with the clock names
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+ * With sigma-delta modulation for fractional-N on the audio PLL,
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+ * we have to use specific dividers. This means the variable divider
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+ * can no longer be used, as the audio codec requests the exact clock
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+ * rates we support through this mechanism. So we now hard code the
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+ * variable divider to 1. This means the clock rates will no longer
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+ * match the clock names.
5653  */
5754 #define SUN8I_A33_PLL_AUDIO_REG	0x008
5855 
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-static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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-				   "osc24M", 0x008,
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-				   8, 7,		/* N */
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-				   0, 5,		/* M */
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-				   BIT(31),		/* gate */
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-				   BIT(28),		/* lock */
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-				   CLK_SET_RATE_UNGATE);
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+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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+	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
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+	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
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+};
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+
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+static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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+				       "osc24M", 0x008,
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+				       8, 7,	/* N */
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+				       0, 5,	/* M */
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+				       pll_audio_sdm_table, BIT(24),
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+				       0x284, BIT(31),
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+				       BIT(31),	/* gate */
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+				       BIT(28),	/* lock */
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+				       CLK_SET_RATE_UNGATE);
6670 
6771 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
6872 					"osc24M", 0x010,
....@@ -576,19 +580,29 @@
576580 	&ats_clk.common,
577581 };
578582 
579
-/* We hardcode the divider to 4 for now */
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-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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-			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
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-			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
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-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
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-			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
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-			"pll-periph", 1, 2, 0);
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-static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
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-			"pll-video", 1, 2, 0);
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+static const struct clk_hw *clk_parent_pll_audio[] = {
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+	&pll_audio_base_clk.common.hw
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+};
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+
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+/* We hardcode the divider to 1 for now */
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+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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+			    clk_parent_pll_audio,
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+			    2, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
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+			    clk_parent_pll_audio,
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+			    1, 2, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
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+			   &pll_periph_clk.common.hw,
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+			   1, 2, 0);
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+static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
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+			   &pll_video_clk.common.hw,
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+			   1, 2, 0);
592606 
593607 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
594608 	.hws	= {
....@@ -781,10 +795,10 @@
781795 		return;
782796 	}
783797 
784
-	/* Force the PLL-Audio-1x divider to 4 */
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+	/* Force the PLL-Audio-1x divider to 1 */
785799 	val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
786800 	val &= ~GENMASK(19, 16);
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-	writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
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+	writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
788802 
789803 	/* Force PLL-MIPI to MIPI mode */
790804 	val = readl(reg + SUN8I_A33_PLL_MIPI_REG);