~hc/RK356X_SDK_RELEASE.git

..	..	@@ -117,6 +117,17 @@
117	117	"core_bi_pll_test_se",
118	118	};
119	119
	120	+static struct clk_fixed_factor xo = {
	121	+ .mult = 1,
	122	+ .div = 1,
	123	+ .hw.init = &(struct clk_init_data){
	124	+ .name = "xo",
	125	+ .parent_names = (const char *[]){ "xo_board" },
	126	+ .num_parents = 1,
	127	+ .ops = &clk_fixed_factor_ops,
	128	+ },
	129	+};
	130	+
120	131	static struct pll_vco fabia_vco[] = {
121	132	{ 250000000, 2000000000, 0 },
122	133	{ 125000000, 1000000000, 1 },
..	..	@@ -1031,7 +1042,7 @@
1031	1042	.name = "sdcc2_apps_clk_src",
1032	1043	.parent_names = gcc_parent_names_4,
1033	1044	.num_parents = 4,
1034		- .ops = &clk_rcg2_ops,
	1045	+ .ops = &clk_rcg2_floor_ops,
1035	1046	},
1036	1047	};
1037	1048
..	..	@@ -1055,7 +1066,7 @@
1055	1066	.name = "sdcc4_apps_clk_src",
1056	1067	.parent_names = gcc_parent_names_1,
1057	1068	.num_parents = 3,
1058		- .ops = &clk_rcg2_ops,
	1069	+ .ops = &clk_rcg2_floor_ops,
1059	1070	},
1060	1071	};
1061	1072
..	..	@@ -1093,6 +1104,27 @@
1093	1104	.freq_tbl = ftbl_ufs_axi_clk_src,
1094	1105	.clkr.hw.init = &(struct clk_init_data){
1095	1106	.name = "ufs_axi_clk_src",
	1107	+ .parent_names = gcc_parent_names_0,
	1108	+ .num_parents = 4,
	1109	+ .ops = &clk_rcg2_ops,
	1110	+ },
	1111	+};
	1112	+
	1113	+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
	1114	+ F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
	1115	+ F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	1116	+ F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	1117	+ { }
	1118	+};
	1119	+
	1120	+static struct clk_rcg2 ufs_unipro_core_clk_src = {
	1121	+ .cmd_rcgr = 0x76028,
	1122	+ .mnd_width = 8,
	1123	+ .hid_width = 5,
	1124	+ .parent_map = gcc_parent_map_0,
	1125	+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
	1126	+ .clkr.hw.init = &(struct clk_init_data){
	1127	+ .name = "ufs_unipro_core_clk_src",
1096	1128	.parent_names = gcc_parent_names_0,
1097	1129	.num_parents = 4,
1098	1130	.ops = &clk_rcg2_ops,
..	..	@@ -1179,6 +1211,7 @@
1179	1211	"ufs_axi_clk_src",
1180	1212	},
1181	1213	.num_parents = 1,
	1214	+ .flags = CLK_SET_RATE_PARENT,
1182	1215	.ops = &clk_branch2_ops,
1183	1216	},
1184	1217	},
..	..	@@ -1196,6 +1229,7 @@
1196	1229	"usb30_master_clk_src",
1197	1230	},
1198	1231	.num_parents = 1,
	1232	+ .flags = CLK_SET_RATE_PARENT,
1199	1233	.ops = &clk_branch2_ops,
1200	1234	},
1201	1235	},
..	..	@@ -1253,6 +1287,72 @@
1253	1287	},
1254	1288	};
1255	1289
	1290	+static struct clk_branch gcc_mss_cfg_ahb_clk = {
	1291	+ .halt_reg = 0x8a000,
	1292	+ .halt_check = BRANCH_HALT,
	1293	+ .clkr = {
	1294	+ .enable_reg = 0x8a000,
	1295	+ .enable_mask = BIT(0),
	1296	+ .hw.init = &(struct clk_init_data){
	1297	+ .name = "gcc_mss_cfg_ahb_clk",
	1298	+ .ops = &clk_branch2_ops,
	1299	+ },
	1300	+ },
	1301	+};
	1302	+
	1303	+static struct clk_branch gcc_mss_snoc_axi_clk = {
	1304	+ .halt_reg = 0x8a03c,
	1305	+ .halt_check = BRANCH_HALT,
	1306	+ .clkr = {
	1307	+ .enable_reg = 0x8a03c,
	1308	+ .enable_mask = BIT(0),
	1309	+ .hw.init = &(struct clk_init_data){
	1310	+ .name = "gcc_mss_snoc_axi_clk",
	1311	+ .ops = &clk_branch2_ops,
	1312	+ },
	1313	+ },
	1314	+};
	1315	+
	1316	+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
	1317	+ .halt_reg = 0x8a004,
	1318	+ .halt_check = BRANCH_HALT,
	1319	+ .clkr = {
	1320	+ .enable_reg = 0x8a004,
	1321	+ .enable_mask = BIT(0),
	1322	+ .hw.init = &(struct clk_init_data){
	1323	+ .name = "gcc_mss_mnoc_bimc_axi_clk",
	1324	+ .ops = &clk_branch2_ops,
	1325	+ },
	1326	+ },
	1327	+};
	1328	+
	1329	+static struct clk_branch gcc_boot_rom_ahb_clk = {
	1330	+ .halt_reg = 0x38004,
	1331	+ .halt_check = BRANCH_HALT_VOTED,
	1332	+ .hwcg_reg = 0x38004,
	1333	+ .hwcg_bit = 1,
	1334	+ .clkr = {
	1335	+ .enable_reg = 0x52004,
	1336	+ .enable_mask = BIT(10),
	1337	+ .hw.init = &(struct clk_init_data){
	1338	+ .name = "gcc_boot_rom_ahb_clk",
	1339	+ .ops = &clk_branch2_ops,
	1340	+ },
	1341	+ },
	1342	+};
	1343	+
	1344	+static struct clk_branch gcc_mss_gpll0_div_clk_src = {
	1345	+ .halt_check = BRANCH_HALT_DELAY,
	1346	+ .clkr = {
	1347	+ .enable_reg = 0x5200c,
	1348	+ .enable_mask = BIT(2),
	1349	+ .hw.init = &(struct clk_init_data){
	1350	+ .name = "gcc_mss_gpll0_div_clk_src",
	1351	+ .ops = &clk_branch2_ops,
	1352	+ },
	1353	+ },
	1354	+};
	1355	+
1256	1356	static struct clk_branch gcc_blsp1_ahb_clk = {
1257	1357	.halt_reg = 0x17004,
1258	1358	.halt_check = BRANCH_HALT_VOTED,
..	..	@@ -1278,6 +1378,7 @@
1278	1378	"blsp1_qup1_i2c_apps_clk_src",
1279	1379	},
1280	1380	.num_parents = 1,
	1381	+ .flags = CLK_SET_RATE_PARENT,
1281	1382	.ops = &clk_branch2_ops,
1282	1383	},
1283	1384	},
..	..	@@ -1295,6 +1396,7 @@
1295	1396	"blsp1_qup1_spi_apps_clk_src",
1296	1397	},
1297	1398	.num_parents = 1,
	1399	+ .flags = CLK_SET_RATE_PARENT,
1298	1400	.ops = &clk_branch2_ops,
1299	1401	},
1300	1402	},
..	..	@@ -1312,6 +1414,7 @@
1312	1414	"blsp1_qup2_i2c_apps_clk_src",
1313	1415	},
1314	1416	.num_parents = 1,
	1417	+ .flags = CLK_SET_RATE_PARENT,
1315	1418	.ops = &clk_branch2_ops,
1316	1419	},
1317	1420	},
..	..	@@ -1329,6 +1432,7 @@
1329	1432	"blsp1_qup2_spi_apps_clk_src",
1330	1433	},
1331	1434	.num_parents = 1,
	1435	+ .flags = CLK_SET_RATE_PARENT,
1332	1436	.ops = &clk_branch2_ops,
1333	1437	},
1334	1438	},
..	..	@@ -1346,6 +1450,7 @@
1346	1450	"blsp1_qup3_i2c_apps_clk_src",
1347	1451	},
1348	1452	.num_parents = 1,
	1453	+ .flags = CLK_SET_RATE_PARENT,
1349	1454	.ops = &clk_branch2_ops,
1350	1455	},
1351	1456	},
..	..	@@ -1363,6 +1468,7 @@
1363	1468	"blsp1_qup3_spi_apps_clk_src",
1364	1469	},
1365	1470	.num_parents = 1,
	1471	+ .flags = CLK_SET_RATE_PARENT,
1366	1472	.ops = &clk_branch2_ops,
1367	1473	},
1368	1474	},
..	..	@@ -1380,6 +1486,7 @@
1380	1486	"blsp1_qup4_i2c_apps_clk_src",
1381	1487	},
1382	1488	.num_parents = 1,
	1489	+ .flags = CLK_SET_RATE_PARENT,
1383	1490	.ops = &clk_branch2_ops,
1384	1491	},
1385	1492	},
..	..	@@ -1397,6 +1504,7 @@
1397	1504	"blsp1_qup4_spi_apps_clk_src",
1398	1505	},
1399	1506	.num_parents = 1,
	1507	+ .flags = CLK_SET_RATE_PARENT,
1400	1508	.ops = &clk_branch2_ops,
1401	1509	},
1402	1510	},
..	..	@@ -1414,6 +1522,7 @@
1414	1522	"blsp1_qup5_i2c_apps_clk_src",
1415	1523	},
1416	1524	.num_parents = 1,
	1525	+ .flags = CLK_SET_RATE_PARENT,
1417	1526	.ops = &clk_branch2_ops,
1418	1527	},
1419	1528	},
..	..	@@ -1431,6 +1540,7 @@
1431	1540	"blsp1_qup5_spi_apps_clk_src",
1432	1541	},
1433	1542	.num_parents = 1,
	1543	+ .flags = CLK_SET_RATE_PARENT,
1434	1544	.ops = &clk_branch2_ops,
1435	1545	},
1436	1546	},
..	..	@@ -1448,6 +1558,7 @@
1448	1558	"blsp1_qup6_i2c_apps_clk_src",
1449	1559	},
1450	1560	.num_parents = 1,
	1561	+ .flags = CLK_SET_RATE_PARENT,
1451	1562	.ops = &clk_branch2_ops,
1452	1563	},
1453	1564	},
..	..	@@ -1465,6 +1576,7 @@
1465	1576	"blsp1_qup6_spi_apps_clk_src",
1466	1577	},
1467	1578	.num_parents = 1,
	1579	+ .flags = CLK_SET_RATE_PARENT,
1468	1580	.ops = &clk_branch2_ops,
1469	1581	},
1470	1582	},
..	..	@@ -1495,6 +1607,7 @@
1495	1607	"blsp1_uart1_apps_clk_src",
1496	1608	},
1497	1609	.num_parents = 1,
	1610	+ .flags = CLK_SET_RATE_PARENT,
1498	1611	.ops = &clk_branch2_ops,
1499	1612	},
1500	1613	},
..	..	@@ -1512,6 +1625,7 @@
1512	1625	"blsp1_uart2_apps_clk_src",
1513	1626	},
1514	1627	.num_parents = 1,
	1628	+ .flags = CLK_SET_RATE_PARENT,
1515	1629	.ops = &clk_branch2_ops,
1516	1630	},
1517	1631	},
..	..	@@ -1529,6 +1643,7 @@
1529	1643	"blsp1_uart3_apps_clk_src",
1530	1644	},
1531	1645	.num_parents = 1,
	1646	+ .flags = CLK_SET_RATE_PARENT,
1532	1647	.ops = &clk_branch2_ops,
1533	1648	},
1534	1649	},
..	..	@@ -1559,6 +1674,7 @@
1559	1674	"blsp2_qup1_i2c_apps_clk_src",
1560	1675	},
1561	1676	.num_parents = 1,
	1677	+ .flags = CLK_SET_RATE_PARENT,
1562	1678	.ops = &clk_branch2_ops,
1563	1679	},
1564	1680	},
..	..	@@ -1576,6 +1692,7 @@
1576	1692	"blsp2_qup1_spi_apps_clk_src",
1577	1693	},
1578	1694	.num_parents = 1,
	1695	+ .flags = CLK_SET_RATE_PARENT,
1579	1696	.ops = &clk_branch2_ops,
1580	1697	},
1581	1698	},
..	..	@@ -1593,6 +1710,7 @@
1593	1710	"blsp2_qup2_i2c_apps_clk_src",
1594	1711	},
1595	1712	.num_parents = 1,
	1713	+ .flags = CLK_SET_RATE_PARENT,
1596	1714	.ops = &clk_branch2_ops,
1597	1715	},
1598	1716	},
..	..	@@ -1610,6 +1728,7 @@
1610	1728	"blsp2_qup2_spi_apps_clk_src",
1611	1729	},
1612	1730	.num_parents = 1,
	1731	+ .flags = CLK_SET_RATE_PARENT,
1613	1732	.ops = &clk_branch2_ops,
1614	1733	},
1615	1734	},
..	..	@@ -1627,6 +1746,7 @@
1627	1746	"blsp2_qup3_i2c_apps_clk_src",
1628	1747	},
1629	1748	.num_parents = 1,
	1749	+ .flags = CLK_SET_RATE_PARENT,
1630	1750	.ops = &clk_branch2_ops,
1631	1751	},
1632	1752	},
..	..	@@ -1644,6 +1764,7 @@
1644	1764	"blsp2_qup3_spi_apps_clk_src",
1645	1765	},
1646	1766	.num_parents = 1,
	1767	+ .flags = CLK_SET_RATE_PARENT,
1647	1768	.ops = &clk_branch2_ops,
1648	1769	},
1649	1770	},
..	..	@@ -1661,6 +1782,7 @@
1661	1782	"blsp2_qup4_i2c_apps_clk_src",
1662	1783	},
1663	1784	.num_parents = 1,
	1785	+ .flags = CLK_SET_RATE_PARENT,
1664	1786	.ops = &clk_branch2_ops,
1665	1787	},
1666	1788	},
..	..	@@ -1678,6 +1800,7 @@
1678	1800	"blsp2_qup4_spi_apps_clk_src",
1679	1801	},
1680	1802	.num_parents = 1,
	1803	+ .flags = CLK_SET_RATE_PARENT,
1681	1804	.ops = &clk_branch2_ops,
1682	1805	},
1683	1806	},
..	..	@@ -1695,6 +1818,7 @@
1695	1818	"blsp2_qup5_i2c_apps_clk_src",
1696	1819	},
1697	1820	.num_parents = 1,
	1821	+ .flags = CLK_SET_RATE_PARENT,
1698	1822	.ops = &clk_branch2_ops,
1699	1823	},
1700	1824	},
..	..	@@ -1712,6 +1836,7 @@
1712	1836	"blsp2_qup5_spi_apps_clk_src",
1713	1837	},
1714	1838	.num_parents = 1,
	1839	+ .flags = CLK_SET_RATE_PARENT,
1715	1840	.ops = &clk_branch2_ops,
1716	1841	},
1717	1842	},
..	..	@@ -1729,6 +1854,7 @@
1729	1854	"blsp2_qup6_i2c_apps_clk_src",
1730	1855	},
1731	1856	.num_parents = 1,
	1857	+ .flags = CLK_SET_RATE_PARENT,
1732	1858	.ops = &clk_branch2_ops,
1733	1859	},
1734	1860	},
..	..	@@ -1746,6 +1872,7 @@
1746	1872	"blsp2_qup6_spi_apps_clk_src",
1747	1873	},
1748	1874	.num_parents = 1,
	1875	+ .flags = CLK_SET_RATE_PARENT,
1749	1876	.ops = &clk_branch2_ops,
1750	1877	},
1751	1878	},
..	..	@@ -1776,6 +1903,7 @@
1776	1903	"blsp2_uart1_apps_clk_src",
1777	1904	},
1778	1905	.num_parents = 1,
	1906	+ .flags = CLK_SET_RATE_PARENT,
1779	1907	.ops = &clk_branch2_ops,
1780	1908	},
1781	1909	},
..	..	@@ -1793,6 +1921,7 @@
1793	1921	"blsp2_uart2_apps_clk_src",
1794	1922	},
1795	1923	.num_parents = 1,
	1924	+ .flags = CLK_SET_RATE_PARENT,
1796	1925	.ops = &clk_branch2_ops,
1797	1926	},
1798	1927	},
..	..	@@ -1810,6 +1939,7 @@
1810	1939	"blsp2_uart3_apps_clk_src",
1811	1940	},
1812	1941	.num_parents = 1,
	1942	+ .flags = CLK_SET_RATE_PARENT,
1813	1943	.ops = &clk_branch2_ops,
1814	1944	},
1815	1945	},
..	..	@@ -1827,6 +1957,7 @@
1827	1957	"usb30_master_clk_src",
1828	1958	},
1829	1959	.num_parents = 1,
	1960	+ .flags = CLK_SET_RATE_PARENT,
1830	1961	.ops = &clk_branch2_ops,
1831	1962	},
1832	1963	},
..	..	@@ -1844,6 +1975,7 @@
1844	1975	"gp1_clk_src",
1845	1976	},
1846	1977	.num_parents = 1,
	1978	+ .flags = CLK_SET_RATE_PARENT,
1847	1979	.ops = &clk_branch2_ops,
1848	1980	},
1849	1981	},
..	..	@@ -1861,6 +1993,7 @@
1861	1993	"gp2_clk_src",
1862	1994	},
1863	1995	.num_parents = 1,
	1996	+ .flags = CLK_SET_RATE_PARENT,
1864	1997	.ops = &clk_branch2_ops,
1865	1998	},
1866	1999	},
..	..	@@ -1878,6 +2011,20 @@
1878	2011	"gp3_clk_src",
1879	2012	},
1880	2013	.num_parents = 1,
	2014	+ .flags = CLK_SET_RATE_PARENT,
	2015	+ .ops = &clk_branch2_ops,
	2016	+ },
	2017	+ },
	2018	+};
	2019	+
	2020	+static struct clk_branch gcc_bimc_gfx_clk = {
	2021	+ .halt_reg = 0x46040,
	2022	+ .halt_check = BRANCH_HALT,
	2023	+ .clkr = {
	2024	+ .enable_reg = 0x46040,
	2025	+ .enable_mask = BIT(0),
	2026	+ .hw.init = &(struct clk_init_data){
	2027	+ .name = "gcc_bimc_gfx_clk",
1881	2028	.ops = &clk_branch2_ops,
1882	2029	},
1883	2030	},
..	..	@@ -1947,6 +2094,7 @@
1947	2094	"hmss_ahb_clk_src",
1948	2095	},
1949	2096	.num_parents = 1,
	2097	+ .flags = CLK_SET_RATE_PARENT,
1950	2098	.ops = &clk_branch2_ops,
1951	2099	},
1952	2100	},
..	..	@@ -1965,19 +2113,6 @@
1965	2113	},
1966	2114	};
1967	2115
1968		-static struct clk_branch gcc_hmss_dvm_bus_clk = {
1969		- .halt_reg = 0x4808c,
1970		- .halt_check = BRANCH_HALT,
1971		- .clkr = {
1972		- .enable_reg = 0x4808c,
1973		- .enable_mask = BIT(0),
1974		- .hw.init = &(struct clk_init_data){
1975		- .name = "gcc_hmss_dvm_bus_clk",
1976		- .ops = &clk_branch2_ops,
1977		- },
1978		- },
1979		-};
1980		-
1981	2116	static struct clk_branch gcc_hmss_rbcpr_clk = {
1982	2117	.halt_reg = 0x48008,
1983	2118	.halt_check = BRANCH_HALT,
..	..	@@ -1990,6 +2125,7 @@
1990	2125	"hmss_rbcpr_clk_src",
1991	2126	},
1992	2127	.num_parents = 1,
	2128	+ .flags = CLK_SET_RATE_PARENT,
1993	2129	.ops = &clk_branch2_ops,
1994	2130	},
1995	2131	},
..	..	@@ -2008,32 +2144,6 @@
2008	2144	},
2009	2145	};
2010	2146
2011		-static struct clk_branch gcc_lpass_at_clk = {
2012		- .halt_reg = 0x47020,
2013		- .halt_check = BRANCH_HALT,
2014		- .clkr = {
2015		- .enable_reg = 0x47020,
2016		- .enable_mask = BIT(0),
2017		- .hw.init = &(struct clk_init_data){
2018		- .name = "gcc_lpass_at_clk",
2019		- .ops = &clk_branch2_ops,
2020		- },
2021		- },
2022		-};
2023		-
2024		-static struct clk_branch gcc_lpass_trig_clk = {
2025		- .halt_reg = 0x4701c,
2026		- .halt_check = BRANCH_HALT,
2027		- .clkr = {
2028		- .enable_reg = 0x4701c,
2029		- .enable_mask = BIT(0),
2030		- .hw.init = &(struct clk_init_data){
2031		- .name = "gcc_lpass_trig_clk",
2032		- .ops = &clk_branch2_ops,
2033		- },
2034		- },
2035		-};
2036		-
2037	2147	static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2038	2148	.halt_reg = 0x9004,
2039	2149	.halt_check = BRANCH_HALT,
..	..	@@ -2043,6 +2153,12 @@
2043	2153	.hw.init = &(struct clk_init_data){
2044	2154	.name = "gcc_mmss_noc_cfg_ahb_clk",
2045	2155	.ops = &clk_branch2_ops,
	2156	+ /*
	2157	+ * Any access to mmss depends on this clock.
	2158	+ * Gating this clock has been shown to crash the system
	2159	+ * when mmssnoc_axi_rpm_clk is inited in rpmcc.
	2160	+ */
	2161	+ .flags = CLK_IS_CRITICAL,
2046	2162	},
2047	2163	},
2048	2164	};
..	..	@@ -2111,6 +2227,7 @@
2111	2227	"pcie_aux_clk_src",
2112	2228	},
2113	2229	.num_parents = 1,
	2230	+ .flags = CLK_SET_RATE_PARENT,
2114	2231	.ops = &clk_branch2_ops,
2115	2232	},
2116	2233	},
..	..	@@ -2180,6 +2297,7 @@
2180	2297	"pcie_aux_clk_src",
2181	2298	},
2182	2299	.num_parents = 1,
	2300	+ .flags = CLK_SET_RATE_PARENT,
2183	2301	.ops = &clk_branch2_ops,
2184	2302	},
2185	2303	},
..	..	@@ -2197,6 +2315,7 @@
2197	2315	"pdm2_clk_src",
2198	2316	},
2199	2317	.num_parents = 1,
	2318	+ .flags = CLK_SET_RATE_PARENT,
2200	2319	.ops = &clk_branch2_ops,
2201	2320	},
2202	2321	},
..	..	@@ -2266,6 +2385,7 @@
2266	2385	"sdcc2_apps_clk_src",
2267	2386	},
2268	2387	.num_parents = 1,
	2388	+ .flags = CLK_SET_RATE_PARENT,
2269	2389	.ops = &clk_branch2_ops,
2270	2390	},
2271	2391	},
..	..	@@ -2296,6 +2416,7 @@
2296	2416	"sdcc4_apps_clk_src",
2297	2417	},
2298	2418	.num_parents = 1,
	2419	+ .flags = CLK_SET_RATE_PARENT,
2299	2420	.ops = &clk_branch2_ops,
2300	2421	},
2301	2422	},
..	..	@@ -2339,6 +2460,7 @@
2339	2460	"tsif_ref_clk_src",
2340	2461	},
2341	2462	.num_parents = 1,
	2463	+ .flags = CLK_SET_RATE_PARENT,
2342	2464	.ops = &clk_branch2_ops,
2343	2465	},
2344	2466	},
..	..	@@ -2369,6 +2491,7 @@
2369	2491	"ufs_axi_clk_src",
2370	2492	},
2371	2493	.num_parents = 1,
	2494	+ .flags = CLK_SET_RATE_PARENT,
2372	2495	.ops = &clk_branch2_ops,
2373	2496	},
2374	2497	},
..	..	@@ -2447,6 +2570,11 @@
2447	2570	.enable_mask = BIT(0),
2448	2571	.hw.init = &(struct clk_init_data){
2449	2572	.name = "gcc_ufs_unipro_core_clk",
	2573	+ .parent_names = (const char *[]){
	2574	+ "ufs_unipro_core_clk_src",
	2575	+ },
	2576	+ .num_parents = 1,
	2577	+ .flags = CLK_SET_RATE_PARENT,
2450	2578	.ops = &clk_branch2_ops,
2451	2579	},
2452	2580	},
..	..	@@ -2464,6 +2592,7 @@
2464	2592	"usb30_master_clk_src",
2465	2593	},
2466	2594	.num_parents = 1,
	2595	+ .flags = CLK_SET_RATE_PARENT,
2467	2596	.ops = &clk_branch2_ops,
2468	2597	},
2469	2598	},
..	..	@@ -2481,6 +2610,7 @@
2481	2610	"usb30_mock_utmi_clk_src",
2482	2611	},
2483	2612	.num_parents = 1,
	2613	+ .flags = CLK_SET_RATE_PARENT,
2484	2614	.ops = &clk_branch2_ops,
2485	2615	},
2486	2616	},
..	..	@@ -2511,6 +2641,7 @@
2511	2641	"usb3_phy_aux_clk_src",
2512	2642	},
2513	2643	.num_parents = 1,
	2644	+ .flags = CLK_SET_RATE_PARENT,
2514	2645	.ops = &clk_branch2_ops,
2515	2646	},
2516	2647	},
..	..	@@ -2518,7 +2649,7 @@
2518	2649
2519	2650	static struct clk_branch gcc_usb3_phy_pipe_clk = {
2520	2651	.halt_reg = 0x50004,
2521		- .halt_check = BRANCH_HALT,
	2652	+ .halt_check = BRANCH_HALT_SKIP,
2522	2653	.clkr = {
2523	2654	.enable_reg = 0x50004,
2524	2655	.enable_mask = BIT(0),
..	..	@@ -2537,6 +2668,76 @@
2537	2668	.enable_mask = BIT(0),
2538	2669	.hw.init = &(struct clk_init_data){
2539	2670	.name = "gcc_usb_phy_cfg_ahb2phy_clk",
	2671	+ .ops = &clk_branch2_ops,
	2672	+ },
	2673	+ },
	2674	+};
	2675	+
	2676	+static struct clk_branch gcc_hdmi_clkref_clk = {
	2677	+ .halt_reg = 0x88000,
	2678	+ .clkr = {
	2679	+ .enable_reg = 0x88000,
	2680	+ .enable_mask = BIT(0),
	2681	+ .hw.init = &(struct clk_init_data){
	2682	+ .name = "gcc_hdmi_clkref_clk",
	2683	+ .parent_names = (const char *[]){ "xo" },
	2684	+ .num_parents = 1,
	2685	+ .ops = &clk_branch2_ops,
	2686	+ },
	2687	+ },
	2688	+};
	2689	+
	2690	+static struct clk_branch gcc_ufs_clkref_clk = {
	2691	+ .halt_reg = 0x88004,
	2692	+ .clkr = {
	2693	+ .enable_reg = 0x88004,
	2694	+ .enable_mask = BIT(0),
	2695	+ .hw.init = &(struct clk_init_data){
	2696	+ .name = "gcc_ufs_clkref_clk",
	2697	+ .parent_names = (const char *[]){ "xo" },
	2698	+ .num_parents = 1,
	2699	+ .ops = &clk_branch2_ops,
	2700	+ },
	2701	+ },
	2702	+};
	2703	+
	2704	+static struct clk_branch gcc_usb3_clkref_clk = {
	2705	+ .halt_reg = 0x88008,
	2706	+ .clkr = {
	2707	+ .enable_reg = 0x88008,
	2708	+ .enable_mask = BIT(0),
	2709	+ .hw.init = &(struct clk_init_data){
	2710	+ .name = "gcc_usb3_clkref_clk",
	2711	+ .parent_names = (const char *[]){ "xo" },
	2712	+ .num_parents = 1,
	2713	+ .ops = &clk_branch2_ops,
	2714	+ },
	2715	+ },
	2716	+};
	2717	+
	2718	+static struct clk_branch gcc_pcie_clkref_clk = {
	2719	+ .halt_reg = 0x8800c,
	2720	+ .clkr = {
	2721	+ .enable_reg = 0x8800c,
	2722	+ .enable_mask = BIT(0),
	2723	+ .hw.init = &(struct clk_init_data){
	2724	+ .name = "gcc_pcie_clkref_clk",
	2725	+ .parent_names = (const char *[]){ "xo" },
	2726	+ .num_parents = 1,
	2727	+ .ops = &clk_branch2_ops,
	2728	+ },
	2729	+ },
	2730	+};
	2731	+
	2732	+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
	2733	+ .halt_reg = 0x88014,
	2734	+ .clkr = {
	2735	+ .enable_reg = 0x88014,
	2736	+ .enable_mask = BIT(0),
	2737	+ .hw.init = &(struct clk_init_data){
	2738	+ .name = "gcc_rx1_usb2_clkref_clk",
	2739	+ .parent_names = (const char *[]){ "xo" },
	2740	+ .num_parents = 1,
2540	2741	.ops = &clk_branch2_ops,
2541	2742	},
2542	2743	},
..	..	@@ -2648,17 +2849,15 @@
2648	2849	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2649	2850	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2650	2851	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
	2852	+ [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2651	2853	[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2652	2854	[GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2653	2855	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2654	2856	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2655	2857	[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2656	2858	[GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2657		- [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2658	2859	[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2659	2860	[GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2660		- [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
2661		- [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
2662	2861	[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2663	2862	[GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2664	2863	[GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
..	..	@@ -2731,9 +2930,20 @@
2731	2930	[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2732	2931	[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2733	2932	[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
	2933	+ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
2734	2934	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2735	2935	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2736	2936	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
	2937	+ [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
	2938	+ [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
	2939	+ [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
	2940	+ [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
	2941	+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
	2942	+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
	2943	+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
	2944	+ [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
	2945	+ [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
	2946	+ [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2737	2947	};
2738	2948
2739	2949	static struct gdsc *gcc_msm8998_gdscs[] = {
..	..	@@ -2762,6 +2972,96 @@
2762	2972	[GCC_TSIF_BCR] = { 0x36000 },
2763	2973	[GCC_UFS_BCR] = { 0x75000 },
2764	2974	[GCC_USB_30_BCR] = { 0xf000 },
	2975	+ [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
	2976	+ [GCC_CONFIG_NOC_BCR] = { 0x5000 },
	2977	+ [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
	2978	+ [GCC_IMEM_BCR] = { 0x8000 },
	2979	+ [GCC_PIMEM_BCR] = { 0xa000 },
	2980	+ [GCC_MMSS_BCR] = { 0xb000 },
	2981	+ [GCC_QDSS_BCR] = { 0xc000 },
	2982	+ [GCC_WCSS_BCR] = { 0x11000 },
	2983	+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
	2984	+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
	2985	+ [GCC_BLSP1_BCR] = { 0x17000 },
	2986	+ [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
	2987	+ [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
	2988	+ [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
	2989	+ [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
	2990	+ [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
	2991	+ [GCC_BLSP2_BCR] = { 0x25000 },
	2992	+ [GCC_BLSP2_UART1_BCR] = { 0x27000 },
	2993	+ [GCC_BLSP2_UART2_BCR] = { 0x29000 },
	2994	+ [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
	2995	+ [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
	2996	+ [GCC_PRNG_BCR] = { 0x34000 },
	2997	+ [GCC_TSIF_0_RESET] = { 0x36024 },
	2998	+ [GCC_TSIF_1_RESET] = { 0x36028 },
	2999	+ [GCC_TCSR_BCR] = { 0x37000 },
	3000	+ [GCC_BOOT_ROM_BCR] = { 0x38000 },
	3001	+ [GCC_MSG_RAM_BCR] = { 0x39000 },
	3002	+ [GCC_TLMM_BCR] = { 0x3a000 },
	3003	+ [GCC_MPM_BCR] = { 0x3b000 },
	3004	+ [GCC_SEC_CTRL_BCR] = { 0x3d000 },
	3005	+ [GCC_SPMI_BCR] = { 0x3f000 },
	3006	+ [GCC_SPDM_BCR] = { 0x40000 },
	3007	+ [GCC_CE1_BCR] = { 0x41000 },
	3008	+ [GCC_BIMC_BCR] = { 0x44000 },
	3009	+ [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
	3010	+ [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
	3011	+ [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
	3012	+ [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
	3013	+ [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
	3014	+ [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
	3015	+ [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
	3016	+ [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
	3017	+ [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
	3018	+ [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
	3019	+ [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
	3020	+ [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
	3021	+ [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
	3022	+ [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
	3023	+ [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
	3024	+ [GCC_APB2JTAG_BCR] = { 0x4c000 },
	3025	+ [GCC_RBCPR_CX_BCR] = { 0x4e000 },
	3026	+ [GCC_RBCPR_MX_BCR] = { 0x4f000 },
	3027	+ [GCC_USB3_PHY_BCR] = { 0x50020 },
	3028	+ [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
	3029	+ [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
	3030	+ [GCC_SSC_BCR] = { 0x63000 },
	3031	+ [GCC_SSC_RESET] = { 0x63020 },
	3032	+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
	3033	+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
	3034	+ [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
	3035	+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
	3036	+ [GCC_PCIE_PHY_BCR] = { 0x6f000 },
	3037	+ [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
	3038	+ [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
	3039	+ [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
	3040	+ [GCC_GPU_BCR] = { 0x71000 },
	3041	+ [GCC_SPSS_BCR] = { 0x72000 },
	3042	+ [GCC_OBT_ODT_BCR] = { 0x73000 },
	3043	+ [GCC_MSS_RESTART] = { 0x79000 },
	3044	+ [GCC_VS_BCR] = { 0x7a000 },
	3045	+ [GCC_MSS_VS_RESET] = { 0x7a100 },
	3046	+ [GCC_GPU_VS_RESET] = { 0x7a104 },
	3047	+ [GCC_APC0_VS_RESET] = { 0x7a108 },
	3048	+ [GCC_APC1_VS_RESET] = { 0x7a10c },
	3049	+ [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
	3050	+ [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
	3051	+ [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
	3052	+ [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
	3053	+ [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
	3054	+ [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
	3055	+ [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
	3056	+ [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
	3057	+ [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
	3058	+ [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
	3059	+ [GCC_DCC_BCR] = { 0x84000 },
	3060	+ [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
	3061	+ [GCC_IPA_BCR] = { 0x89000 },
	3062	+ [GCC_GLM_BCR] = { 0x8b000 },
	3063	+ [GCC_SKL_BCR] = { 0x8c000 },
	3064	+ [GCC_MSMPU_BCR] = { 0x8d000 },
2765	3065	};
2766	3066
2767	3067	static const struct regmap_config gcc_msm8998_regmap_config = {
..	..	@@ -2772,6 +3072,10 @@
2772	3072	.fast_io = true,
2773	3073	};
2774	3074
	3075	+static struct clk_hw *gcc_msm8998_hws[] = {
	3076	+ &xo.hw,
	3077	+};
	3078	+
2775	3079	static const struct qcom_cc_desc gcc_msm8998_desc = {
2776	3080	.config = &gcc_msm8998_regmap_config,
2777	3081	.clks = gcc_msm8998_clocks,
..	..	@@ -2780,6 +3084,8 @@
2780	3084	.num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2781	3085	.gdscs = gcc_msm8998_gdscs,
2782	3086	.num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
	3087	+ .clk_hws = gcc_msm8998_hws,
	3088	+ .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
2783	3089	};
2784	3090
2785	3091	static int gcc_msm8998_probe(struct platform_device *pdev)
..	..	@@ -2813,6 +3119,7 @@
2813	3119	.driver = {
2814	3120	.name = "gcc-msm8998",
2815	3121	.of_match_table = gcc_msm8998_match_table,
	3122	+ .sync_state = clk_sync_state,
2816	3123	},
2817	3124	};
2818	3125