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| 3 | 3 | #define __MACH_MMP_CLK_H |
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| 4 | 4 | |
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| 5 | 5 | #include <linux/clk-provider.h> |
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| 6 | +#include <linux/pm_domain.h> |
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| 6 | 7 | #include <linux/clkdev.h> |
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| 7 | 8 | |
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| 8 | 9 | #define APBC_NO_BUS_CTRL BIT(0) |
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| .. | .. |
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| 16 | 17 | unsigned int den_mask; |
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| 17 | 18 | unsigned int num_shift; |
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| 18 | 19 | unsigned int den_shift; |
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| 20 | + unsigned int enable_mask; |
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| 19 | 21 | }; |
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| 20 | 22 | |
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| 21 | 23 | struct mmp_clk_factor_tbl { |
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| .. | .. |
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| 97 | 99 | extern const struct clk_ops mmp_clk_mix_ops; |
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| 98 | 100 | extern struct clk *mmp_clk_register_mix(struct device *dev, |
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| 99 | 101 | const char *name, |
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| 100 | | - const char **parent_names, |
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| 102 | + const char * const *parent_names, |
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| 101 | 103 | u8 num_parents, |
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| 102 | 104 | unsigned long flags, |
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| 103 | 105 | struct mmp_clk_mix_config *config, |
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| .. | .. |
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| 124 | 126 | u32 val_disable, unsigned int gate_flags, |
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| 125 | 127 | spinlock_t *lock); |
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| 126 | 128 | |
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| 127 | | - |
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| 128 | | -extern struct clk *mmp_clk_register_pll2(const char *name, |
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| 129 | | - const char *parent_name, unsigned long flags); |
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| 130 | 129 | extern struct clk *mmp_clk_register_apbc(const char *name, |
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| 131 | 130 | const char *parent_name, void __iomem *base, |
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| 132 | 131 | unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); |
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| .. | .. |
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| 196 | 195 | struct mmp_param_mux_clk { |
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| 197 | 196 | unsigned int id; |
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| 198 | 197 | char *name; |
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| 199 | | - const char **parent_name; |
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| 198 | + const char * const *parent_name; |
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| 200 | 199 | u8 num_parents; |
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| 201 | 200 | unsigned long flags; |
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| 202 | 201 | unsigned long offset; |
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| .. | .. |
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| 224 | 223 | struct mmp_param_div_clk *clks, |
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| 225 | 224 | void __iomem *base, int size); |
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| 226 | 225 | |
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| 226 | +struct mmp_param_pll_clk { |
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| 227 | + unsigned int id; |
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| 228 | + char *name; |
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| 229 | + unsigned long default_rate; |
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| 230 | + unsigned long enable_offset; |
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| 231 | + u32 enable; |
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| 232 | + unsigned long offset; |
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| 233 | + u8 shift; |
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| 234 | + /* MMP3 specific: */ |
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| 235 | + unsigned long input_rate; |
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| 236 | + unsigned long postdiv_offset; |
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| 237 | + unsigned long postdiv_shift; |
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| 238 | +}; |
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| 239 | +void mmp_register_pll_clks(struct mmp_clk_unit *unit, |
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| 240 | + struct mmp_param_pll_clk *clks, |
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| 241 | + void __iomem *base, int size); |
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| 242 | + |
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| 227 | 243 | #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \ |
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| 228 | 244 | { \ |
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| 229 | 245 | .width_div = (w_d), \ |
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| .. | .. |
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| 237 | 253 | int nr_clks); |
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| 238 | 254 | void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, |
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| 239 | 255 | struct clk *clk); |
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| 256 | + |
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| 257 | +/* Power islands */ |
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| 258 | +#define MMP_PM_DOMAIN_NO_DISABLE BIT(0) |
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| 259 | + |
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| 260 | +struct generic_pm_domain *mmp_pm_domain_register(const char *name, |
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| 261 | + void __iomem *reg, |
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| 262 | + u32 power_on, u32 reset, u32 clock_enable, |
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| 263 | + unsigned int flags, spinlock_t *lock); |
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| 264 | + |
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| 240 | 265 | #endif |
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