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2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/drivers/clk/meson/meson8b.h
....@@ -17,22 +17,40 @@
1717  * blocks below. Those offsets must be multiplied by 4 before adding them to
1818  * the base address to get the right value
1919  *
20
- * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
20
+ * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
2121  */
22
+#define HHI_GP_PLL_CNTL			0x40  /* 0x10 offset in data sheet */
23
+#define HHI_GP_PLL_CNTL2		0x44  /* 0x11 offset in data sheet */
24
+#define HHI_GP_PLL_CNTL3		0x48  /* 0x12 offset in data sheet */
25
+#define HHI_GP_PLL_CNTL4		0x4C  /* 0x13 offset in data sheet */
26
+#define HHI_GP_PLL_CNTL5		0x50  /* 0x14 offset in data sheet */
27
+#define HHI_VIID_CLK_DIV		0x128 /* 0x4a offset in data sheet */
28
+#define HHI_VIID_CLK_CNTL		0x12c /* 0x4b offset in data sheet */
2229 #define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
2330 #define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
2431 #define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
2532 #define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
2633 #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
2734 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
35
+#define HHI_VID_CLK_DIV			0x164 /* 0x59 offset in data sheet */
2836 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
37
+#define HHI_AUD_CLK_CNTL		0x178 /* 0x5e offset in data sheet */
2938 #define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
39
+#define HHI_AUD_CLK_CNTL2		0x190 /* 0x64 offset in data sheet */
40
+#define HHI_VID_CLK_CNTL2		0x194 /* 0x65 offset in data sheet */
3041 #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
3142 #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
43
+#define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */
44
+#define HHI_VPU_CLK_CNTL		0x1bc /* 0x6f offset in data sheet */
45
+#define HHI_HDMI_CLK_CNTL		0x1cc /* 0x73 offset in data sheet */
46
+#define HHI_VDEC_CLK_CNTL		0x1e0 /* 0x78 offset in data sheet */
47
+#define HHI_VDEC2_CLK_CNTL		0x1e4 /* 0x79 offset in data sheet */
48
+#define HHI_VDEC3_CLK_CNTL		0x1e8 /* 0x7a offset in data sheet */
3249 #define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
3350 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
3451 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
3552 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
53
+#define HHI_VID_PLL_CNTL2		0x324 /* 0xc9 offset in data sheet */
3654 
3755 /*
3856  * MPLL register offeset taken from the S905 datasheet. Vendor kernel source
....@@ -63,8 +81,8 @@
6381 #define CLKID_MPLL1_DIV		97
6482 #define CLKID_MPLL2_DIV		98
6583 #define CLKID_CPU_IN_SEL	99
66
-#define CLKID_CPU_DIV2		100
67
-#define CLKID_CPU_DIV3		101
84
+#define CLKID_CPU_IN_DIV2	100
85
+#define CLKID_CPU_IN_DIV3	101
6886 #define CLKID_CPU_SCALE_DIV	102
6987 #define CLKID_CPU_SCALE_OUT_SEL	103
7088 #define CLKID_MPLL_PREDIV	104
....@@ -75,8 +93,97 @@
7593 #define CLKID_FCLK_DIV7_DIV	109
7694 #define CLKID_NAND_SEL		110
7795 #define CLKID_NAND_DIV		111
96
+#define CLKID_PLL_FIXED_DCO	113
97
+#define CLKID_HDMI_PLL_DCO	114
98
+#define CLKID_PLL_SYS_DCO	115
99
+#define CLKID_CPU_CLK_DIV2	116
100
+#define CLKID_CPU_CLK_DIV3	117
101
+#define CLKID_CPU_CLK_DIV4	118
102
+#define CLKID_CPU_CLK_DIV5	119
103
+#define CLKID_CPU_CLK_DIV6	120
104
+#define CLKID_CPU_CLK_DIV7	121
105
+#define CLKID_CPU_CLK_DIV8	122
106
+#define CLKID_APB_SEL		123
107
+#define CLKID_PERIPH_SEL	125
108
+#define CLKID_AXI_SEL		127
109
+#define CLKID_L2_DRAM_SEL	129
110
+#define CLKID_HDMI_PLL_LVDS_OUT	131
111
+#define CLKID_HDMI_PLL_HDMI_OUT	132
112
+#define CLKID_VID_PLL_IN_SEL	133
113
+#define CLKID_VID_PLL_IN_EN	134
114
+#define CLKID_VID_PLL_PRE_DIV	135
115
+#define CLKID_VID_PLL_POST_DIV	136
116
+#define CLKID_VID_PLL_FINAL_DIV	137
117
+#define CLKID_VCLK_IN_SEL	138
118
+#define CLKID_VCLK_IN_EN	139
119
+#define CLKID_VCLK_DIV1		140
120
+#define CLKID_VCLK_DIV2_DIV	141
121
+#define CLKID_VCLK_DIV2		142
122
+#define CLKID_VCLK_DIV4_DIV	143
123
+#define CLKID_VCLK_DIV4		144
124
+#define CLKID_VCLK_DIV6_DIV	145
125
+#define CLKID_VCLK_DIV6		146
126
+#define CLKID_VCLK_DIV12_DIV	147
127
+#define CLKID_VCLK_DIV12	148
128
+#define CLKID_VCLK2_IN_SEL	149
129
+#define CLKID_VCLK2_IN_EN	150
130
+#define CLKID_VCLK2_DIV1	151
131
+#define CLKID_VCLK2_DIV2_DIV	152
132
+#define CLKID_VCLK2_DIV2	153
133
+#define CLKID_VCLK2_DIV4_DIV	154
134
+#define CLKID_VCLK2_DIV4	155
135
+#define CLKID_VCLK2_DIV6_DIV	156
136
+#define CLKID_VCLK2_DIV6	157
137
+#define CLKID_VCLK2_DIV12_DIV	158
138
+#define CLKID_VCLK2_DIV12	159
139
+#define CLKID_CTS_ENCT_SEL	160
140
+#define CLKID_CTS_ENCT		161
141
+#define CLKID_CTS_ENCP_SEL	162
142
+#define CLKID_CTS_ENCP		163
143
+#define CLKID_CTS_ENCI_SEL	164
144
+#define CLKID_CTS_ENCI		165
145
+#define CLKID_HDMI_TX_PIXEL_SEL	166
146
+#define CLKID_HDMI_TX_PIXEL	167
147
+#define CLKID_CTS_ENCL_SEL	168
148
+#define CLKID_CTS_ENCL		169
149
+#define CLKID_CTS_VDAC0_SEL	170
150
+#define CLKID_CTS_VDAC0		171
151
+#define CLKID_HDMI_SYS_SEL	172
152
+#define CLKID_HDMI_SYS_DIV	173
153
+#define CLKID_MALI_0_SEL	175
154
+#define CLKID_MALI_0_DIV	176
155
+#define CLKID_MALI_0		177
156
+#define CLKID_MALI_1_SEL	178
157
+#define CLKID_MALI_1_DIV	179
158
+#define CLKID_MALI_1		180
159
+#define CLKID_GP_PLL_DCO	181
160
+#define CLKID_GP_PLL		182
161
+#define CLKID_VPU_0_SEL		183
162
+#define CLKID_VPU_0_DIV		184
163
+#define CLKID_VPU_0		185
164
+#define CLKID_VPU_1_SEL		186
165
+#define CLKID_VPU_1_DIV		187
166
+#define CLKID_VPU_1		189
167
+#define CLKID_VDEC_1_SEL	191
168
+#define CLKID_VDEC_1_1_DIV	192
169
+#define CLKID_VDEC_1_1		193
170
+#define CLKID_VDEC_1_2_DIV	194
171
+#define CLKID_VDEC_1_2		195
172
+#define CLKID_VDEC_HCODEC_SEL	197
173
+#define CLKID_VDEC_HCODEC_DIV	198
174
+#define CLKID_VDEC_2_SEL	200
175
+#define CLKID_VDEC_2_DIV	201
176
+#define CLKID_VDEC_HEVC_SEL	203
177
+#define CLKID_VDEC_HEVC_DIV	204
178
+#define CLKID_VDEC_HEVC_EN	205
179
+#define CLKID_CTS_AMCLK_SEL	207
180
+#define CLKID_CTS_AMCLK_DIV	208
181
+#define CLKID_CTS_MCLK_I958_SEL	210
182
+#define CLKID_CTS_MCLK_I958_DIV	211
183
+#define CLKID_VCLK_EN		214
184
+#define CLKID_VCLK2_EN		215
78185 
79
-#define CLK_NR_CLKS		113
186
+#define CLK_NR_CLKS		216
80187 
81188 /*
82189  * include the CLKID and RESETID that have