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| 159 | 159 | #define CLKID_VDEC_HEVC_DIV 155 |
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| 160 | 160 | #define CLKID_GEN_CLK_SEL 157 |
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| 161 | 161 | #define CLKID_GEN_CLK_DIV 158 |
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| 162 | +#define CLKID_FIXED_PLL_DCO 160 |
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| 163 | +#define CLKID_HDMI_PLL_DCO 161 |
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| 164 | +#define CLKID_HDMI_PLL_OD 162 |
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| 165 | +#define CLKID_HDMI_PLL_OD2 163 |
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| 166 | +#define CLKID_SYS_PLL_DCO 164 |
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| 167 | +#define CLKID_GP0_PLL_DCO 165 |
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| 168 | +#define CLKID_VID_PLL_SEL 167 |
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| 169 | +#define CLKID_VID_PLL_DIV 168 |
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| 170 | +#define CLKID_VCLK_SEL 169 |
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| 171 | +#define CLKID_VCLK2_SEL 170 |
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| 172 | +#define CLKID_VCLK_INPUT 171 |
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| 173 | +#define CLKID_VCLK2_INPUT 172 |
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| 174 | +#define CLKID_VCLK_DIV 173 |
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| 175 | +#define CLKID_VCLK2_DIV 174 |
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| 176 | +#define CLKID_VCLK_DIV2_EN 177 |
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| 177 | +#define CLKID_VCLK_DIV4_EN 178 |
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| 178 | +#define CLKID_VCLK_DIV6_EN 179 |
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| 179 | +#define CLKID_VCLK_DIV12_EN 180 |
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| 180 | +#define CLKID_VCLK2_DIV2_EN 181 |
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| 181 | +#define CLKID_VCLK2_DIV4_EN 182 |
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| 182 | +#define CLKID_VCLK2_DIV6_EN 183 |
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| 183 | +#define CLKID_VCLK2_DIV12_EN 184 |
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| 184 | +#define CLKID_CTS_ENCI_SEL 195 |
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| 185 | +#define CLKID_CTS_ENCP_SEL 196 |
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| 186 | +#define CLKID_CTS_VDAC_SEL 197 |
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| 187 | +#define CLKID_HDMI_TX_SEL 198 |
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| 188 | +#define CLKID_HDMI_SEL 203 |
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| 189 | +#define CLKID_HDMI_DIV 204 |
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| 162 | 190 | |
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| 163 | | -#define NR_CLKS 160 |
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| 191 | +#define NR_CLKS 207 |
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| 164 | 192 | |
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| 165 | 193 | /* include the CLKIDs that have been made part of the DT binding */ |
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| 166 | 194 | #include <dt-bindings/clock/gxbb-clkc.h> |
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