| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Hisilicon hi6220 SoC divider clock driver |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (c) 2015 Hisilicon Limited. |
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| 5 | 6 | * |
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| 6 | 7 | * Author: Bintian Wang <bintian.wang@huawei.com> |
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| 7 | | - * |
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| 8 | | - * This program is free software; you can redistribute it and/or modify |
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| 9 | | - * it under the terms of the GNU General Public License version 2 as |
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| 10 | | - * published by the Free Software Foundation. |
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| 11 | | - * |
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| 12 | 8 | */ |
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| 13 | 9 | |
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| 14 | 10 | #include <linux/kernel.h> |
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| .. | .. |
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| 107 | 103 | { |
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| 108 | 104 | struct hi6220_clk_divider *div; |
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| 109 | 105 | struct clk *clk; |
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| 110 | | - struct clk_init_data init = {}; |
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| 106 | + struct clk_init_data init; |
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| 111 | 107 | struct clk_div_table *table; |
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| 112 | 108 | u32 max_div, min_div; |
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| 113 | 109 | int i; |
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