mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/drivers/clk/actions/owl-s700.c
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@@ -20,8 +20,10 @@
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 #include "owl-gate.h"
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 #include "owl-mux.h"
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 #include "owl-pll.h"
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+#include "owl-reset.h"
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 #include <dt-bindings/clock/actions,s700-cmu.h>
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+#include <dt-bindings/reset/actions,s700-reset.h>
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 #define CMU_COREPLL		(0x0000)
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 #define CMU_DEVPLL		(0x0004)
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@@ -160,6 +162,7 @@
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 static struct clk_div_table rmii_div_table[] = {
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 	{0, 4},   {1, 10},
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+	{0, 0}
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 };
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 /* divider clocks */
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@@ -569,20 +572,69 @@
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 		.num    = CLK_NR_CLKS,
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 };
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-static const struct owl_clk_desc s700_clk_desc = {
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+static const struct owl_reset_map s700_resets[] = {
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+	[RESET_DE]	= { CMU_DEVRST0, BIT(0) },
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+	[RESET_LCD0]	= { CMU_DEVRST0, BIT(1) },
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+	[RESET_DSI]	= { CMU_DEVRST0, BIT(2) },
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+	[RESET_CSI]	= { CMU_DEVRST0, BIT(13) },
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+	[RESET_SI]	= { CMU_DEVRST0, BIT(14) },
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+	[RESET_I2C0]	= { CMU_DEVRST1, BIT(0) },
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+	[RESET_I2C1]	= { CMU_DEVRST1, BIT(1) },
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+	[RESET_I2C2]	= { CMU_DEVRST1, BIT(2) },
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+	[RESET_I2C3]	= { CMU_DEVRST1, BIT(3) },
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+	[RESET_SPI0]	= { CMU_DEVRST1, BIT(4) },
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+	[RESET_SPI1]	= { CMU_DEVRST1, BIT(5) },
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+	[RESET_SPI2]	= { CMU_DEVRST1, BIT(6) },
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+	[RESET_SPI3]	= { CMU_DEVRST1, BIT(7) },
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+	[RESET_UART0]	= { CMU_DEVRST1, BIT(8) },
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+	[RESET_UART1]	= { CMU_DEVRST1, BIT(9) },
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+	[RESET_UART2]	= { CMU_DEVRST1, BIT(10) },
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+	[RESET_UART3]	= { CMU_DEVRST1, BIT(11) },
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+	[RESET_UART4]	= { CMU_DEVRST1, BIT(12) },
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+	[RESET_UART5]	= { CMU_DEVRST1, BIT(13) },
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+	[RESET_UART6]	= { CMU_DEVRST1, BIT(14) },
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+	[RESET_KEY]	= { CMU_DEVRST1, BIT(24) },
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+	[RESET_GPIO]	= { CMU_DEVRST1, BIT(25) },
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+	[RESET_AUDIO]	= { CMU_DEVRST1, BIT(29) },
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+};
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+
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+static struct owl_clk_desc s700_clk_desc = {
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 	.clks       = s700_clks,
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 	.num_clks   = ARRAY_SIZE(s700_clks),
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 	.hw_clks    = &s700_hw_clks,
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+
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+	.resets     = s700_resets,
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+	.num_resets = ARRAY_SIZE(s700_resets),
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 };
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 static int s700_clk_probe(struct platform_device *pdev)
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 {
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-	const struct owl_clk_desc *desc;
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+	struct owl_clk_desc *desc;
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+	struct owl_reset *reset;
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+	int ret;
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 	desc = &s700_clk_desc;
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 	owl_clk_regmap_init(pdev, desc);
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619
 
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+	/*
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+	 * FIXME: Reset controller registration should be moved to
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+	 * common code, once all SoCs of Owl family supports it.
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+	 */
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+	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
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+	if (!reset)
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+		return -ENOMEM;
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+
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+	reset->rcdev.of_node = pdev->dev.of_node;
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+	reset->rcdev.ops = &owl_reset_ops;
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+	reset->rcdev.nr_resets = desc->num_resets;
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+	reset->reset_map = desc->resets;
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+	reset->regmap = desc->regmap;
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+
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+	ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
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+	if (ret)
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+		dev_err(&pdev->dev, "Failed to register reset controller\n");
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+
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 	return owl_clk_probe(&pdev->dev, desc->hw_clks);
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 }
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